From c6a6e6e203ee9a34fa53f773272f21d48b4e3454 Mon Sep 17 00:00:00 2001 From: Abhijit Pagare Date: Tue, 26 Jan 2010 20:12:51 -0700 Subject: ARM: OMAP4: PM: OMAP4 essential basic initialisations. Some of the OMAP4 specific chip level initialisations are taken care of. Signed-off-by: Abhijit Pagare Cc: Benoit Cousson Cc: Rajendra Nayak Cc: Tony Lindgren [paul@pwsan.com: updated to use '4430ES1' rather than simply '4430'; updated to apply after the intervening cpu.h/id.c patch; thanks also to Tony for catching a bug in my rewrite] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/id.c | 1 + arch/arm/plat-omap/include/plat/cpu.h | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 3d65c50bd017..9e7c4aeeae02 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -281,6 +281,7 @@ void __init omap4_check_revision(void) if ((hawkeye == 0xb852) && (rev == 0x0)) { omap_revision = OMAP4430_REV_ES1_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES1; pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); return; } diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index a162f585b1e3..ccd78fd473d1 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -44,7 +44,7 @@ int omap_type(void); struct omap_chip_id { - u8 oc; + u16 oc; u8 type; }; @@ -154,6 +154,7 @@ unsigned int omap_rev(void); * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 * cpu_is_omap243x(): True for OMAP2430 * cpu_is_omap343x(): True for OMAP3430 + * cpu_is_omap443x(): True for OMAP4430 */ #define GET_OMAP_CLASS (omap_rev() & 0xff) @@ -286,6 +287,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) * cpu_is_omap2423(): True for OMAP2423 * cpu_is_omap2430(): True for OMAP2430 * cpu_is_omap3430(): True for OMAP3430 + * cpu_is_omap4430(): True for OMAP4430 * cpu_is_omap3505(): True for OMAP3505 * cpu_is_omap3517(): True for OMAP3517 */ @@ -334,6 +336,7 @@ IS_OMAP_TYPE(3517, 0x3517) #define cpu_is_omap3505() 0 #define cpu_is_omap3517() 0 #define cpu_is_omap3430() 0 +#define cpu_is_omap4430() 0 #define cpu_is_omap3630() 0 /* @@ -471,9 +474,12 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3430ES3_0 (1 << 5) #define CHIP_IS_OMAP3430ES3_1 (1 << 6) #define CHIP_IS_OMAP3630ES1 (1 << 7) +#define CHIP_IS_OMAP4430ES1 (1 << 8) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) +#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1) + /* * "GE" here represents "greater than or equal to" in terms of ES * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430 -- cgit v1.2.2 From 3790300903e6a98ce5f5391f4d435959266f79e7 Mon Sep 17 00:00:00 2001 From: Abhijit Pagare Date: Tue, 26 Jan 2010 20:12:51 -0700 Subject: ARM: OMAP4: PM: OMAP4 Power Domain Porting Related Clean-up. Module offsets were same for OMAP2 and OMAP3 while they differ for OMAP4. Hence we need different macros for identifying platform specific offsets. Signed-off-by: Abhijit Pagare Signed-off-by: Paul Walmsley Cc: Benoit Cousson Cc: Rajendra Nayak --- arch/arm/mach-omap2/clockdomain.c | 4 ++-- arch/arm/mach-omap2/pm-debug.c | 14 +++++++------- arch/arm/mach-omap2/pm24xx.c | 5 +++-- arch/arm/mach-omap2/pm34xx.c | 24 ++++++++++++------------ arch/arm/mach-omap2/powerdomain.c | 22 +++++++++++----------- arch/arm/mach-omap2/prcm-common.h | 9 +++++++++ arch/arm/mach-omap2/prcm.c | 17 ++++++++++++++--- arch/arm/mach-omap2/prm.h | 17 ++++++++++++----- arch/arm/mach-omap2/sleep34xx.S | 2 +- 9 files changed, 71 insertions(+), 43 deletions(-) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index dd285f001467..50c8cd7c7126 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -413,7 +413,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) if (cpu_is_omap24xx()) { cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, - clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL); + clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); } else if (cpu_is_omap34xx()) { @@ -455,7 +455,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) if (cpu_is_omap24xx()) { cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, - clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL); + clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); } else if (cpu_is_omap34xx()) { diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index a0866268aa41..03dc845c82cb 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -68,8 +68,8 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) /* MPU */ DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET); DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL); - DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL); - DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST); + DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL); + DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST); DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP); #endif #if 0 @@ -93,7 +93,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN); DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN); DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE); - DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST); + DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST); #endif #if 0 /* DSP */ @@ -104,10 +104,10 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE); DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL); DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST); } #endif } else { diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index cba05b9f041f..754381857cb6 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -219,11 +219,12 @@ static void omap2_enter_mpu_retention(void) /* Try to enter MPU retention */ prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE, - MPU_MOD, PM_PWSTCTRL); + MPU_MOD, OMAP2_PM_PWSTCTRL); } else { /* Block MPU retention */ - prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL); + prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, + OMAP2_PM_PWSTCTRL); only_idle = 1; } diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 910a7acf542d..f841a6e33611 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -685,7 +685,7 @@ static void __init omap3_iva_idle(void) prm_write_mod_reg(OMAP3430_RST1_IVA2 | OMAP3430_RST2_IVA2 | OMAP3430_RST3_IVA2, - OMAP3430_IVA2_MOD, RM_RSTCTRL); + OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Enable IVA2 clock */ cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, @@ -696,7 +696,7 @@ static void __init omap3_iva_idle(void) OMAP343X_CONTROL_IVA2_BOOTMOD); /* Un-reset IVA2 */ - prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); + prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Disable IVA2 clock */ cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); @@ -705,7 +705,7 @@ static void __init omap3_iva_idle(void) prm_write_mod_reg(OMAP3430_RST1_IVA2 | OMAP3430_RST2_IVA2 | OMAP3430_RST3_IVA2, - OMAP3430_IVA2_MOD, RM_RSTCTRL); + OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); } static void __init omap3_d2d_idle(void) @@ -728,8 +728,8 @@ static void __init omap3_d2d_idle(void) /* reset modem */ prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, - CORE_MOD, RM_RSTCTRL); - prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); + CORE_MOD, OMAP2_RM_RSTCTRL); + prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); } static void __init prcm_setup_regs(void) @@ -916,13 +916,13 @@ static void __init prcm_setup_regs(void) prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); /* Clear any pending 'reset' flags */ - prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); + prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); + prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); + prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); + prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); + prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); + prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); + prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); /* Clear any pending PRCM interrupts */ prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 26b3f3ee82a3..e503050dda06 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -710,7 +710,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, (pwrst << OMAP_POWERSTATE_SHIFT), - pwrdm->prcm_offs, PM_PWSTCTRL); + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); return 0; } @@ -728,7 +728,7 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm) if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTCTRL, + return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, OMAP_POWERSTATE_MASK); } @@ -745,7 +745,7 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm) if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, + return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, OMAP_POWERSTATEST_MASK); } @@ -796,7 +796,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) */ prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE, (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)), - pwrdm->prcm_offs, PM_PWSTCTRL); + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); return 0; } @@ -856,7 +856,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) } prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, PM_PWSTCTRL); + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); return 0; } @@ -917,7 +917,7 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) } prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, - PM_PWSTCTRL); + OMAP2_PM_PWSTCTRL); return 0; } @@ -936,7 +936,7 @@ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, + return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, OMAP3430_LOGICSTATEST); } @@ -1010,7 +1010,7 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) return -EEXIST; } - return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, m); + return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, m); } /** @@ -1114,7 +1114,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) pwrdm->name); prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, - pwrdm->prcm_offs, PM_PWSTCTRL); + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); return 0; } @@ -1142,7 +1142,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) pwrdm->name); prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, - pwrdm->prcm_offs, PM_PWSTCTRL); + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); return 0; } @@ -1183,7 +1183,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) */ /* XXX Is this udelay() value meaningful? */ - while ((prm_read_mod_reg(pwrdm->prcm_offs, PM_PWSTST) & + while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & OMAP_INTRANSITION) && (c++ < PWRDM_TRANSITION_BAILOUT)) udelay(1); diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 61ac2a418bd0..90f603d434c6 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -119,6 +119,15 @@ #define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400 #define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800 +/* Base Addresses for the OMAP4 */ + +#define OMAP4430_CM1_BASE 0x4a004000 +#define OMAP4430_CM2_BASE 0x4a008000 +#define OMAP4430_PRM_BASE 0x4a306000 +#define OMAP4430_SCRM_BASE 0x4a30a000 +#define OMAP4430_CHIRONSS_BASE 0x48243000 + + /* 24XX register bits shared between CM & PRM registers */ /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index cf466ea1dffc..b4ba14974b37 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -11,6 +11,7 @@ * Rajendra Nayak * * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. + * Upgraded with OMAP4 support by Abhijit Pagare * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -121,7 +122,10 @@ struct omap3_prcm_regs prcm_context; u32 omap_prcm_get_reset_sources(void) { /* XXX This presumably needs modification for 34XX */ - return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f; + if (cpu_is_omap24xx() | cpu_is_omap34xx()) + return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; + if (cpu_is_omap44xx()) + return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; } EXPORT_SYMBOL(omap_prcm_get_reset_sources); @@ -144,10 +148,17 @@ void omap_prcm_arch_reset(char mode) * cf. OMAP34xx TRM, Initialization / Software Booting * Configuration. */ omap_writel(l, OMAP343X_SCRATCHPAD + 4); - } else + } else if (cpu_is_omap44xx()) + prcm_offs = OMAP4430_PRM_DEVICE_MOD; + else WARN_ON(1); - prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); + if (cpu_is_omap24xx() | cpu_is_omap34xx()) + prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, + OMAP2_RM_RSTCTRL); + if (cpu_is_omap44xx()) + prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, + OMAP4_RM_RSTCTRL); } static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 40f006285163..5fba2aa8932c 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -179,9 +179,11 @@ /* Registers appearing on both 24xx and 34xx */ -#define RM_RSTCTRL 0x0050 -#define RM_RSTTIME 0x0054 -#define RM_RSTST 0x0058 +#define OMAP2_RM_RSTCTRL 0x0050 +#define OMAP2_RM_RSTTIME 0x0054 +#define OMAP2_RM_RSTST 0x0058 +#define OMAP2_PM_PWSTCTRL 0x00e0 +#define OMAP2_PM_PWSTST 0x00e4 #define PM_WKEN 0x00a0 #define PM_WKEN1 PM_WKEN @@ -191,8 +193,6 @@ #define PM_EVGENCTRL 0x00d4 #define PM_EVGENONTIM 0x00d8 #define PM_EVGENOFFTIM 0x00dc -#define PM_PWSTCTRL 0x00e0 -#define PM_PWSTST 0x00e4 /* Omap2 specific registers */ #define OMAP24XX_PM_WKEN2 0x00a4 @@ -220,6 +220,13 @@ #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc +/* Omap4 specific registers */ +#define OMAP4_RM_RSTCTRL 0x0000 +#define OMAP4_RM_RSTTIME 0x0004 +#define OMAP4_RM_RSTST 0x0008 +#define OMAP4_PM_PWSTCTRL 0x0000 +#define OMAP4_PM_PWSTST 0x0004 + #ifndef __ASSEMBLER__ diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index c3626ea48143..22fcc14e63be 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -38,7 +38,7 @@ #define PM_PREPWSTST_CORE_P 0x48306AE8 #define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ OMAP3430_PM_PREPWSTST) -#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL +#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) #define SRAM_BASE_P 0x40200000 #define CONTROL_STAT 0x480022F0 -- cgit v1.2.2 From f37c6dfac99451b8babdd320d7aed4e03d51b94b Mon Sep 17 00:00:00 2001 From: Abhijit Pagare Date: Tue, 26 Jan 2010 20:12:52 -0700 Subject: ARM: OMAP4: PM: Add the Autogenerated OMAP4 specific power domain framework. The Autogenerated OMAP4 power domain specific file (mach-omap2/powerdomains44xx.h) is added here. This file is auto-generated using python scripting and following is the list of the people involved: Paul Walmsley Benoit Cousson Abhijit Pagare Signed-off-by: Abhijit Pagare Signed-off-by: Paul Walmsley Signed-off-by: Benoit Cousson Signed-off-by: Rajendra Nayak --- arch/arm/mach-omap2/powerdomains44xx.h | 310 ++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/powerdomain.h | 3 + 2 files changed, 313 insertions(+) create mode 100644 arch/arm/mach-omap2/powerdomains44xx.h diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h new file mode 100644 index 000000000000..c1015147d579 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains44xx.h @@ -0,0 +1,310 @@ +/* + * OMAP4 Power domains framework + * + * Copyright (C) 2009 Texas Instruments, Inc. + * Copyright (C) 2009 Nokia Corporation + * + * Abhijit Pagare (abhijitpagare@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Paul Walmsley + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H +#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H + +#include + +#include "prcm-common.h" +#include "cm.h" +#include "cm-regbits-44xx.h" +#include "prm.h" +#include "prm-regbits-44xx.h" + +#if defined(CONFIG_ARCH_OMAP4) + +/* core_44xx_pwrdm: CORE power domain */ +static struct powerdomain core_44xx_pwrdm = { + .name = "core_pwrdm", + .prcm_offs = OMAP4430_PRM_CORE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 5, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRDM_POWER_RET, /* core_other_bank */ + [3] = PWRSTS_OFF_RET, /* ducati_l2ram */ + [4] = PWRSTS_OFF_RET, /* ducati_unicache */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRDM_POWER_ON, /* core_other_bank */ + [3] = PWRDM_POWER_ON, /* ducati_l2ram */ + [4] = PWRDM_POWER_ON, /* ducati_unicache */ + }, +}; + +/* gfx_44xx_pwrdm: 3D accelerator power domain */ +static struct powerdomain gfx_44xx_pwrdm = { + .name = "gfx_pwrdm", + .prcm_offs = OMAP4430_PRM_GFX_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* gfx_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* gfx_mem */ + }, +}; + +/* abe_44xx_pwrdm: Audio back end power domain */ +static struct powerdomain abe_44xx_pwrdm = { + .name = "abe_pwrdm", + .prcm_offs = OMAP4430_PRM_ABE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_OFF, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* aessmem */ + [1] = PWRDM_POWER_OFF, /* periphmem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* aessmem */ + [1] = PWRDM_POWER_ON, /* periphmem */ + }, +}; + +/* dss_44xx_pwrdm: Display subsystem power domain */ +static struct powerdomain dss_44xx_pwrdm = { + .name = "dss_pwrdm", + .prcm_offs = OMAP4430_PRM_DSS_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* dss_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* dss_mem */ + }, +}; + +/* tesla_44xx_pwrdm: Tesla processor power domain */ +static struct powerdomain tesla_44xx_pwrdm = { + .name = "tesla_pwrdm", + .prcm_offs = OMAP4430_PRM_TESLA_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* tesla_edma */ + [1] = PWRSTS_OFF_RET, /* tesla_l1 */ + [2] = PWRSTS_OFF_RET, /* tesla_l2 */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* tesla_edma */ + [1] = PWRDM_POWER_ON, /* tesla_l1 */ + [2] = PWRDM_POWER_ON, /* tesla_l2 */ + }, +}; + +/* wkup_44xx_pwrdm: Wake-up power domain */ +static struct powerdomain wkup_44xx_pwrdm = { + .name = "wkup_pwrdm", + .prcm_offs = OMAP4430_PRM_WKUP_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRDM_POWER_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* wkup_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* wkup_bank */ + }, +}; + +/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ +static struct powerdomain cpu0_44xx_pwrdm = { + .name = "cpu0_pwrdm", + .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* cpu0_l1 */ + }, +}; + +/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ +static struct powerdomain cpu1_44xx_pwrdm = { + .name = "cpu1_pwrdm", + .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* cpu1_l1 */ + }, +}; + +/* emu_44xx_pwrdm: Emulation power domain */ +static struct powerdomain emu_44xx_pwrdm = { + .name = "emu_pwrdm", + .prcm_offs = OMAP4430_PRM_EMU_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* emu_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* emu_bank */ + }, +}; + +/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */ +static struct powerdomain mpu_44xx_pwrdm = { + .name = "mpu_pwrdm", + .prcm_offs = OMAP4430_PRM_MPU_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* mpu_l1 */ + [1] = PWRSTS_OFF_RET, /* mpu_l2 */ + [2] = PWRDM_POWER_RET, /* mpu_ram */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* mpu_l1 */ + [1] = PWRDM_POWER_ON, /* mpu_l2 */ + [2] = PWRDM_POWER_ON, /* mpu_ram */ + }, +}; + +/* ivahd_44xx_pwrdm: IVA-HD power domain */ +static struct powerdomain ivahd_44xx_pwrdm = { + .name = "ivahd_pwrdm", + .prcm_offs = OMAP4430_PRM_IVAHD_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_OFF, + .banks = 4, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* hwa_mem */ + [1] = PWRSTS_OFF_RET, /* sl2_mem */ + [2] = PWRSTS_OFF_RET, /* tcm1_mem */ + [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* hwa_mem */ + [1] = PWRDM_POWER_ON, /* sl2_mem */ + [2] = PWRDM_POWER_ON, /* tcm1_mem */ + [3] = PWRDM_POWER_ON, /* tcm2_mem */ + }, +}; + +/* cam_44xx_pwrdm: Camera subsystem power domain */ +static struct powerdomain cam_44xx_pwrdm = { + .name = "cam_pwrdm", + .prcm_offs = OMAP4430_PRM_CAM_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* cam_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* cam_mem */ + }, +}; + +/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ +static struct powerdomain l3init_44xx_pwrdm = { + .name = "l3init_pwrdm", + .prcm_offs = OMAP4430_PRM_L3INIT_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* l3init_bank1 */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* l3init_bank1 */ + }, +}; + +/* l4per_44xx_pwrdm: Target peripherals power domain */ +static struct powerdomain l4per_44xx_pwrdm = { + .name = "l4per_pwrdm", + .prcm_offs = OMAP4430_PRM_L4PER_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* nonretained_bank */ + [1] = PWRDM_POWER_RET, /* retained_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* nonretained_bank */ + [1] = PWRDM_POWER_ON, /* retained_bank */ + }, +}; + +/* + * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage + * domain + */ +static struct powerdomain always_on_core_44xx_pwrdm = { + .name = "always_on_core_pwrdm", + .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRDM_POWER_ON, +}; + +/* cefuse_44xx_pwrdm: Customer efuse controller power domain */ +static struct powerdomain cefuse_44xx_pwrdm = { + .name = "cefuse_pwrdm", + .prcm_offs = OMAP4430_PRM_CEFUSE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_ON, +}; + +/* + * The following power domains are not under SW control + * + * always_on_iva + * always_on_mpu + * stdefuse + */ + +#endif + +#endif diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index 0b960051eaed..2510005e5ef0 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h @@ -37,6 +37,9 @@ #define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ (1 << PWRDM_POWER_RET)) +#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ + (1 << PWRDM_POWER_ON)) + #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) -- cgit v1.2.2 From 38900c27fbbbe97e16f448b8bc9cafc05af03460 Mon Sep 17 00:00:00 2001 From: Abhijit Pagare Date: Tue, 26 Jan 2010 20:12:52 -0700 Subject: ARM: OMAP4: PM: Adapt the existing OMAP2/3 and common Power Domain Frameworks. Taking care of the platform specific and common power domains with proper checks. Also refining some Macros according to the latest OMAP4 requirements. Signed-off-by: Abhijit Pagare Signed-off-by: Paul Walmsley Cc: Benoit Cousson Cc: Rajendra Nayak --- arch/arm/mach-omap2/powerdomains.h | 40 ++++++++++++++++++++++++--- arch/arm/plat-omap/include/plat/powerdomain.h | 10 +++---- 2 files changed, 41 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h index 057b2e3e2c35..d646c9979c38 100644 --- a/arch/arm/mach-omap2/powerdomains.h +++ b/arch/arm/mach-omap2/powerdomains.h @@ -12,6 +12,12 @@ * published by the Free Software Foundation. */ +/* + * To Do List + * -> Move the Sleep/Wakeup dependencies from Power Domain framework to + * Clock Domain Framework + */ + #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS @@ -71,6 +77,7 @@ /* OMAP2/3-common powerdomains and wakeup dependencies */ +#ifndef CONFIG_ARCH_OMAP4 /* * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE @@ -110,21 +117,25 @@ static struct pwrdm_dep cam_gfx_sleepdeps[] = { }, { NULL }, }; +#endif #include "powerdomains24xx.h" #include "powerdomains34xx.h" +#include "powerdomains44xx.h" /* * OMAP2/3 common powerdomains */ +#if defined(CONFIG_ARCH_OMAP24XX) | defined(CONFIG_ARCH_OMAP34XX) + /* * The GFX powerdomain is not present on 3430ES2, but currently we do not * have a macro to filter it out at compile-time. */ -static struct powerdomain gfx_pwrdm = { +static struct powerdomain gfx_omap2_pwrdm = { .name = "gfx_pwrdm", .prcm_offs = GFX_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | @@ -142,20 +153,23 @@ static struct powerdomain gfx_pwrdm = { }, }; -static struct powerdomain wkup_pwrdm = { +static struct powerdomain wkup_omap2_pwrdm = { .name = "wkup_pwrdm", .prcm_offs = WKUP_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), .dep_bit = OMAP_EN_WKUP_SHIFT, }; +#endif /* As powerdomains are added or removed above, this list must also be changed */ static struct powerdomain *powerdomains_omap[] __initdata = { - &gfx_pwrdm, - &wkup_pwrdm, +#if defined(CONFIG_ARCH_OMAP24XX) | defined(CONFIG_ARCH_OMAP34XX) + &wkup_omap2_pwrdm, + &gfx_omap2_pwrdm, +#endif #ifdef CONFIG_ARCH_OMAP24XX &dsp_pwrdm, @@ -186,6 +200,24 @@ static struct powerdomain *powerdomains_omap[] __initdata = { &dpll5_pwrdm, #endif +#ifdef CONFIG_ARCH_OMAP4 + &core_44xx_pwrdm, + &gfx_44xx_pwrdm, + &abe_44xx_pwrdm, + &dss_44xx_pwrdm, + &tesla_44xx_pwrdm, + &wkup_44xx_pwrdm, + &cpu0_44xx_pwrdm, + &cpu1_44xx_pwrdm, + &emu_44xx_pwrdm, + &mpu_44xx_pwrdm, + &ivahd_44xx_pwrdm, + &cam_44xx_pwrdm, + &l3init_44xx_pwrdm, + &l4per_44xx_pwrdm, + &always_on_core_44xx_pwrdm, + &cefuse_44xx_pwrdm, +#endif NULL }; diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index 2510005e5ef0..bac378eff8df 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h @@ -51,16 +51,16 @@ */ /* - * Number of memory banks that are power-controllable. On OMAP3430, the - * maximum is 4. + * Number of memory banks that are power-controllable. On OMAP4430, the + * maximum is 5. */ -#define PWRDM_MAX_MEM_BANKS 4 +#define PWRDM_MAX_MEM_BANKS 5 /* * Maximum number of clockdomains that can be associated with a powerdomain. - * CORE powerdomain on OMAP3 is the worst case + * CORE powerdomain on OMAP4 is the worst case */ -#define PWRDM_MAX_CLKDMS 4 +#define PWRDM_MAX_CLKDMS 9 /* XXX A completely arbitrary number. What is reasonable here? */ #define PWRDM_TRANSITION_BAILOUT 100000 -- cgit v1.2.2 From 3a759f09d7b9c6bbefffadd38fdc116125c49730 Mon Sep 17 00:00:00 2001 From: Abhijit Pagare Date: Tue, 26 Jan 2010 20:12:53 -0700 Subject: ARM: OMAP4: PM: Refine the APIs to support OMAP4 features. The proper Macros have to be used for platform specific calls and some of the compiling requirements and init calls are taken care of. Signed-off-by: Abhijit Pagare Signed-off-by: Paul Walmsley Cc: Benoit Cousson Cc: Rajendra Nayak --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/io.c | 2 +- arch/arm/mach-omap2/powerdomain.c | 112 +++++++++++++++++++++++++++++--------- 3 files changed, 87 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b32678b848bc..4a54e5afbac5 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -13,7 +13,7 @@ clock-common = clock.o clock_common_data.o clockdomain.o obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ $(omap-3-4-common) -obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) $(prcm-common) clock.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 5a7996402c53..aa237ff644d6 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -312,12 +312,12 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, else if (cpu_is_omap34xx()) hwmods = omap34xx_hwmods; + pwrdm_init(powerdomains_omap); #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ /* The OPP tables have to be registered before a clk init */ omap_hwmod_init(hwmods); omap2_mux_init(); omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); - pwrdm_init(powerdomains_omap); clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); #endif omap2_clk_init(); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index e503050dda06..c0de05097b5d 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -6,6 +6,8 @@ * * Written by Paul Walmsley * + * Added OMAP4 specific support by Abhijit Pagare + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -26,8 +28,10 @@ #include "cm.h" #include "cm-regbits-34xx.h" +#include "cm-regbits-44xx.h" #include "prm.h" #include "prm-regbits-34xx.h" +#include "prm-regbits-44xx.h" #include #include @@ -40,6 +44,38 @@ enum { PWRDM_STATE_PREV, }; +/* Variable holding value of the CPU dependent PWRSTCTRL Register Offset */ +static u16 pwrstctrl_reg_offs; + +/* Variable holding value of the CPU dependent PWRSTST Register Offset */ +static u16 pwrstst_reg_offs; + +/* OMAP3 and OMAP4 specific register bit initialisations + * Notice that the names here are not according to each power + * domain but the bit mapping used applies to all of them + */ + +/* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */ +#define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK +#define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK +#define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK +#define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK +#define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK + +/* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ +#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE +#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE +#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE +#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE +#define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK + +/* OMAP3 and OMAP4 Memory Status bits */ +#define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK +#define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK +#define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK +#define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK +#define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK + /* pwrdm_list contains all registered struct powerdomains */ static LIST_HEAD(pwrdm_list); @@ -181,6 +217,18 @@ void pwrdm_init(struct powerdomain **pwrdm_list) { struct powerdomain **p = NULL; + if (cpu_is_omap24xx() | cpu_is_omap34xx()) { + pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL; + pwrstst_reg_offs = OMAP2_PM_PWSTST; + } else if (cpu_is_omap44xx()) { + pwrstctrl_reg_offs = OMAP4_PM_PWSTCTRL; + pwrstst_reg_offs = OMAP4_PM_PWSTST; + } else { + printk(KERN_ERR "Power Domain struct not supported for " \ + "this CPU\n"); + return; + } + if (pwrdm_list) { for (p = pwrdm_list; *p; p++) { pwrdm_register(*p); @@ -710,7 +758,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, (pwrst << OMAP_POWERSTATE_SHIFT), - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + pwrdm->prcm_offs, pwrstctrl_reg_offs); return 0; } @@ -728,8 +776,8 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm) if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, - OMAP_POWERSTATE_MASK); + return prm_read_mod_bits_shift(pwrdm->prcm_offs, + pwrstctrl_reg_offs, OMAP_POWERSTATE_MASK); } /** @@ -745,8 +793,8 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm) if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, - OMAP_POWERSTATEST_MASK); + return prm_read_mod_bits_shift(pwrdm->prcm_offs, + pwrstst_reg_offs, OMAP_POWERSTATEST_MASK); } /** @@ -796,7 +844,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) */ prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE, (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)), - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + pwrdm->prcm_offs, pwrstctrl_reg_offs); return 0; } @@ -839,16 +887,19 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) */ switch (bank) { case 0: - m = OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK; + m = OMAP_MEM0_ONSTATE_MASK; break; case 1: - m = OMAP3430_L1FLATMEMONSTATE_MASK; + m = OMAP_MEM1_ONSTATE_MASK; break; case 2: - m = OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK; + m = OMAP_MEM2_ONSTATE_MASK; break; case 3: - m = OMAP3430_L2FLATMEMONSTATE_MASK; + m = OMAP_MEM3_ONSTATE_MASK; + break; + case 4: + m = OMAP_MEM4_ONSTATE_MASK; break; default: WARN_ON(1); /* should never happen */ @@ -856,7 +907,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) } prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + pwrdm->prcm_offs, pwrstctrl_reg_offs); return 0; } @@ -900,16 +951,19 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) */ switch (bank) { case 0: - m = OMAP3430_SHAREDL1CACHEFLATRETSTATE; + m = OMAP_MEM0_RETSTATE_MASK; break; case 1: - m = OMAP3430_L1FLATMEMRETSTATE; + m = OMAP_MEM1_RETSTATE_MASK; break; case 2: - m = OMAP3430_SHAREDL2CACHEFLATRETSTATE; + m = OMAP_MEM2_RETSTATE_MASK; break; case 3: - m = OMAP3430_L2FLATMEMRETSTATE; + m = OMAP_MEM3_RETSTATE_MASK; + break; + case 4: + m = OMAP_MEM4_RETSTATE_MASK; break; default: WARN_ON(1); /* should never happen */ @@ -917,7 +971,7 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) } prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL); + pwrstctrl_reg_offs); return 0; } @@ -936,8 +990,8 @@ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, - OMAP3430_LOGICSTATEST); + return prm_read_mod_bits_shift(pwrdm->prcm_offs, + pwrstst_reg_offs, OMAP3430_LOGICSTATEST); } /** @@ -994,23 +1048,27 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) */ switch (bank) { case 0: - m = OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK; + m = OMAP_MEM0_STATEST_MASK; break; case 1: - m = OMAP3430_L1FLATMEMSTATEST_MASK; + m = OMAP_MEM1_STATEST_MASK; break; case 2: - m = OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK; + m = OMAP_MEM2_STATEST_MASK; break; case 3: - m = OMAP3430_L2FLATMEMSTATEST_MASK; + m = OMAP_MEM3_STATEST_MASK; + break; + case 4: + m = OMAP_MEM4_STATEST_MASK; break; default: WARN_ON(1); /* should never happen */ return -EEXIST; } - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, m); + return prm_read_mod_bits_shift(pwrdm->prcm_offs, + pwrstst_reg_offs, m); } /** @@ -1114,7 +1172,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) pwrdm->name); prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + pwrdm->prcm_offs, pwrstctrl_reg_offs); return 0; } @@ -1142,7 +1200,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) pwrdm->name); prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + pwrdm->prcm_offs, pwrstctrl_reg_offs); return 0; } @@ -1183,10 +1241,10 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) */ /* XXX Is this udelay() value meaningful? */ - while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & + while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) & OMAP_INTRANSITION) && (c++ < PWRDM_TRANSITION_BAILOUT)) - udelay(1); + udelay(1); if (c > PWRDM_TRANSITION_BAILOUT) { printk(KERN_ERR "powerdomain: waited too long for " -- cgit v1.2.2 From 84c0c39aec31a09571fc08a752a2f4da0fe9fcf2 Mon Sep 17 00:00:00 2001 From: Abhijit Pagare Date: Tue, 26 Jan 2010 20:12:53 -0700 Subject: ARM: OMAP4: PM: Make OMAP3 Clock-domain framework compatible for OMAP4. Here the ".clkstctrl_reg" field is added to the clockdomain stucture as the module offsets for OMAP4 do not map one to one for powerdomains and clockdomains as it used to for OMAP3. Hence we need to use absolute addresses to access the control registers. Some of the clock domains have modules falling in the address space of PRM partition. Hence necessitating the use of absolute adresses. Signed-off-by: Abhijit Pagare Signed-off-by: Paul Walmsley Cc: Benoit Cousson Cc: Rajendra Nayak --- arch/arm/mach-omap2/clockdomain.c | 12 ++- arch/arm/mach-omap2/clockdomains.h | 133 ++++++++++++++++++++------ arch/arm/mach-omap2/cm.h | 5 +- arch/arm/mach-omap2/pm-debug.c | 4 +- arch/arm/mach-omap2/prcm.c | 43 +++++---- arch/arm/plat-omap/include/plat/clockdomain.h | 3 + 6 files changed, 142 insertions(+), 58 deletions(-) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 50c8cd7c7126..52885ac5bb5d 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -163,7 +163,7 @@ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable) cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v << __ffs(clkdm->clktrctrl_mask), - clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); + clkdm->pwrdm.ptr->prcm_offs, OMAP2_CM_CLKSTCTRL); } static struct clockdomain *_clkdm_lookup(const char *name) @@ -371,7 +371,7 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm) * @clk: struct clk * of a clockdomain * * Return the clockdomain's current state transition mode from the - * corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if clk + * corresponding domain OMAP2_CM_CLKSTCTRL register. Returns -EINVAL if clk * is NULL or the current mode upon success. */ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) @@ -381,7 +381,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) if (!clkdm) return -EINVAL; - v = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); + v = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, OMAP2_CM_CLKSTCTRL); v &= clkdm->clktrctrl_mask; v >>= __ffs(clkdm->clktrctrl_mask); @@ -421,7 +421,8 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) __ffs(clkdm->clktrctrl_mask)); cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, - clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); + clkdm->pwrdm.ptr->prcm_offs, + OMAP2_CM_CLKSTCTRL); } else { BUG(); @@ -463,7 +464,8 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) __ffs(clkdm->clktrctrl_mask)); cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, - clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); + clkdm->pwrdm.ptr->prcm_offs, + OMAP2_CM_CLKSTCTRL); } else { BUG(); diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h index c4ee0761d908..0e6114058db5 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains.h @@ -11,6 +11,8 @@ #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H #include +#include "cm.h" +#include "prm44xx.h" /* * OMAP2/3-common clockdomains @@ -50,6 +52,7 @@ static struct clockdomain mpu_2420_clkdm = { .name = "mpu_clkdm", .pwrdm = { .name = "mpu_pwrdm" }, .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; @@ -58,11 +61,59 @@ static struct clockdomain iva1_2420_clkdm = { .name = "iva1_clkdm", .pwrdm = { .name = "dsp_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; -#endif /* CONFIG_ARCH_OMAP2420 */ +static struct clockdomain dsp_2420_clkdm = { + .name = "dsp_clkdm", + .pwrdm = { .name = "dsp_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD, + OMAP2_CM_CLKSTCTRL), + .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +static struct clockdomain gfx_2420_clkdm = { + .name = "gfx_clkdm", + .pwrdm = { .name = "gfx_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), + .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +static struct clockdomain core_l3_2420_clkdm = { + .name = "core_l3_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), + .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +static struct clockdomain core_l4_2420_clkdm = { + .name = "core_l4_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), + .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +static struct clockdomain dss_2420_clkdm = { + .name = "dss_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), + .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +#endif /* CONFIG_ARCH_OMAP2420 */ /* @@ -75,6 +126,8 @@ static struct clockdomain mpu_2430_clkdm = { .name = "mpu_clkdm", .pwrdm = { .name = "mpu_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(MPU_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; @@ -83,60 +136,59 @@ static struct clockdomain mdm_clkdm = { .name = "mdm_clkdm", .pwrdm = { .name = "mdm_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -#endif /* CONFIG_ARCH_OMAP2430 */ - - -/* - * 24XX-only clockdomains - */ - -#if defined(CONFIG_ARCH_OMAP24XX) - -static struct clockdomain dsp_clkdm = { +static struct clockdomain dsp_2430_clkdm = { .name = "dsp_clkdm", .pwrdm = { .name = "dsp_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -static struct clockdomain gfx_24xx_clkdm = { +static struct clockdomain gfx_2430_clkdm = { .name = "gfx_clkdm", .pwrdm = { .name = "gfx_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -static struct clockdomain core_l3_24xx_clkdm = { +static struct clockdomain core_l3_2430_clkdm = { .name = "core_l3_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -static struct clockdomain core_l4_24xx_clkdm = { +static struct clockdomain core_l4_2430_clkdm = { .name = "core_l4_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -static struct clockdomain dss_24xx_clkdm = { +static struct clockdomain dss_2430_clkdm = { .name = "dss_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -#endif /* CONFIG_ARCH_OMAP24XX */ +#endif /* CONFIG_ARCH_OMAP2430 */ /* @@ -149,6 +201,7 @@ static struct clockdomain mpu_34xx_clkdm = { .name = "mpu_clkdm", .pwrdm = { .name = "mpu_pwrdm" }, .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -157,6 +210,8 @@ static struct clockdomain neon_clkdm = { .name = "neon_clkdm", .pwrdm = { .name = "neon_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -165,6 +220,8 @@ static struct clockdomain iva2_clkdm = { .name = "iva2_clkdm", .pwrdm = { .name = "iva2_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -173,6 +230,7 @@ static struct clockdomain gfx_3430es1_clkdm = { .name = "gfx_clkdm", .pwrdm = { .name = "gfx_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), }; @@ -181,6 +239,8 @@ static struct clockdomain sgx_clkdm = { .name = "sgx_clkdm", .pwrdm = { .name = "sgx_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), }; @@ -196,6 +256,7 @@ static struct clockdomain d2d_clkdm = { .name = "d2d_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -204,6 +265,7 @@ static struct clockdomain core_l3_34xx_clkdm = { .name = "core_l3_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -212,6 +274,7 @@ static struct clockdomain core_l4_34xx_clkdm = { .name = "core_l4_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -220,6 +283,8 @@ static struct clockdomain dss_34xx_clkdm = { .name = "dss_clkdm", .pwrdm = { .name = "dss_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -228,6 +293,8 @@ static struct clockdomain cam_clkdm = { .name = "cam_clkdm", .pwrdm = { .name = "cam_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -236,6 +303,8 @@ static struct clockdomain usbhost_clkdm = { .name = "usbhost_clkdm", .pwrdm = { .name = "usbhost_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), }; @@ -244,6 +313,8 @@ static struct clockdomain per_clkdm = { .name = "per_clkdm", .pwrdm = { .name = "per_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -256,6 +327,8 @@ static struct clockdomain emu_clkdm = { .name = "emu_clkdm", .pwrdm = { .name = "emu_pwrdm" }, .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -323,19 +396,21 @@ static struct clockdomain *clockdomains_omap[] = { #ifdef CONFIG_ARCH_OMAP2420 &mpu_2420_clkdm, &iva1_2420_clkdm, + &dsp_2420_clkdm, + &gfx_2420_clkdm, + &core_l3_2420_clkdm, + &core_l4_2420_clkdm, + &dss_2420_clkdm, #endif #ifdef CONFIG_ARCH_OMAP2430 &mpu_2430_clkdm, &mdm_clkdm, -#endif - -#ifdef CONFIG_ARCH_OMAP24XX - &dsp_clkdm, - &gfx_24xx_clkdm, - &core_l3_24xx_clkdm, - &core_l4_24xx_clkdm, - &dss_24xx_clkdm, + &dsp_2430_clkdm, + &gfx_2430_clkdm, + &core_l3_2430_clkdm, + &core_l4_2430_clkdm, + &dss_2430_clkdm, #endif #ifdef CONFIG_ARCH_OMAP34XX diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index 90a4086fbdf4..4e4ac8ccd7f5 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -67,7 +67,8 @@ #define CM_CLKSEL 0x0040 #define CM_CLKSEL1 CM_CLKSEL #define CM_CLKSEL2 0x0044 -#define CM_CLKSTCTRL 0x0048 +#define OMAP2_CM_CLKSTCTRL 0x0048 +#define OMAP4_CM_CLKSTCTRL 0x0000 /* Architecture-specific registers */ @@ -88,7 +89,7 @@ #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 -#define OMAP3430_CM_CLKSEL3 CM_CLKSTCTRL +#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL #define OMAP3430_CM_CLKSTST 0x004c #define OMAP3430ES2_CM_CLKSEL4 0x004c #define OMAP3430ES2_CM_CLKSEL5 0x0050 diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 03dc845c82cb..5b6ae1e88e01 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -67,7 +67,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) #if 0 /* MPU */ DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET); - DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL); + DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL); DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL); DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST); DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP); @@ -103,7 +103,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST); DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE); DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL); - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL); + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL); DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL); DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST); DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL); diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index b4ba14974b37..82ad8f8ad83a 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -291,7 +291,7 @@ void omap3_prcm_save_context(void) prcm_context.emu_cm_clksel = cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); prcm_context.emu_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.pll_cm_autoidle2 = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); prcm_context.pll_cm_clksel4 = @@ -344,23 +344,25 @@ void omap3_prcm_save_context(void) prcm_context.mpu_cm_autoidle2 = cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); prcm_context.iva2_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.mpu_cm_clkstctrl = - cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.core_cm_clkstctrl = - cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.sgx_cm_clkstctrl = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430ES2_SGX_MOD, + OMAP2_CM_CLKSTCTRL); prcm_context.dss_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.cam_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.per_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.neon_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.usbhost_cm_clkstctrl = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, + OMAP2_CM_CLKSTCTRL); prcm_context.core_cm_autoidle1 = cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); prcm_context.core_cm_autoidle2 = @@ -443,7 +445,7 @@ void omap3_prcm_restore_context(void) cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD, CM_CLKSEL1); cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD, CM_AUTOIDLE2); cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD, @@ -489,22 +491,23 @@ void omap3_prcm_restore_context(void) CM_AUTOIDLE2); cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, - CM_CLKSTCTRL); - cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); + cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl, - OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL); + OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD, CM_AUTOIDLE1); cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD, diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h index eb734826e64e..4806e2c52c11 100644 --- a/arch/arm/plat-omap/include/plat/clockdomain.h +++ b/arch/arm/plat-omap/include/plat/clockdomain.h @@ -74,6 +74,9 @@ struct clockdomain { struct powerdomain *ptr; } pwrdm; + /* CLKSTCTRL reg for the given clock domain*/ + void __iomem *clkstctrl_reg; + /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */ const u16 clktrctrl_mask; -- cgit v1.2.2 From b099474aa4e7fbaf5dc3b5858bc83dee2f94c60f Mon Sep 17 00:00:00 2001 From: Abhijit Pagare Date: Tue, 26 Jan 2010 20:12:53 -0700 Subject: ARM: OMAP4: PM: Modify Clock-domain interfaces for OMAP4 compatibility. Here the APIs are modified to use absolute addresses instead of module offsets. Signed-off-by: Abhijit Pagare Signed-off-by: Paul Walmsley Cc: Benoit Cousson Cc: Rajendra Nayak --- arch/arm/mach-omap2/clockdomain.c | 44 ++++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 52885ac5bb5d..5366a10d8597 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -145,25 +145,29 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm) */ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable) { - u32 v; + u32 bits, v; if (cpu_is_omap24xx()) { if (enable) - v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO; + bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO; else - v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO; + bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO; } else if (cpu_is_omap34xx()) { if (enable) - v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO; + bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO; else - v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO; + bits = OMAP34XX_CLKSTCTRL_DISABLE_AUTO; } else { BUG(); } - cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, - v << __ffs(clkdm->clktrctrl_mask), - clkdm->pwrdm.ptr->prcm_offs, OMAP2_CM_CLKSTCTRL); + bits = bits << __ffs(clkdm->clktrctrl_mask); + + v = __raw_readl(clkdm->clkstctrl_reg); + v &= ~(clkdm->clktrctrl_mask); + v |= bits; + __raw_writel(v, clkdm->clkstctrl_reg); + } static struct clockdomain *_clkdm_lookup(const char *name) @@ -381,7 +385,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) if (!clkdm) return -EINVAL; - v = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, OMAP2_CM_CLKSTCTRL); + v = __raw_readl(clkdm->clkstctrl_reg); v &= clkdm->clktrctrl_mask; v >>= __ffs(clkdm->clktrctrl_mask); @@ -417,12 +421,13 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) } else if (cpu_is_omap34xx()) { - u32 v = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP << + u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP << __ffs(clkdm->clktrctrl_mask)); - cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, - clkdm->pwrdm.ptr->prcm_offs, - OMAP2_CM_CLKSTCTRL); + u32 v = __raw_readl(clkdm->clkstctrl_reg); + v &= ~(clkdm->clktrctrl_mask); + v |= bits; + __raw_writel(v, clkdm->clkstctrl_reg); } else { BUG(); @@ -460,12 +465,13 @@ int omap2_clkdm_wakeup(struct clockdom