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* vmscan: count the number of times zone_reclaim() scans and failsMel Gorman2009-06-16
* mm: remove CONFIG_UNEVICTABLE_LRU config optionKOSAKI Motohiro2009-06-16
* vmscan: don't export nr_saved_scan in /proc/zoneinfoWu Fengguang2009-06-16
* vmscan: cleanup the scan batching codeWu Fengguang2009-06-16
* page allocator: use allocation flags as an index to the zone watermarkMel Gorman2009-06-16
* [ARM] Double check memmap is actually valid with a memmap has unexpected hole...Mel Gorman2009-05-18
* mm: align vmstat_work's timerAnton Blanchard2009-04-02
* mm: introduce for_each_populated_zone() macroKOSAKI Motohiro2009-04-01
* cpumask: use new cpumask_ functions in core code.Rusty Russell2009-03-30
* cpumask: convert mm/Rusty Russell2008-12-31
* proc: move /proc/zoneinfo boilerplate to mm/vmstat.cAlexey Dobriyan2008-10-23
* proc: move /proc/vmstat boilerplate to mm/vmstat.cAlexey Dobriyan2008-10-23
* proc: move /proc/pagetypeinfo boilerplate to mm/vmstat.cAlexey Dobriyan2008-10-23
* proc: move /proc/buddyinfo boilerplate to mm/vmstat.cAlexey Dobriyan2008-10-23
* mlock: count attempts to free mlocked pageLee Schermerhorn2008-10-20
* vmstat: mlocked pages statisticsNick Piggin2008-10-20
* Unevictable LRU Page StatisticsLee Schermerhorn2008-10-20
* unevictable lru: add event counting with statisticsLee Schermerhorn2008-10-20
* vmscan: second chance replacement for anonymous pagesRik van Riel2008-10-20
* vmscan: split LRU lists into anon & file setsRik van Riel2008-10-20
* vmscan: Use an indexed array for LRU variablesChristoph Lameter2008-10-20
* [ARM] Skip memory holes in FLATMEM when reading /proc/pagetypeinfoMel Gorman2008-08-27
* mm/vmstat.c: proper externsAdrian Bunk2008-07-24
* mm: use performance variant for_each_cpu_mask_nrMike Travis2008-05-23
* make vmstat cpu-unplug safeKOSAKI Motohiro2008-05-13
* mm: Add NR_WRITEBACK_TEMP counterMiklos Szeredi2008-04-30
* /proc/pagetypeinfo: fix output for memoryless nodesKOSAKI Motohiro2008-04-30
* vmstats: add cond_resched() to refresh_cpu_vm_stats()Dimitri Sivanich2008-04-28
* Subject: [PATCH] hugetlb: vmstat events for huge page allocationsAdam Litke2008-04-28
* mm: remember what the preferred zone is for zone_statisticsMel Gorman2008-04-28
* add "Isolate" migratetype name to /proc/pagetypeinfoKOSAKI Motohiro2008-04-15
* vmstat: remove prefetchChristoph Lameter2008-02-05
* Page allocator: get rid of the list of cold pagesChristoph Lameter2008-02-05
* vmstat: small revisions to refresh_cpu_vm_stats()Christoph Lameter2008-02-05
* vmstat: fix section mismatch warningRandy Dunlap2007-11-14
* oom: change all_unreclaimable zone member to flagsDavid Rientjes2007-10-17
* mm/vmstat.c: cleanupsAdrian Bunk2007-10-16
* Print out statistics in relation to fragmentation avoidance to /proc/pagetype...Mel Gorman2007-10-16
* Remove fs.h from mm.hAlexey Dobriyan2007-07-29
* Create the ZONE_MOVABLE zoneMel Gorman2007-07-17
* mm: fixup /proc/vmstat outputPeter Zijlstra2007-07-06
* Detach sched.h from mm.hAlexey Dobriyan2007-05-21
* VM statistics: Make timer deferrableChristoph Lameter2007-05-11
* Move remote node draining out of slab allocatorsChristoph Lameter2007-05-09
* Make vm statistics update interval configurableChristoph Lameter2007-05-09
* vmstat: use our own timer eventsChristoph Lameter2007-05-09
* Add suspend-related notifications for CPU hotplugRafael J. Wysocki2007-05-09
* [PATCH] optional ZONE_DMA: optional ZONE_DMA in the VMChristoph Lameter2007-02-11
* [PATCH] Drop get_zone_counts()Christoph Lameter2007-02-11
* [PATCH] Drop __get_zone_counts()Christoph Lameter2007-02-11
n class="hl ppc">#define GT96100_ETH0_BASE (MIPS_GT96100_BASE + GT96100_ETH_PORT_CONFIG) #define GT96100_ETH1_BASE (GT96100_ETH0_BASE + GT96100_ETH_IO_SIZE) #ifdef CONFIG_MIPS_EV96100 #define GT96100_ETHER0_IRQ 3 #define GT96100_ETHER1_IRQ 4 #else #define GT96100_ETHER0_IRQ -1 #define GT96100_ETHER1_IRQ -1 #endif #define REV_GT96100 1 #define REV_GT96100A_1 2 #define REV_GT96100A 3 #define GT96100ETH_READ(gp, offset) \ GT96100_READ((gp->port_offset + offset)) #define GT96100ETH_WRITE(gp, offset, data) \ GT96100_WRITE((gp->port_offset + offset), data) #define GT96100ETH_SETBIT(gp, offset, bits) {\ u32 val = GT96100ETH_READ(gp, offset); val |= (u32)(bits); \ GT96100ETH_WRITE(gp, offset, val); } #define GT96100ETH_CLRBIT(gp, offset, bits) {\ u32 val = GT96100ETH_READ(gp, offset); val &= (u32)(~(bits)); \ GT96100ETH_WRITE(gp, offset, val); } /* Bit definitions of the SMI Reg */ enum { smirDataMask = 0xffff, smirPhyAdMask = 0x1f<<16, smirPhyAdBit = 16, smirRegAdMask = 0x1f<<21, smirRegAdBit = 21, smirOpCode = 1<<26, smirReadValid = 1<<27, smirBusy = 1<<28 }; /* Bit definitions of the Port Config Reg */ enum pcr_bits { pcrPM = 1, pcrRBM = 2, pcrPBF = 4, pcrEN = 1<<7, pcrLPBKMask = 0x3<<8, pcrLPBKBit = 8, pcrFC = 1<<10, pcrHS = 1<<12, pcrHM = 1<<13, pcrHDM = 1<<14, pcrHD = 1<<15, pcrISLMask = 0x7<<28, pcrISLBit = 28, pcrACCS = 1<<31 }; /* Bit definitions of the Port Config Extend Reg */ enum pcxr_bits { pcxrIGMP = 1, pcxrSPAN = 2, pcxrPAR = 4, pcxrPRIOtxMask = 0x7<<3, pcxrPRIOtxBit = 3, pcxrPRIOrxMask = 0x3<<6, pcxrPRIOrxBit = 6, pcxrPRIOrxOverride = 1<<8, pcxrDPLXen = 1<<9, pcxrFCTLen = 1<<10, pcxrFLP = 1<<11, pcxrFCTL = 1<<12, pcxrMFLMask = 0x3<<14, pcxrMFLBit = 14, pcxrMIBclrMode = 1<<16, pcxrSpeed = 1<<18, pcxrSpeeden = 1<<19, pcxrRMIIen = 1<<20, pcxrDSCPen = 1<<21 }; /* Bit definitions of the Port Command Reg */ enum pcmr_bits { pcmrFJ = 1<<15 }; /* Bit definitions of the Port Status Reg */ enum psr_bits { psrSpeed = 1, psrDuplex = 2, psrFctl = 4, psrLink = 8, psrPause = 1<<4, psrTxLow = 1<<5, psrTxHigh = 1<<6, psrTxInProg = 1<<7 }; /* Bit definitions of the SDMA Config Reg */ enum sdcr_bits { sdcrRCMask = 0xf<<2, sdcrRCBit = 2, sdcrBLMR = 1<<6, sdcrBLMT = 1<<7, sdcrPOVR = 1<<8, sdcrRIFB = 1<<9, sdcrBSZMask = 0x3<<12, sdcrBSZBit = 12 }; /* Bit definitions of the SDMA Command Reg */ enum sdcmr_bits { sdcmrERD = 1<<7, sdcmrAR = 1<<15, sdcmrSTDH = 1<<16, sdcmrSTDL = 1<<17, sdcmrTXDH = 1<<23, sdcmrTXDL = 1<<24, sdcmrAT = 1<<31 }; /* Bit definitions of the Interrupt Cause Reg */ enum icr_bits { icrRxBuffer = 1, icrTxBufferHigh = 1<<2, icrTxBufferLow = 1<<3, icrTxEndHigh = 1<<6, icrTxEndLow = 1<<7, icrRxError = 1<<8, icrTxErrorHigh = 1<<10, icrTxErrorLow = 1<<11, icrRxOVR = 1<<12, icrTxUdr = 1<<13, icrRxBufferQ0 = 1<<16, icrRxBufferQ1 = 1<<17, icrRxBufferQ2 = 1<<18, icrRxBufferQ3 = 1<<19, icrRxErrorQ0 = 1<<20, icrRxErrorQ1 = 1<<21, icrRxErrorQ2 = 1<<22, icrRxErrorQ3 = 1<<23, icrMIIPhySTC = 1<<28, icrSMIdone = 1<<29, icrEtherIntSum = 1<<31 }; /* The Rx and Tx descriptor lists. */ typedef struct { #ifdef DESC_BE u16 byte_cnt; u16 reserved; #else u16 reserved; u16 byte_cnt; #endif u32 cmdstat; u32 next; u32 buff_ptr; } __attribute__ ((packed)) gt96100_td_t; typedef struct { #ifdef DESC_BE u16 buff_sz; u16 byte_cnt; #else u16 byte_cnt; u16 buff_sz; #endif u32 cmdstat; u32 next; u32 buff_ptr; } __attribute__ ((packed)) gt96100_rd_t; /* Values for the Tx command-status descriptor entry. */ enum td_cmdstat { txOwn = 1<<31, txAutoMode = 1<<30, txEI = 1<<23, txGenCRC = 1<<22, txPad = 1<<18, txFirst = 1<<17, txLast = 1<<16, txErrorSummary = 1<<15, txReTxCntMask = 0x0f<<10, txReTxCntBit = 10, txCollision = 1<<9, txReTxLimit = 1<<8, txUnderrun = 1<<6, txLateCollision = 1<<5 }; /* Values for the Rx command-status descriptor entry. */ enum rd_cmdstat { rxOwn = 1<<31, rxAutoMode = 1<<30, rxEI = 1<<23, rxFirst = 1<<17, rxLast = 1<<16, rxErrorSummary = 1<<15, rxIGMP = 1<<14, rxHashExpired = 1<<13, rxMissedFrame = 1<<12, rxFrameType = 1<<11, rxShortFrame = 1<<8, rxMaxFrameLen = 1<<7, rxOverrun = 1<<6, rxCollision = 1<<4, rxCRCError = 1 }; /* Bit fields of a Hash Table Entry */ enum hash_table_entry { hteValid = 1, hteSkip = 2, hteRD = 4 }; // The MIB counters typedef struct { u32 byteReceived; u32 byteSent; u32 framesReceived; u32 framesSent; u32 totalByteReceived; u32 totalFramesReceived; u32 broadcastFramesReceived; u32 multicastFramesReceived; u32 cRCError; u32 oversizeFrames; u32 fragments; u32 jabber; u32 collision; u32 lateCollision; u32 frames64; u32 frames65_127; u32 frames128_255; u32 frames256_511; u32 frames512_1023; u32 frames1024_MaxSize; u32 macRxError; u32 droppedFrames; u32 outMulticastFrames; u32 outBroadcastFrames; u32 undersizeFrames; } mib_counters_t; struct gt96100_private { gt96100_rd_t* rx_ring; gt96100_td_t* tx_ring; // The Rx and Tx rings must be 16-byte aligned dma_addr_t rx_ring_dma; dma_addr_t tx_ring_dma; char* hash_table; // The Hash Table must be 8-byte aligned dma_addr_t hash_table_dma; int hash_mode; // The Rx buffers must be 8-byte aligned char* rx_buff; dma_addr_t rx_buff_dma; // Tx buffers (tx_skbuff[i]->data) with less than 8 bytes // of payload must be 8-byte aligned struct sk_buff* tx_skbuff[TX_RING_SIZE]; int rx_next_out; /* The next free ring entry to receive */ int tx_next_in; /* The next free ring entry to send */ int tx_next_out; /* The last ring entry the ISR processed */ int tx_count; /* current # of pkts waiting to be sent in Tx ring */ int intr_work_done; /* number of Rx and Tx pkts processed in the isr */ int tx_full; /* Tx ring is full */ mib_counters_t mib; struct net_device_stats stats; int io_size; int port_num; // 0 or 1 int chip_rev; u32 port_offset; int phy_addr; // PHY address u32 last_psr; // last value of the port status register int options; /* User-settable misc. driver options. */ int drv_flags; struct timer_list timer; spinlock_t lock; /* Serialise access to device */ }; #endif