aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-sparc64
Commit message (Collapse)AuthorAge
...
* [SPARC64]: Add GET_GL_GLOBAL() macro for SUN4V.David S. Miller2006-03-20
| | | | | | So we can read the %gl register for debugging. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add sun4v_cpu_qconf() hypervisor call.David S. Miller2006-03-20
| | | | | | Call it from register_one_mondo(). Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC]: Kill off these __put_user_ret things.David S. Miller2006-03-20
| | | | | | They are bogus and haven't been referenced in years. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Decode virtual-devices interrupts correctly.David S. Miller2006-03-20
| | | | | | Need to translate through the interrupt-map{,-mask] properties. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add prom_{start,stop}cpu_cpuid().David S. Miller2006-03-20
| | | | | | | | | Use prom_startcpu_cpuid() on SUN4V instead of prom_startcpu(). We should really test for "SUNW,start-cpu-by-cpuid" presence and use it if present even on SUN4U. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fixup TSTATE layout diagram in asm/pstate.hDavid S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix gcc-3.3.x warnings.David S. Miller2006-03-20
| | | | | | | | | | | It doesn't like const variables being passed into "i" constraing asm operations. It's a bug, but there is nothing we can really do but work around it. Based upon a report from Andrew Morton. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Make error codes available from sun4v_intr_get*().David S. Miller2006-03-20
| | | | | | And check for errors at call sites. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix comment typo in asm/hypervisor.hDavid S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Probe virtual-devices root node on sun4v.David S. Miller2006-03-20
| | | | | | | This is where we learn how to get the interrupts for things like the hypervisor console device. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Generic sun4v_build_irq().David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Implement rest of generic interrupt hypervisor calls.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move devino_to_sysino out of pci_sun4v_asm.SDavid S. Miller2006-03-20
| | | | | | It is not PCI specific, it is for all system interrupts. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use inline patching for critical PTE operations.David S. Miller2006-03-20
| | | | | | | This handles the SUN4U vs SUN4V PTE layout differences with near zero performance cost. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move PTE field definitions back into asm/pgtable.hDavid S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Recognize "virtual-console" as input and output console device.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Deal with PTE layout differences in SUN4V.David S. Miller2006-03-20
| | | | | | | | | | Yes, you heard it right, they changed the PTE layout for SUN4V. Ho hum... This is the simple and inefficient way to support this. It'll get optimized, don't worry. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Register kernel TSB with hypervisor.David S. Miller2006-03-20
| | | | | | We do this right after we take over the trap table from OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix some SUN4V TLB miss bugs.David S. Miller2006-03-20
| | | | | | | | | | Code patching did not sign extend negative branch offsets correctly. Kernel TLB miss path needs patching and %g4 register preservation in order to handle SUN4V correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.David S. Miller2006-03-20
| | | | | | | | | | | | | This is where the virtual address of the fault status area belongs. To set it up we don't make a hypervisor call, instead we call OBP's SUNW,set-trap-table with the real address of the fault status area as the second argument. And right before that call we write the virtual address into ASI_SCRATCHPAD vaddr 0x0. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add HV_PCI_TSBID() macro.David S. Miller2006-03-20
| | | | | | For constructing hypervisor PCI TSB IDs. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: More SUN4V PCI controller work.David S. Miller2006-03-20
| | | | | | | | | | Add assembler file for PCI hypervisor calls. Setup basic skeleton of SUN4V PCI controller driver. Add 32-bit devhandle to PBM struct, as this is needed for hypervisor calls. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Beginnings of SUN4V PCI controller support.David S. Miller2006-03-20
| | | | | | | | Abstract out IOMMU operations so that we can have a different set of calls on sun4v, which needs to do things through hypervisor calls. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC]: Clean up idprom header files.David S. Miller2006-03-20
| | | | | | | Delete unused macros, and use fixed sized types in sparc32 header. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Hypervisor TSB context switching.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Implement sun4v TSB miss handlers.David S. Miller2006-03-20
| | | | | | | | | | | When we register a TSB with the hypervisor, so that it or hardware can handle TLB misses and do the TSB walk for us, the hypervisor traps down to these trap when it incurs a TSB miss. Processing is simple, we load the missing virtual address and context, and do a full page table walk. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Detect sun4v early in boot process.David S. Miller2006-03-20
| | | | | | | | | | | | | We look for "SUNW,sun4v" in the 'compatible' property of the root OBP device tree node. Protect every %ver register access, to make sure it is not touched on sun4v, as %ver is hyperprivileged there. Lock kernel TLB entries using hypervisor calls instead of calls into OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v cross-call sending support.David S. Miller2006-03-20
| | | | | | | | | | | Technically the hypervisor call supports sending in a list of all cpus to get the cross-call, but I only pass in one cpu at a time for now. The multi-cpu support is there, just ifdef'd out so it's easy to enable or delete it later. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v interrupt handling.David S. Miller2006-03-20
| | | | | | | | | | | | | | | | | Sun4v has 4 interrupt queues: cpu, device, resumable errors, and non-resumable errors. A set of head/tail offset pointers help maintain a work queue in physical memory. The entries are 64-bytes in size. Each queue is allocated then registered with the hypervisor as we bring cpus up. The two error queues each get a kernel side buffer that we use to quickly empty the main interrupt queue before we call up to C code to log the event and possibly take evasive action. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add sun4v mondo queue bases to struct trap_per_cpu.David S. Miller2006-03-20
| | | | | | | Also, correct TRAP_PER_CPU_FAULT_INFO define, it should be 0x40 not 0x20. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix some comment typos in asm/hypervisor.hDavid S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Patch up mmu context register writes for sun4v.David S. Miller2006-03-20
| | | | | | sun4v uses ASI_MMU instead of ASI_DMMU Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Register per-cpu fault status area with sun4v hypervisor.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: asm/cpudata.h needs asm/asi.hDavid S. Miller2006-03-20
| | | | | | For the expansion of __GET_CPUID() on SMP. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patchDavid S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Initial sun4v TLB miss handling infrastructure.David S. Miller2006-03-20
| | | | | | | | | | Things are a little tricky because, unlike sun4u, we have to: 1) do a hypervisor trap to do the TLB load. 2) do the TSB lookup calculations by hand Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sanitize %pstate writes for sun4v.David S. Miller2006-03-20
| | | | | | | | If we're just switching between different alternate global sets, nop it out on sun4v. Also, get rid of all of the alternate global save/restore in the OBP CIF trampoline code. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill all %pstate changes in context switch code.David S. Miller2006-03-20
| | | | | | | | | | | | | | | They are totally unnecessary because: 1) Interrupts are already disabled when switch_to() runs. 2) We don't use hard-coded alternate globals any longer. This found a case in rtrap, which still assumed alternate global %g6 was current_thread_info(), and that is fixed by this changeset as well. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add initial code to twiddle %gl on trap entry/exit.David S. Miller2006-03-20
| | | | | | | Instead of setting/clearing PSTATE_AG we have to change the %gl register value on sun4v. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add define for "GL" field of sun4v %tstate register.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add sun4v case to __GET_CPUID() patch tables.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v interrupt queue register definitions.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v scratchpad register layout.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v specific ASI defines.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add Niagara init-store twin-load ASI defines.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add 'hypervisor' to ultra_tlb_type enumeration.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: SUN4V hypervisor interface defines.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Refine register window trap handling.David S. Miller2006-03-20
| | | | | | | | | | | When saving and restoing trap state, do the window spill/fill handling inline so that we never trap deeper than 2 trap levels. This is important for chips like Niagara. The window fixup code is massively simplified, and many more improvements are now possible. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add explicit register args to trap state loading macros.David S. Miller2006-03-20
| | | | | | | This, as well as making the code cleaner, allows a simplification in the TSB miss handling path. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Refine code sequences to get the cpu id.David S. Miller2006-03-20
| | | | | | | | | | | | | | | | | | On uniprocessor, it's always zero for optimize that. On SMP, the jmpl to the stub kills the return address stack in the cpu branch prediction logic, so expand the code sequence inline and use a code patching section to fix things up. This also always better and explicit register selection, which will be taken advantage of in a future changeset. The hard_smp_processor_id() function is big, so do not inline it. Fix up tests for Jalapeno to also test for Serrano chips too. These tests want "jbus Ultra-IIIi" cases to match, so that is what we should test for. Signed-off-by: David S. Miller <davem@davemloft.net>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 02:38:29 -0500