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* sh: Revert TLB miss fast-path changes that broke PTEA parts.Paul Mundt2007-02-14
| | | | | | | | This ended up causing problems for older parts (particularly ones using PTEA). Revert this for now, it can be added back in once it's had some more testing. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: define dma noncoherent API functions.Paul Mundt2007-02-12
| | | | | | sh was missing these, too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Missing flush_dcache_all() proto in cacheflush.h.Paul Mundt2007-02-12
| | | | | | Some boards need this, so provide a definition. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add cpu-features header to asm/Kbuild.Paul Mundt2007-02-12
| | | | | | | | This is used by the libc for parsing CPU capability flags passed via the ELF auxvt, needed for run-time selection of atomic opcodes amongst other things. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Move __KERNEL__ up in asm/page.h.Paul Mundt2007-02-12
| | | | | | | This was breaking the uClibc build, which triggered the bogus page size error. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix syscall numbering breakage.Paul Mundt2007-02-12
| | | | | | We accidentally broke the inotify syscalls, fix those up again. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Local TLB flushing variants for SMP prep.Paul Mundt2007-02-12
| | | | | | | Rename the existing flush routines to local_ variants for use by the IPI-backed global flush routines on SMP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fixup cpu_data references for the non-boot CPUs.Paul Mundt2007-02-12
| | | | | | | There are a lot of bogus cpu_data-> references that only end up working for the boot CPU, convert these to current_cpu_data to fixup SMP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Use a per-cpu ASID cache.Paul Mundt2007-02-12
| | | | | | | | Previously this was implemented using a global cache, cache this per-CPU instead and bump up the number of context IDs to match NR_CPUS. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: SH-DMAC compile fixesManuel Lauss2007-02-12
| | | | | | | | | | | | | | | | | This patch does the following: - remove the make_ipr_irq stuff from dma-sh.c and replace it with a simple channel<->irq mapping table. - add DMTEx_IRQ constants for sh4 cpus - fix sh7751 DMAE irq number The SH7780 uses the same IRQs for DMA as other SH4 types, so I put the constants on top of the dma.h file. Other CPU types need to #define their own DMTEx_IRQ contants in their appropriate header. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Lazy dcache writeback optimizations.Paul Mundt2007-02-12
| | | | | | | | | | | | | | | This converts the lazy dcache handling to the model described in Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a bonus, this slightly cuts down on the cache flushing frequency. With that and the PTEA handling out of the way, the update_mmu_cache() implementations can be consolidated, and we no longer have to worry about which configuration the cache is in for the SH7705 case. And finally, explicitly disable the lazy writeback on SMP (SH-4A). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: More tidying for large base pages.Paul Mundt2007-02-12
| | | | | | | | There were a few more things that needed fixing up, namely THREAD_SIZE and the TLB miss handler where certain PTRS_PER_PGD == PTRS_PER_PTE assumptions were being made. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: syscall 300 should be __NR_fstatat64.SUGIOKA Toshinobu2007-02-12
| | | | | | | | | | | | syscall number 300 fails while testing with latest LTP (ltp-full-20061121.tgz) on sh. sys_fstatat64 is called on syscall 300 (see arch/sh/kernel/syscalls.S), and __ARCH_WANT_STAT64 is defined in include/asm-sh/unistd.h, so following patch seems correct. Signed-off-by: SUGIOKA Toshinobu <sugioka@itonet.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Use a jump call table for debug trap handlers.Paul Mundt2007-02-12
| | | | | | | | | | | | | | | | | This rips out most of the needlessly complicated sh_bios and kgdb trap handling, and forces it all through a common fast dispatch path. As more debug traps are inserted, it's important to keep them in sync for all of the parts, not just SH-3/4. As the SH-2 parts are unable to do traps in the >= 0x40 range, we restrict the debug traps to the 0x30-0x3f range on all parts, and also bump the kgdb breakpoint trap down in to this range (from 0xff to 0x3c) so it's possible to use for nommu. Optionally, this table can be padded out to catch spurious traps for SH-3/4, but we don't do that yet.. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* [PATCH] consolidate line discipline number definitionsTilman Schmidt2007-02-11
| | | | | | | | | | | | | | | | | | | The line discipline numbers N_* are currently defined for each architecture individually, but (except for a seeming mistake) identically, in asm/termios.h. There is no obvious reason why these numbers should be architecture specific, nor any apparent relationship with the termios structure. The total number of these, NR_LDISCS, is defined in linux/tty.h anyway. So I propose the following patch which moves the definitions of the individual line disciplines to linux/tty.h too. Three of these numbers (N_MASC, N_PROFIBUS_FDL, and N_SMSBLOCK) are unused in the current kernel, but the patch still keeps the complete set in case there are plans to use them yet. Signed-off-by: Tilman Schmidt <tilman@imap.cc> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [APM] SH: Convert to use shared APM emulation.Paul Mundt2007-02-09
| | | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [PATCH] Optimize D-cache alias handling on forkRalf Baechle2006-12-13
| | | | | | | | | | | Virtually index, physically tagged cache architectures can get away without cache flushing when forking. This patch adds a new cache flushing function flush_cache_dup_mm(struct mm_struct *) which for the moment I've implemented to do the same thing on all architectures except on MIPS where it's a no-op. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] PM: Fix SMP races in the freezerRafael J. Wysocki2006-12-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, to tell a task that it should go to the refrigerator, we set the PF_FREEZE flag for it and send a fake signal to it. Unfortunately there are two SMP-related problems with this approach. First, a task running on another CPU may be updating its flags while the freezer attempts to set PF_FREEZE for it and this may leave the task's flags in an inconsistent state. Second, there is a potential race between freeze_process() and refrigerator() in which freeze_process() running on one CPU is reading a task's PF_FREEZE flag while refrigerator() running on another CPU has just set PF_FROZEN for the same task and attempts to reset PF_FREEZE for it. If the refrigerator wins the race, freeze_process() will state that PF_FREEZE hasn't been set for the task and will set it unnecessarily, so the task will go to the refrigerator once again after it's been thawed. To solve first of these problems we need to stop using PF_FREEZE to tell tasks that they should go to the refrigerator. Instead, we can introduce a special TIF_*** flag and use it for this purpose, since it is allowed to change the other tasks' TIF_*** flags and there are special calls for it. To avoid the freeze_process()-refrigerator() race we can make freeze_process() to always check the task's PF_FROZEN flag after it's read its "freeze" flag. We should also make sure that refrigerator() will always reset the task's "freeze" flag after it's set PF_FROZEN for it. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Acked-by: Pavel Machek <pavel@ucw.cz> Cc: Russell King <rmk@arm.linux.org.uk> Cc: David Howells <dhowells@redhat.com> Cc: Andi Kleen <ak@muc.de> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* sh: SH-MobileR SH7722 CPU support.Paul Mundt2006-12-11
| | | | | | This adds CPU support for the SH7722. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fixup dma_cache_sync() callers.Paul Mundt2006-12-11
| | | | | | This now takes a struct device, update all of the callers. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: BUG() handling through trapa vector.Paul Mundt2006-12-11
| | | | | | | | | | | | | Previously we haven't been doing anything with verbose BUG() reporting, and we've been relying on the oops path for handling BUG()'s, which is rather sub-optimal. This switches BUG handling to use a fixed trapa vector (#0x3e) where we construct a small bug frame post trapa instruction to get the context right. This also makes it trivial to wire up a DIE_BUG for the atomic die chain, which we couldn't really do before. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Split out atomic ops logically.Paul Mundt2006-12-11
| | | | | | | | We have a few different ways to do the atomic operations, so split them out in to different headers rather than bloating atomic.h. Kernelspace gUSA will take this up to a third implementation. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: landisk board build fixes.Paul Mundt2006-12-11
| | | | | | Get the landisk board building again.. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: push-switch fixups for work_struct API damage.Paul Mundt2006-12-11
| | | | | | | INIT_WORK() dropped the data arg, so now we have to stash an extra pointer and backpedal instead. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Shut up csum_ipv6_magic() warnings.Paul Mundt2006-12-11
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Reworked swap cache entry encoding for SH-X2 MMU.Paul Mundt2006-12-11
| | | | | | | | | | | | | In the 64-bit PTE case there's no point in restricting the encoding to the low bits of the PTE, we can instead bump all of this up to the high 32 bits and extend PTE_FILE_MAX_BITS to 32, adopting the same convention used by x86 PAE. There's a minor discrepency between the number of bits used for the swap type encoding between 32 and 64-bit PTEs, but this is unlikely to cause any problem given the extended offset. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* [PATCH] tty: preparatory structures for termios revampAlan Cox2006-12-08
| | | | | | | | | | | | | | | | | | | | In order to sort out our struct termios and add proper speed control we need to separate the kernel and user termios structures. Glibc is fine but the other libraries rely on the kernel exported struct termios and we need to extend this without breaking the ABI/API To do so we add a struct ktermios which is the kernel view of a termios structure and overlaps the struct termios with extra fields on the end for now. (That limitation will go away in later patches). Some platforms (eg alpha) planned ahead and thus use the same struct for both, others did not. This just adds the structures but does not use them, it seems a sensible splitting point for bisect if there are compile failures (not that I expect them) Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] cleanup asm/setup.h userspace visibilityAdrian Bunk2006-12-07
| | | | | | | | | | | | | | | | | | Make the contents of the userspace asm/setup.h header consistent on all architectures: - export setup.h to userspace on all architectures - export only COMMAND_LINE_SIZE to userspace - frv: move COMMAND_LINE_SIZE from param.h - i386: remove duplicate COMMAND_LINE_SIZE from param.h - arm: - export ATAGs to userspace - change u8/u16/u32 to __u8/__u16/__u32 Signed-off-by: Adrian Bunk <bunk@stusta.de> Acked-by: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] Pass struct dev pointer to dma_cache_sync()Ralf Baechle2006-12-07
| | | | | | | | | | | | | | | | | Pass struct dev pointer to dma_cache_sync() dma_cache_sync() is ill-designed in that it does not have a struct device pointer argument which makes proper support for systems that consist of a mix of coherent and non-coherent DMA devices hard. Change dma_cache_sync to take a struct device pointer as first argument and fix all its callers to pass it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: James Bottomley <James.Bottomley@steeleye.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] remove kernel syscallsArnd Bergmann2006-12-07
| | | | | | | | | | | | The last thing we agreed on was to remove the macros entirely for 2.6.19, on all architectures. Unfortunately, I think nobody actually _did_ that, so they are still there. [akpm@osdl.org: x86_64 fix] Cc: David Woodhouse <dwmw2@infradead.org> Cc: Greg Schafer <gschafer@zip.com.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* sh: sh775x/titan fixes for irq header changes.Jamie Lenehan2006-12-05
| | | | | | | | | | | | | | | | | | | | | The following moves the creation of IPR interupts into setup-7750.c and updates a few other things to make it all work after the "Drop CPU subtype IRQ headers" commit. It boots and runs fine on my titan board. - adds an ipr_idx to the ipr_data and uses a function in the subtype code to calculate the address of the IPR registers - adds a function to enable individual interrupt mode for externals in the subtype code and calls that from the titan board code instead of doing it directly. - I changed the shift in the ipr_data to be the actual # of bits to shift, instead of the numnber / 4 - made it easier to match with the manual. Signed-off-by: Jamie Lenehan <lenehan@twibble.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fixup pte_mkhuge() build failure.Paul Mundt2006-12-05
| | | | | | | | When hugetlbpage support isn't enabled, this can be bogus. Wrap it back in _PAGE_FLAGS_HARD to avoid changes to the base PTE when not aiming for larger sizes. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: stacktrace/lockdep/irqflags tracing support.Paul Mundt2006-12-05
| | | | | | Wire up all of the essentials for lockdep.. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fixup movli.l/movco.l atomic ops for gcc4.Paul Mundt2006-12-05
| | | | | | | | | | | | | | | gcc4 gets a bit pissy about the outputs: include/asm/atomic.h: In function 'atomic_add': include/asm/atomic.h:37: error: invalid lvalue in asm statement include/asm/atomic.h:30: error: invalid lvalue in asm output 1 ... this ended up being a thinko anyways, so just fix it up. Verified for proper behaviour with the older toolchains, too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: dyntick infrastructure.Paul Mundt2006-12-05
| | | | | | | | This adds basic NO_IDLE_HZ support to the SH timer API so timers are able to wire it up. Taken from the ARM version, as it fit in to our API with very few changes needed. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Clock framework tidying.Paul Mundt2006-12-05
| | | | | | | | This syncs up the SH clock framework with the linux/clk.h API, for which there were only some minor changes required, namely the clk_get() dev_id and subsequent callsites. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fixup various PAGE_SIZE == 4096 assumptions.Paul Mundt2006-12-05
| | | | | | | | | | | | | | | | | | | | | | There were a number of places that made evil PAGE_SIZE == 4k assumptions that ended up breaking when trying to play with 8k and 64k page sizes, this fixes those up. The most significant change is the way we load THREAD_SIZE, previously this was done via: mov #(THREAD_SIZE >> 8), reg shll8 reg to avoid a memory access and allow the immediate load. With a 64k PAGE_SIZE, we're out of range for the immediate load size without resorting to special instructions available in later ISAs (movi20s and so on). The "workaround" for this is to bump up the shift to 10 and insert a shll2, which gives a bit more flexibility while still being much cheaper than a memory access. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: dma-api channel capability extensions.Mark Glaisher2006-12-05
| | | | | | | | | | | | | This extends the SH DMA API for allowing handling of DMA channels based off of their respective capabilities. A couple of functions are added to the existing API, the core bits are register_chan_caps() for registering channel capabilities, and request_dma_bycap() for fetching a channel dynamically based off of a capability set. Signed-off-by: Mark Glaisher <mark.glaisher@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: KSTK_EIP/KSTK_ESP consistency.Stuart Menefy2006-12-05
| | | | | | | | | | | | | | | | | | | | | Two of the fields in /proc/[number]/stat are documented in proc(5) as: kstkesp %lu The current value of esp (stack pointer), as found in the kernel stack page for the process. kstkeip %lu The current EIP (instruction pointer). The SH currently prints the the last SP and PC of the process inside the kernel, while most other archs use the last user space values. This patch modifes the SH to display the user space values. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: TLB miss fast-path optimizations.Stuart Menefy2006-12-05
| | | | | | | | Handle simple TLB miss faults which can be resolved completely from the page table in assembler. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: generic push-switch framework.Paul Mundt2006-12-05
| | | | | | | | | | This adds support for a generic push switch framework. Adaptable for various switches, including GPIO switches and the push switches commonly found on Renesas debug boards. This allows switch states to be trivially reported through sysfs. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pmd rework.Stuart Menefy2006-12-05
| | | | | | | | | Remove extra bits from the pmd structure and store a kernel logical address rather than a physical address. This allows it to be directly dereferenced. Another piece of wierdness inherited from x86. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Use MMU.TTB register as pointer to current pgd.Stuart Menefy2006-12-05
| | | | | | | | | Add TTB accessor functions and give it a sensible default value. We will use this later for optimizing the fault path. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Set up correct siginfo structures for page faults.Stuart Menefy2006-12-05
| | | | | | | | Remove the previous saving of fault codes into the thread_struct as they are never used, and appeared to be inherited from x86. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Preliminary support for SH-X2 MMU.Paul Mundt2006-12-05
| | | | | | | | | | | | | | | | | | | This adds some preliminary support for the SH-X2 MMU, used by newer SH-4A parts (particularly SH7785). This MMU implements a 'compat' mode with SH-X MMUs and an 'extended' mode for SH-X2 extended features. Extended features include additional page sizes (8kB, 4MB, 64MB), as well as the addition of page execute permissions. The extended mode attributes are placed in a second data array, which requires us to switch to 64-bit PTEs when in X2 mode. With the addition of the exec perms, we also overhaul the mmap prots somewhat, now that it's possible to handle them more intelligently. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Hook SH7785 in to the build system.Paul Mundt2006-12-05
| | | | | | Simple 7785 placeholders to start hooking up other bits of code. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Drop CPU subtype IRQ headers.Paul Mundt2006-12-05
| | | | | | | | | | | | | This drops the various IRQ headers that were floating around and primarily providing hardcoded IRQ definitions for the various CPU subtypes. This quickly got to be an unmaintainable mess, made even more evident by the subtle breakage introduced by the SH-2 and SH-2A changes. Now that subtypes are able to register IRQ maps directly, just rip all of the headers out. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: SE7206 build fixes.Paul Mundt2006-12-05
| | | | | | | A number of API changes happened underneath the 7206 patches, update for everything that broke. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add SH-2A platform headers.Yoshinori Sato2006-12-05
| | | | | | | Mostly SH-2 wrappers.. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* [PATCH] Centralise definitions of sector_t and blkcnt_tMatthew Wilcox2006-12-04
| | | | | | | | | | | | | | | | CONFIG_LBD and CONFIG_LSF are spread into asm/types.h for no particularly good reason. Centralising the definition in linux/types.h means that arch maintainers don't need to bother adding it, as well as fixing the problem with x86-64 users being asked to make a decision that has absolutely no effect. The H8/300 porters seem particularly confused since I'm not aware of any microcontrollers that need to support 2TB filesystems. Signed-off-by: Matthew Wilcox <matthew@wil.cx> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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