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* [MIPS] Sibyte: Fix race in sb1250_gettimeoffset().Ralf Baechle2006-03-18
| | | | | | | | | | | | | | | | | | | | | | | From Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>: sb1250_gettimeoffset() simply reads the current cpu 0 timer remaining value, however once this counter reaches 0 and the interrupt is raised, it immediately resets and begins to count down again. If sb1250_gettimeoffset() is called on cpu 1 via do_gettimeofday() after the timer has reset but prior to cpu 0 processing the interrupt and taking write_seqlock() in timer_interrupt() it will return a full value (or close to it) causing time to jump backwards 1ms. Once cpu 0 handles the interrupt and timer_interrupt() gets far enough along it will jump forward 1ms. Fix this problem by implementing mips_hpt_*() on sb1250 using a spare timer unrelated to the existing periodic interrupt timers. It runs at 1Mhz with a full 23bit counter. This eliminated the custom do_gettimeoffset() for sb1250 and allowed use of the generic fixed_rate_gettimeoffset() using mips_hpt_*() and timerhi/timerlo. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Fix M_SCD_TIMER_INIT and M_SCD_TIMER_CNT wrong field width.Ralf Baechle2006-03-18
| | | | | | | | From Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>: Field width should be 23 bits not 20 bits. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Work around bad code generation for <asm/io.h>.Ralf Baechle2006-03-18
| | | | | | | | | If a call to set_io_port_base() was being followed by usage of mips_io_port_base in the same function gcc was possibly using the old value due to some clever abuse of const. Adding a barrier will keep the optimization and result in correct code with latest gcc. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto2006-03-18
| | | | | | | | | | If dcache_size != icache_size or dcache_size != scache_size, or set-associative cache, icache/scache does not flushed properly. Make blast_?cache_page_indexed() masks its index value correctly. Also, use physical address for physically indexed pcache/scache. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SB1: Fix interrupt disable hazard.Ralf Baechle2006-03-18
| | | | | | | The SB1 core has a three cycle interrupt disable hazard but we were wrongly treating it as fully interlocked. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Undefine scr_writew and scr_readw in <asm/vga.h>.Ralf Baechle2006-03-09
| | | | | | | This is gluing the build of cirrusfb but really the mess that would need cleaning and fixing is <video/vga.h> and <linux/vt_buffer.h> ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix build error on processors that don's support copy-on-write.Ralf Baechle2006-02-28
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix atomic*_sub_if_positive return value.Ralf Baechle2006-02-27
| | | | | | | Reported and initial fix by Thomas Koeller <thomas.koeller@baslerweb.com>, rewritten by me. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMP: Fix initialization order bug.Ralf Baechle2006-02-27
| | | | | | | | | | | | | | A recent change requires cpu_possible_map to be initialized before smp_sched_init() but most MIPS platforms were initializing their processors in the prom_prepare_cpus callback of smp_prepare_cpus. The simple fix of calling prom_prepare_cpus from one of the earlier SMP initialization hooks doesn't work well either since IPIs may require init_IRQ() to have completed, so bit the bullet and split prom_prepare_cpus into two initialization functions, plat_smp_setup which is called early from setup_arch and plat_prepare_cpus called where prom_prepare_cpus used to be called. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Use "=R" constraint to avoid compiler errors in cmpxchg().Ralf Baechle2006-02-27
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Follow Uli's latest *at syscall changes.Ralf Baechle2006-02-21
| | | | | | | (This really is only the half of the patch which was forgotten in 326a625748535c4cdb1c632b1dcb07030989a393 ...) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fixes for uaccess.h with gcc >= 4.0.1Atsushi Nemoto2006-02-21
| | | | | | | | | | It seems current get_user() incorrectly sign-extend an unsigned int value on 64bit kernel. I think this is because '(__typeof__(val))' cast in final assignment. I suppose the cast should be '(__typeof__(*(addr))'. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [PATCH] add asm-generic/mman.hMichael S. Tsirkin2006-02-15
| | | | | | | | | | | | | | Make new MADV_REMOVE, MADV_DONTFORK, MADV_DOFORK consistent across all arches. The idea is to make it possible to use them portably even before distros include them in libc headers. Move common flags to asm-generic/mman.h Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il> Cc: Roland Dreier <rolandd@cisco.com> Cc: Badari Pulavarty <pbadari@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] madvise MADV_DONTFORK/MADV_DOFORKMichael S. Tsirkin2006-02-14
| | | | | | | | | | | | | | | | | | | | | | | | Currently, copy-on-write may change the physical address of a page even if the user requested that the page is pinned in memory (either by mlock or by get_user_pages). This happens if the process forks meanwhile, and the parent writes to that page. As a result, the page is orphaned: in case of get_user_pages, the application will never see any data hardware DMA's into this page after the COW. In case of mlock'd memory, the parent is not getting the realtime/security benefits of mlock. In particular, this affects the Infiniband modules which do DMA from and into user pages all the time. This patch adds madvise options to control whether memory range is inherited across fork. Useful e.g. for when hardware is doing DMA from/into these pages. Could also be useful to an application wanting to speed up its forks by cutting large areas out of consideration. Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il> Acked-by: Hugh Dickins <hugh@veritas.com> Cc: Michael Kerrisk <mtk-manpages@gmx.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [MIPS] Fix CPU type bitmasks for MIPS III, IV and V.Maciej W. Rozycki2006-02-14
| | | | | Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Get rid of kludgery needed to keep stdargs of old compilers working.Ralf Baechle2006-02-14
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] More uaccess.h fixes with gcc >= 4.0.1.Ralf Baechle2006-02-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Richard Sandiford <richard@codesourcery.com>: This patch caused a miscompilation of the restore_gp_regs() block in restore_sigcontext(). This was in a 32-bit kernel compiled with GCC CVS head. restore_gp_regs() copies 64-bit user fields into 32-bit variables, and in this combination, the new __get_user_asm_ll32() clobbers too many registers. It says: /* * Get a long long 64 using 32 bit registers. */ { \ __asm__ __volatile__( \ "1: lw %1, (%3) \n" \ "2: lw %D1, 4(%3) \n" \ " move %0, $0 \n" \ "3: .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " move %1, $0 \n" \ " move %D1, $0 \n" \ " j 3b \n" \ " .previous \n" \ " .section __ex_table,\"a\" \n" \ " " __UA_ADDR " 1b, 4b \n" \ " " __UA_ADDR " 2b, 4b \n" \ " .previous \n" \ : "=r" (__gu_err), "=&r" (val) \ : "0" (0), "r" (addr), "i" (-EFAULT)); \ } and this requires val (%1) to be a 64-bit value. In the case I saw, gcc was using $3 for the 32-bit val, and wasn't expecting $4 to be clobbered. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add protected_blast_icache_range, blast_icache_range, etc.Atsushi Nemoto2006-02-14
| | | | | | | | | | Add blast_xxx_range(), protected_blast_xxx_range() etc. for common use. They are built by __BUILD_BLAST_CACHE_RANGE(). Use protected_cache_op() macro for various protected_ routines. Output code should be logically same. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fold non-__mips64 case into CONFIG_32BIT case.Ralf Baechle2006-02-14
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] RM200: Give RM200 it's own timex.h.Ralf Baechle2006-02-14
| | | | | | | So we can get rid of config.h and the #ifdef crapola in the generic timex.h. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2006-02-08
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| * [MIPS] Add 'const' to readb and friendsAtsushi Nemoto2006-02-08
| | | | | | | | | | | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
| * [MIPS] Wire up new syscalls.Ralf Baechle2006-02-08
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
| * [MIPS] Make do_signal return void.Ralf Baechle2006-02-08
| | | | | | | | | | | | | | | | It's return value is ignored everywhere. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
| * [MIPS] Add support for TIF_RESTORE_SIGMASK.Ralf Baechle2006-02-08
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
* | [PATCH] mips: namespace pollution - mem_... -> __mem_... in io.hAl Viro2006-02-08
|/ | | | | | | A pile of internal functions use only inside mips io.h has names starting with mem_... and clashing with names in drivers; renamed to __mem_.... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* [PATCH] remove bogus asm/bug.h includes.Al Viro2006-02-07
| | | | | | | A bunch of asm/bug.h includes are both not needed (since it will get pulled anyway) and bogus (since they are done too early). Removed. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* [MIPS] TX49x7: Fix reporting of the CPU name and PCI clockSergei Shtylylov2006-02-07
| | | | | | | | | | | | | I've noticed that PCI clock was incorrectly reported as 66 MHz while being mere 33 MHz on RBTX4937 board -- this was due to the different encoding of the PCI divisor field in CCFG register between TX4927 and TX4937 chips... Also, RBTX49x7 was printed out as a CPU name (e.g., "CPU is RBTX4937"); and some debug printk() were duplicating each other... Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] TX49 MFC0 bug workaroundAtsushi Nemoto2006-02-07
| | | | | | | | | | | | | | If mfc0 $12 follows store and the mfc0 is last instruction of a page and fetching the next instruction causes TLB miss, the result of the mfc0 might wrongly contain EXL bit. ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 Workaround: mask EXL bit of the result or place a nop before mfc0. It doesn't harm to always clear those bits, so we change the code to do so. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MIPS R2 optimized endianess swapping.Ralf Baechle2006-02-07
| | | | | | From Franck Bui-Huu <vagabon.xyz@gmail.com> with modifications by me. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove buggy inline version of memscan.Ralf Baechle2006-02-07
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove wrong __user tags.Atsushi Nemoto2006-02-07
| | | | | | | This fixes sparse warnings 'dereference of noderef expression'. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cleanup fls implementation.Ralf Baechle2006-02-07
| | | | | | | fls was the only called of flz, so fold flz into fls, same for the __ilog2 call. Delete the now unused flz function. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] local_irq_restore wasn't safe to be used in other macros mode.Ralf Baechle2006-02-07
| | | | | | It always left the assembler in reorder mode possibly causing disaster. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Build blast_cache routines from templateAtsushi Nemoto2006-02-07
| | | | | | | | | Build blast_xxx, blast_xxx_page, blast_xxx_page_indexed from template. Easier to maintaina and saves 300 lines. Generated code should be unchanged. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Au1200: Make KGDB compileSergei Shtylylov2006-02-07
| | | | | | | | AMD Au1200 SOC just doesn't have UART3, so KGDB won't even compile for it as is, here's the fix to make KGDB use UART1. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] TX49x7: Fix timer register #define'sSergei Shtylylov2006-02-07
| | | | | | | | Fix the #define's for TX4927/37 timer reg's to match the datasheets (those Signed-off-by: Konstantin Baydarov <kbaidarov@mvista.com> Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Bullet proof uaccess.h against 4.0.1 miss-compilation.Ralf Baechle2006-02-07
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Nevada support for SGI O2.Ralf Baechle2006-02-07
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] CPU definitions for Cobalt.Ralf Baechle2006-02-07
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Rename include/asm-mips/cobalt to include/asm-mips/mach-cobalt.Ralf Baechle2006-02-07
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Rename _machine_power_off to pm_power_off so the kernel builds again.Ralf Baechle2006-02-07
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix C version of ssnop to use the right opcode.Ralf Baechle2006-02-07
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [PATCH] death of get_thread_info/put_thread_infoAl Viro2006-01-12
| | | | | | | | | {get,put}_thread_info() were introduced in 2.5.4 and never had been called by anything in the tree. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] mips: task_stack_page()Al Viro2006-01-12
| | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] mips: task_pt_regs()Al Viro2006-01-12
| | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] scheduler cache-hot-autodetectakpm@osdl.org2006-01-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ) From: Ingo Molnar <mingo@elte.hu> This is the latest version of the scheduler cache-hot-auto-tune patch. The first problem was that detection time scaled with O(N^2), which is unacceptable on larger SMP and NUMA systems. To solve this: - I've added a 'domain distance' function, which is used to cache measurement results. Each distance is only measured once. This means that e.g. on NUMA distances of 0, 1 and 2 might be measured, on HT distances 0 and 1, and on SMP distance 0 is measured. The code walks the domain tree to determine the distance, so it automatically follows whatever hierarchy an architecture sets up. This cuts down on the boot time significantly and removes the O(N^2) limit. The only assumption is that migration costs can be expressed as a function of domain distance - this covers the overwhelming majority of existing systems, and is a good guess even for more assymetric systems. [ People hacking systems that have assymetries that break this assumption (e.g. different CPU speeds) should experiment a bit with the cpu_distance() function. Adding a ->migration_distance factor to the domain structure would be one possible solution - but lets first see the problem systems, if they exist at all. Lets not overdesign. ] Another problem was that only a single cache-size was used for measuring the cost of migration, and most architectures didnt set that variable up. Furthermore, a single cache-size does not fit NUMA hierarchies with L3 caches and does not fit HT setups, where different CPUs will often have different 'effective cache sizes'. To solve this problem: - Instead of relying on a single cache-size provided by the platform and sticking to it, the code now auto-detects the 'effective migration cost' between two measured CPUs, via iterating through a wide range of cachesizes. The code searches for the maximum migration cost, which occurs when the working set of the test-workload falls just below the 'effective cache size'. I.e. real-life optimized search is done for the maximum migration cost, between two real CPUs. This, amongst other things, has the positive effect hat if e.g. two CPUs share a L2/L3 cache, a different (and accurate) migration cost will be found than between two CPUs on the same system that dont share any caches. (The reliable measurement of migration costs is tricky - see the source for details.) Furthermore i've added various boot-time options to override/tune migration behavior. Firstly, there's a blanket override for autodetection: migration_cost=1000,2000,3000 will override the depth 0/1/2 values with 1msec/2msec/3msec values. Secondly, there's a global factor that can be used to increase (or decrease) the autodetected values: migration_factor=120 will increase the autodetected values by 20%. This option is useful to tune things in a workload-dependent way - e.g. if a workload is cache-insensitive then CPU utilization can be maximized by specifying migration_factor=0. I've tested the autodetection code quite extensively on x86, on 3 P3/Xeon/2MB, and the autodetected values look pretty good: Dual Celeron (128K L2 cache): --------------------- migration cost matrix (max_cache_size: 131072, cpu: 467 MHz): --------------------- [00] [01] [00]: - 1.7(1) [01]: 1.7(1) - --------------------- cacheflush times [2]: 0.0 (0) 1.7 (1784008) --------------------- Here the slow memory subsystem dominates system performance, and even though caches are small, the migration cost is 1.7 msecs. Dual HT P4 (512K L2 cache): --------------------- migration cost matrix (max_cache_size: 524288, cpu: 2379 MHz): --------------------- [00] [01] [02] [03] [00]: - 0.4(1) 0.0(0) 0.4(1) [01]: 0.4(1) - 0.4(1) 0.0(0) [02]: 0.0(0) 0.4(1) - 0.4(1) [03]: 0.4(1) 0.0(0) 0.4(1) - --------------------- cacheflush times [2]: 0.0 (33900) 0.4 (448514) --------------------- Here it can be seen that there is no migration cost between two HT siblings (CPU#0/2 and CPU#1/3 are separate physical CPUs). A fast memory system makes inter-physical-CPU migration pretty cheap: 0.4 msecs. 8-way P3/Xeon [2MB L2 cache]: --------------------- migration cost matrix (max_cache_size: 2097152, cpu: 700 MHz): --------------------- [00] [01] [02] [03] [04] [05] [06] [07] [00]: - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) [01]: 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) [02]: 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) [03]: 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) [04]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) [05]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) [06]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) [07]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - --------------------- cacheflush times [2]: 0.0 (0) 19.2 (19281756) --------------------- This one has huge caches and a relatively slow memory subsystem - so the migration cost is 19 msecs. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Ken Chen <kenneth.w.chen@intel.com> Cc: <wilder@us.ibm.com> Signed-off-by: John Hawkes <hawkes@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] sched: add cacheflush() asmIngo Molnar2006-01-12
| | | | | | | | | | Add per-arch sched_cacheflush() which is a write-back cacheflush used by the migration-cost calibration code at bootup time. Signed-off-by: Ingo Molnar <mingo@elte.hu> Cc: Nick Piggin <nickpiggin@yahoo.com.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* MIPS: R2: Try to bulletproof instruction_hazard against miss-compilation.Ralf Baechle2006-01-10
| | | | | | | | | | | Gcc has a tradition of misscompiling the previous construct using the address of a label as argument to inline assembler. Gas otoh has the annoying difference between la and dla which are only usable for 32-bit rsp. 64-bit code, so can't be used without conditional compilation. The alterantive is switching the assembler to 64-bit code which happens to work right even for 32-bit code ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: R2: Fix local_irq_save()Maxime Bizon2006-01-10
| | | | | | | | | local_irq_restore uses di which saves the whole status content, not just the IE bit resulting in local_irq_restore() to fail. This only happens if both CONFIG_CPU_MIPSR2 and CONFIG_IRQ_CPU are enabled. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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