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* [MIPS] SMTC: Fix build error.Frank Rowand2008-01-21
| | | | | | | | Fix compile warning (which becomes compile error due to -Werror). Type of argument "flags" for spin_lock_irqsave() was incorrect in some functions. Signed-off-by: Frank Rowand <frank.rowand@am.sony.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cacheops.h: Fix typo.Ralf Baechle2008-01-14
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: fix PCI resource conflictSergei Shtylyov2007-12-14
| | | | | | | | | ... by getting the PCI resources back into the 32-bit range -- there's no need therefore for CONFIG_RESOURCES_64BIT either. This makes Alchemy PCI work again while currently the kernel skips the bus scan. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: Fix Au1x SD controller IRQManuel Lauss2007-12-08
| | | | | | | | With the introduction of MIPS_CPU_IRQ_BASE, the hardcoded IRQ number of the au1100/au1200 SD controller(s) is no longer valid. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: fix IRQ basesSergei Shtylyov2007-12-06
| | | | | | | | | Do what the commits commits f3e8d1da389fe2e514e31f6e93c690c8e1243849 and 9d360ab4a7568a8d177280f651a8a772ae52b9b9 failed to achieve -- actually convert the Alchemy code to irq_cpu. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix use of smp_processor_id() in preemptible code.Pavel Kiryukhin2007-11-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freeing prom memory: 956kb freed Freeing firmware memory: 978944k freed Freeing unused kernel memory: 180k freed BUG: using smp_processor_id() in preemptible [00000000] code: swapper/1 caller is r4k_dma_cache_wback_inv+0x144/0x2a0 Call Trace: [<80117af8>] r4k_dma_cache_wback_inv+0x144/0x2a0 [<802e4b84>] debug_smp_processor_id+0xd4/0xf0 [<802e4b7c>] debug_smp_processor_id+0xcc/0xf0 ... CONFIG_DEBUG_PREEMPT is enabled. -- Bug cause is blast_dcache_range() in preemptible code [in r4k_dma_cache_wback_inv()]. blast_dcache_range() is constructed via __BUILD_BLAST_CACHE_RANGE that uses cpu_dcache_line_size(). It uses current_cpu_data that use smp_processor_id() in turn. In case of CONFIG_DEBUG_PREEMPT smp_processor_id emits BUG if we are executing with preemption enabled. Cpu options of cpu0 are assumed to be the superset of all processors. Can I make the same assumptions for cache line size and fix this issue the following way: Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* IP22ZILOG: fix lockup and sysrqThomas Bogendoerfer2007-11-29
| | | | | | | | | | | | - fix lockup when switching from early console to real console - make sysrq reliable - fix panic, if sysrq is issued before console is opened Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [MIPS] 64-bit Sibyte kernels need DMA32.Ralf Baechle2007-11-26
| | | | | | | | | | | | Sibyte SOCs only have 32-bit PCI. Due to the sparse use of the address space only the first 1GB of memory is mapped at physical addresses below 1GB. If a system has more than 1GB of memory 32-bit DMA will not be able to reach all of it. For now this patch is good enough to keep Sibyte users happy but it seems eventually something like swiotlb will be needed for Sibyte. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Only build r4k clocksource for systems that work ok with it.Ralf Baechle2007-11-26
| | | | | | | | | | In particular as-is it's not suited for multicore and mutiprocessors systems where there is on guarantee that the counter are synchronized or running from the same clock at all. This broke Sibyte and probably others since the "[MIPS] Handle R4000/R4400 mfc0 from count register." commit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Handle R4000/R4400 mfc0 from count register.Ralf Baechle2007-11-26
| | | | | | | | | | | | | | | | | | | | | The R4000 and R4400 have an errata where if the cp0 count register is read in the exact moment when it matches the compare register no interrupt will be generated. This bug may be triggered if the cp0 count register is being used as clocksource and the compare interrupt as clockevent. So a simple workaround is to avoid using the compare for both facilities on the affected CPUs. This is different from the workaround suggested in the old errata documents; at some opportunity probably the official version should be implemented and tested. Another thing to find out is which processor versions exactly are affected. I only have errata documents upto R4400 V3.0 available so for the moment the code treats all R4000 and R4400 as broken. This is potencially a problem for some machines that have no other decent clocksource available; this workaround will cause them to fall back to another clocksource, worst case the "jiffies" source.
* [MIPS] Fix possible hang in LL/SC futex loops.Ralf Baechle2007-11-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LL / SC loops in __futex_atomic_op() have the usual fixups necessary for memory acccesses to userspace from kernel space installed: __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: ll %1, %4 # __futex_atomic_op \n" " .set mips0 \n" " " insn " \n" " .set mips3 \n" "2: sc $1, %2 \n" " beqz $1, 1b \n" __WEAK_LLSC_MB "3: \n" " .set pop \n" " .set mips0 \n" " .section .fixup,\"ax\" \n" "4: li %0, %6 \n" " j 2b \n" <----- " .previous \n" " .section __ex_table,\"a\" \n" " "__UA_ADDR "\t1b, 4b \n" " "__UA_ADDR "\t2b, 4b \n" " .previous \n" : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) : "memory"); The branch at the end of the fixup code, it goes back to the SC instruction, no matter if the fault was first taken by the LL or SC instruction resulting in an endless loop which will only terminate if the address become valid again due to another thread setting up an accessible mapping and the CPU happens to execute the SC instruction successfully which due to the preceeding ERET instruction of the fault handler would only happen if UNPREDICTABLE instruction behaviour of the SC instruction without a preceeding LL happens to favor that outcome. But normally processes are nice, pass valid arguments and we were just getting away with this. Thanks to Kaz Kylheku <kaz@zeugmasystems.com> for providing the original report and a test case. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix context DSP context / TLS pointer switching bug for new threads.Ralf Baechle2007-11-26
| | | | | | | | | | | | | | | | | | | | | | | A new born thread starts execution not in schedule but rather in ret_from_fork which results in it bypassing the part of the code to load a new context written in C which are the DSP context and the userlocal register which Linux uses for the TLS pointer. Frequently we were just getting away with this bug for a number of reasons: o Real world application scenarios are very unlikely to use clone or fork in blocks of DSP code. o Linux by default runs the child process right after the fork, so the child by luck will find all the right context in the DSP and userlocal registers. o So far the rdhwr instruction was emulated on all hardware so userlocal wasn't getting referenced at all and the emulation wasn't suffering from the issue since it gets it's value straight from the thread's thread_info. Fixed by moving the code to load the context from switch_to() to finish_arch_switch which will be called by newborn and old threads. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP32: More interrupt renumbering fixes.Ralf Baechle2007-11-26
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix pcspeaker build.Ralf Baechle2007-11-26
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Lasat: Fix overlap of interrupt number ranges.Yoichi Yuasa2007-11-15
| | | | | | | The range of MIPS_CPU IRQ and the range of LASAT IRQ overlap. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix shadow register support.Ralf Baechle2007-11-15
| | | | | | | | | | | | | Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Change get_cycles to always return 0.Ralf Baechle2007-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | This avoids us executing an mfc0 c0_count instruction on processors which don't have but also on certain R4000 and R4400 versions where reading from the count register just in the very moment when its value equals c0_compare will result in the timer interrupt getting lost. There is still a number of users of get_cycles remaining outside the arch code: crypto/tcrypt.c: start = get_cycles(); crypto/tcrypt.c: end = get_cycles(); crypto/tcrypt.c: start = get_cycles(); crypto/tcrypt.c: end = get_cycles(); crypto/tcrypt.c: start = get_cycles(); crypto/tcrypt.c: end = get_cycles(); drivers/char/hangcheck-timer.c: return get_cycles(); drivers/char/hangcheck-timer.c: printk("Hangcheck: Using get_cycles().\n"); drivers/char/random.c: sample.cycles = get_cycles(); drivers/input/joystick/analog.c:#define GET_TIME(x) do { x = get_cycles(); } include/linux/arcdevice.h: _x = get_cycles(); \ include/linux/arcdevice.h: _y = get_cycles(); \ mm/slub.c: if (!s->defrag_ratio || get_cycles() % 1024 > s->defrag_ratio) mm/slub.c: p += 64 + (get_cycles() & 0xff) * sizeof(void *); Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Use i8253.c lock for PC speaker on MIPS, too.Ralf Baechle2007-11-02
| | | | | | | | | | The Jazz machines have to use the PIT timer for dyntick and highresolution kernels. This may break because currently just like i386 used to do MIPS uses two separate spinlocks in the actual PIT code and the PC speaker code. So switch to do it the same that x86 currently does PIT locking. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [MIPS] Fix and cleanup the MIPS part of the (ab)use of CLOCK_TICK_RATE.Ralf Baechle2007-11-02
| | | | | | | | | This is the clock rate of the i8253 PIT. A MIPS system may not have a PIT by the symbol is used all over the kernel including some APIs. So keeping it defined to the number for the PIT is the only sane thing for now. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] i8253.h: Remove all i8259 related definitions.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cobalt: Fix IRQ comment; the Cobalt kernel uses CP0 counter now.Yoichi Yuasa2007-11-02
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Code cleanupsAtsushi Nemoto2007-11-02
| | | | | | | | | | | | | * Do not include unnecessary headers. * Do not mention time.README. * Do not mention mips_timer_ack. * Make clocksource_mips static. It is now dedicated to c0_timer. * Initialize clocksource_mips.read statically. * Remove null_hpt_read. * Remove an argument of plat_timer_setup. It is just a placeholder. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Remove now unused local_timer_interrupt.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Replace plat_timer_setup with modern APIs.Ralf Baechle2007-10-29
| | | | | | plat_timer_setup is no longer getting called. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] txx9tmr clockevent/clocksource driverAtsushi Nemoto2007-10-29
| | | | | | | | | | | | | | Convert jmr3927_clock_event_device to more generic txx9tmr_clock_event_device which supports one-shot mode. The txx9tmr_clock_event_device can be used for TX49 too if the cp0 timer interrupt was not available. Convert jmr3927_hpt_read to txx9_clocksource driver which does not depends jiffies anymore. The txx9_clocksource itself can be used for TX49, but normally TX49 uses higher precision clocksource_mips. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP32: Fixes after interrupt renumbering.Ralf Baechle2007-10-29
| | | | | | And general untangling. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Remove declaration of plat_timer_setup, there is no caller.Ralf Baechle2007-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2007-10-22
|\ | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] time: Make c0_compare_int_usable more bullet proof [MIPS] Kbuild: Use the new cc-cross-prefix feature. [MIPS] Fix include wrapper symbol to something sane. [MIPS] Malta: Delete dead code. [MIPS] time: Add GT641xx timer0 clockevent driver [MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code. [MIPS] time: SMP/NUMA-proofing of IP27 HUB RT timer code. [MIPS] time: Fix calculation in clockevent_set_clock()
| * [MIPS] Fix include wrapper symbol to something sane.Ralf Baechle2007-10-22
| | | | | | | | | | | | And why are there i8253.h and 8253pit.h ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] time: Add GT641xx timer0 clockevent driverYoichi Yuasa2007-10-22
| | | | | | | | | | | | | | | | And make use of it for Cobalt. A few others such as the Malta could make use of it as well. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code.Ralf Baechle2007-10-22
| | | | | | | | | | | | | | | | | | | | | | The BCM148 has 4 cores but there are also just 4 generic timers available so use the ZBbus cycle counter instead of it. In addition the ZBbus counter also offers a much higher resolution and 64-bit counting so I'm considering a later complete conversion to it once I figure out if all members of the Sibyte SOC family support it - the docs seem to agree but the headers files seem to disagree ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Add CONFIG_DEBUG_SG sg validationJens Axboe2007-10-22
| | | | | | | | | | | | | | Add a Kconfig entry which will toggle some sanity checks on the sg entry and tables. Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
* | Change table chaining layoutJens Axboe2007-10-22
|/ | | | | | | | | | | | | | | | | Change the page member of the scatterlist structure to be an unsigned long, and encode more stuff in the lower bits: - Bits 0 and 1 zero: this is a normal sg entry. Next sg entry is located at sg + 1. - Bit 0 set: this is a chain entry, the next real entry is at ->page_link with the two low bits masked off. - Bit 1 set: this is the final entry in the sg entry. sg_next() will return NULL when passed such an entry. It's thus important that sg table users use the proper accessors to get and set the page member. Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivialLinus Torvalds2007-10-19
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial: (74 commits) fix do_sys_open() prototype sysfs: trivial: fix sysfs_create_file kerneldoc spelling mistake Documentation: Fix typo in SubmitChecklist. Typo: depricated -> deprecated Add missing profile=kvm option to Documentation/kernel-parameters.txt fix typo about TBI in e1000 comment proc.txt: Add /proc/stat field small documentation fixes Fix compiler warning in smount example program from sharedsubtree.txt docs/sysfs: add missing word to sysfs attribute explanation documentation/ext3: grammar fixes Documentation/java.txt: typo and grammar fixes Documentation/filesystems/vfs.txt: typo fix include/asm-*/system.h: remove unused set_rmb(), set_wmb() macros trivial copy_data_pages() tidy up Fix typo in arch/x86/kernel/tsc_32.c file link fix for Pegasus USB net driver help remove unused return within void return function Typo fixes retrun -> return x86 hpet.h: remove broken links ...
| * Fix misspellings of "system", "controller", "interrupt" and "necessary".Robert P. J. Day2007-10-19
| | | | | | | | | | | | | | | | Fix the various misspellings of "system", controller", "interrupt" and "[un]necessary". Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Adrian Bunk <bunk@kernel.org>
* | ide: add CONFIG_IDE_ARCH_OBSOLETE_INITBartlomiej Zolnierkiewicz2007-10-19
|/ | | | | | | Add CONFIG_IDE_ARCH_OBSOLETE_INIT to drivers/ide/Kconfig and use it instead of defining IDE_ARCH_OBSOLETE_INIT in <arch/ide.h>. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2007-10-19
|\ | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Delete totally outdated Documentation/mips/time.README [MIPS] Kill duplicated setup_irq() for cp0 timer [MIPS] Sibyte: Finish conversion to modern time APIs. [MIPS] time: Helpers to compute clocksource/event shift and mult values. [MIPS] SMTC: Build fix. [MIPS] time: Delete dead code. [MIPS] MIPSsim: Strip defconfig file to the bones.
| * [MIPS] Kill duplicated setup_irq() for cp0 timerAtsushi Nemoto2007-10-19
| | | | | | | | | | | | | | Also many plat_timer_setup() can be killed too. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] time: Helpers to compute clocksource/event shift and mult values.Ralf Baechle2007-10-19
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | define global BIT macroJiri Slaby2007-10-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | define global BIT macro move all local BIT defines to the new globally define macro. Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Kumar Gala <galak@gate.crashing.org> Cc: Dmitry Torokhov <dtor@mail.ru> Cc: Jeff Garzik <jeff@garzik.org> Cc: James Bottomley <James.Bottomley@steeleye.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: Russell King <rmk@arm.linux.org.uk> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: "John W. Linville" <linville@tuxdriver.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | forbid asm/bitops.h direct inclusionJiri Slaby2007-10-19
| | | | | | | | | | | | | | | | | | | | | | | | | | forbid asm/bitops.h direct inclusion Because of compile errors that may occur after bit changes if asm/bitops.h is included directly without e.g. linux/kernel.h which includes linux/bitops.h, forbid direct inclusion of asm/bitops.h. Thanks to Adrian Bunk. Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Cc: Adrian Bunk <bunk@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | remove asm/bitops.h includesJiri Slaby2007-10-19
| | | | | | | | | | | | | | | | | | | | | | | | | | remove asm/bitops.h includes including asm/bitops directly may cause compile errors. don't include it and include linux/bitops instead. next patch will deny including asm header directly. Cc: Adrian Bunk <bunk@kernel.org> Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | remove unused flush_tlb_pgtablesBenjamin Herrenschmidt2007-10-19
|/ | | | | | | | | | Nobody uses flush_tlb_pgtables anymore, this patch removes all remaining traces of it from all archs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2007-10-18
|\ | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] time: Move R4000 clockevent device code to separate configurable file [MIPS] time: Delete dead cycles_per_jiffy, mips_timer_ack and null_timer_ack [MIPS] IP32: Retire use of plat_timer_setup. [MIPS] Jazz: Retire use of plat_timer_setup. [MIPS] IP27: Convert to clock_event_device. [MIPS] JMR3927: Convert to clock_event_device. [MIPS] Always do the ARC64_TWIDDLE_PC thing.
| * [MIPS] time: Move R4000 clockevent device code to separate configurable fileRalf Baechle2007-10-18
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] time: Delete dead cycles_per_jiffy, mips_timer_ack and null_timer_ackRalf Baechle2007-10-18
| | | | | | | | | | | | | | | | | | | | cycles_per_jiffy was only ever getting assigned and the function pointer not being called anymore and mips_timer_ack had gotten similarly stale. I leave the remaining assignments unfixed as a lighthouse pointing platform maintainers to what needs a rewrite. These changes make null_timer_ack() unreferenced, so delete that too. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Always do the ARC64_TWIDDLE_PC thing.Thomas Bogendoerfer2007-10-18
| | | | | | | | | | | | | | | | Always jump to the place where the kernel is linked to. This helps where the bootloaders/proms ignores the start address inside the ELF header. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | mips: lock bitopsNick Piggin2007-10-18
| | | | | | | | | | | | | | | | | | mips can avoid one mb when acquiring a lock with test_and_set_bit_lock. Signed-off-by: Nick Piggin <npiggin@suse.de> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | mips: fix bitopsNick Piggin2007-10-18
| | | | | | | | | | | | | | | | | | | | | | Documentation/atomic_ops.txt defines these primitives must contain a memory barrier both before and after their memory operation. This is consistent with the atomic ops implementation on mips. Signed-off-by: Nick Piggin <npiggin@suse.de> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | bitops: introduce lock opsNick Piggin2007-10-18
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce test_and_set_bit_lock / clear_bit_unlock bitops with lock semantics. Convert all architectures to use the generic implementation. Signed-off-by: Nick Piggin <npiggin@suse.de> Acked-By: David Howells <dhowells@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Haavard Skinnemoen <hskinnemoen@atmel.com> Cc: Bryan Wu <bryan.wu@analog.com> Cc: Mikael Starvik <starvik@axis.com> Cc: David Howells <dhowells@redhat.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Hirokazu Takata <takata@linux-m32r.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Roman Zippel <zippel@linux-m68k.org> Cc: Greg Ungerer <gerg@uclinux.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Kyle McMartin <kyle@mcmartin.ca> Cc: Matthew Wilcox <willy@debian.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Kazumoto Kojima <kkojima@rr.iij4u.or.jp> Cc: Richard Curnow <rc@rc0.org.uk> Cc: William Lee Irwin III <wli@holomorphy.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jeff Dike <jdike@addtoit.com> Cc: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it> Cc: Miles Bader <uclinux-v850@lsi.nec.co.jp> Cc: Andi Kleen <ak@muc.de> Cc: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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