| Commit message (Expand) | Author | Age |
* | [MIPS] Fix use of smp_processor_id() in preemptible code. | Pavel Kiryukhin | 2007-11-30 |
* | [MIPS] Allow hardwiring of the CPU type to a single type for optimization. | Ralf Baechle | 2007-10-11 |
* | [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. | Ralf Baechle | 2007-10-11 |
* | [MIPS] Enable support for the userlocal hardware register | Ralf Baechle | 2007-07-10 |
* | [MIPS] FPU ownership management & preemption fixes | Atsushi Nemoto | 2007-03-16 |
* | [MIPS] Use the proper technical term for naming some of the cache macros. | Ralf Baechle | 2006-07-13 |
* | [MIPS] Default cpu_has_mipsmt to a runtime check | Chris Dearman | 2006-07-13 |
* | [MIPS] Fix configuration of R2 CPU features and multithreading. | Ralf Baechle | 2006-06-29 |
* | Don't include linux/config.h from anywhere else in include/ | David Woodhouse | 2006-04-26 |
* | [MIPS] FPU affinity for MT ASE. | Ralf Baechle | 2006-04-18 |
* | [MIPS] local_r4k_flush_cache_page fix | Atsushi Nemoto | 2006-03-18 |
* | MIPS: Reorganize ISA constants strictly as bitmasks. | Ralf Baechle | 2006-01-10 |
* | MIPS: Introduce machinery for testing for MIPSxxR1/2. | Ralf Baechle | 2006-01-10 |
* | Cleanup the mess in cpu_cache_init. | Ralf Baechle | 2005-10-29 |
* | Detect the MIPS R2 vectored interrupt, external interrupt controller | Ralf Baechle | 2005-10-29 |
* | Redo RM9000 workaround which along with other DSP ASE changes was | Ralf Baechle | 2005-10-29 |
* | Support the MIPS32 / MIPS64 DSP ASE. | Ralf Baechle | 2005-10-29 |
* | Cleanup decoding of MIPSxx config registers. | Ralf Baechle | 2005-10-29 |
* | [PATCH] mips: clean up 32/64-bit configuration | Ralf Baechle | 2005-09-05 |
* | Linux-2.6.12-rc2v2.6.12-rc2 | Linus Torvalds | 2005-04-16 |