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path: root/include/asm-ia64/pal.h
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* [IA64] PAL calls need physical mode, stackedRuss Anderson2006-09-26
| | | | | | | | PAL_CACHE_READ and PAL_CACHE_WRITE need to be called in physical mode with stacked registers. Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck <tony.luck@intel.com>
* Pull model-name into release branchTony Luck2006-09-26
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| * [IA64] Add "model name" to /proc/cpuinfoTony Luck2006-06-05
| | | | | | | | | | | | | | | | | | | | | | | | Linux ia64 port tried to decode the processor family number to something human-readable, but Intel brandnames don't change synchronously with updates to the family number. Adopt a more i386-like approach and just print the family number in decimal. Add a new field "model name" that uses PAL_BRAND_INFO to find the official name for the cpu, or on older systems, falls back to using the well-known codenames (Merced, McKinley, Madison). Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64] Format /proc/pal/*/version_info correctlyMatthew Wilcox2006-07-31
|/ | | | | | | | | | | /proc/pal/*/version_info is a bit confusing. HP firmware, at least, reports 07.31 instead of 0.7.31. Also, the comment is out of place; it's an internal detail about the implementation of ia64_pal_version. Since the 2.2 revision of the SDM still states that PAL_VERSION can be called in virtual mode, correct the comment to be more accurate. Signed-off-by: Matthew Wilcox <matthew@wil.cx> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Avoid "u64 foo : 32;" for gcc3 vs. gcc4 compatibilityTony Luck2006-03-31
| | | | | | | | gcc3 thinks that a 32-bit field of a u64 type is itself a u64, so should be printed with "%ld". gcc4 thinks it needs just "%d". Make both versions happy by avoiding this construct. Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Export cpu cache info by sysfsZhang, Yanmin2006-03-30
| | | | | | | | | | | | | | | | The patch exports 8 attributes of cpu cache info under /sys/devices/system/cpu/cpuX/cache/indexX: 1) level 2) type 3) coherency_line_size 4) ways_of_associativity 5) size 6) shared_cpu_map 7) attributes 8) number_of_sets: number_of_sets=size/ways_of_associativity/coherency_line_size. Signed-off-by: Zhang Yanmin <yanmin.zhang@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] New IA64 core/thread detection patchFenghua Yu2006-03-24
| | | | | | | | | | | | | | IPF SDM 2.2 changes definition of PAL_LOGICAL_TO_PHYSICAL to add proc_number=-1 to get core/thread mapping info on the running processer. Based on this change, we had better to update existing core/thread detection in IA64 kernel correspondingly. The attached patch implements this change. It simplifies detection code and eliminates potential race condition. It also runs a bit faster and has better scalability especially when cores and threads number grows up in one package. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] pal cache flush patchXu, Anthony2006-01-16
| | | | | | | | | | | | Because PAL spec has changed since 2002, you can goto http://developer.intel.com/design/itanium/manuals/iiasdmanual.htm to download new SDM, all PAL calls should be invoked with psr.ic=1, and it's caller's responsibility to handle possible tlb miss. Ia64_pal_cache_flush was written according to old spec, it is obsolete, and this patch has ia64_pal_cache_flush conform to new spec. Signed-off-by Anthony Xu <anthony.xu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Add ACPI based P-state supportVenkatesh Pallipadi2005-08-26
| | | | | | | | | | | | | | | | | | | | Patch to support P-state transitions on ia64. This driver is based on ACPI, and uses the ACPI processor driver interface to find out the P-state support information for the processor. This driver plugs into generic cpufreq infrastructure. Once this driver is loaded successfully, ondemand/userspace governor can be used to change the CPU frequency dynamically based on load or on request from userspace process. Refer : ACPI specification - http://www.acpi.info P-state related PAL calls - http://developer.intel.com/design/itanium/downloads/24869909.pdf Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] multi-core/multi-thread identificationSuresh Siddha2005-04-25
| | | | | | | | | | | | | | | | | | | | | | Version 3 - rediffed to apply on top of Ashok's hotplug cpu patch. /proc/cpuinfo output in step with x86. This is an updated MC/MT identification patch based on the previous discussions on list. Add the Multi-core and Multi-threading detection for IPF. - Add new core and threading related fields in /proc/cpuinfo. Physical id Core id Thread id Siblings - setup the cpu_core_map and cpu_sibling_map appropriately - Handles Hot plug CPU Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Gordon Jin <gordon.jin@intel.com> Signed-off-by: Rohit Seth <rohit.seth@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-16
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!