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dma_cache_(wback|inv|wback_inv) were the earliest attempt on a generalized
cache managment API for I/O purposes. Originally it was basically the raw
MIPS low level cache API exported to the entire world. The API has
suffered from a lack of documentation, was not very widely used unlike it's
more modern brothers and can easily be replaced by dma_cache_sync. So
remove it rsp. turn the surviving bits back into an arch private API, as
discussed on linux-arch.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Acked-by: Paul Mackerras <paulus@samba.org>
Acked-by: David S. Miller <davem@davemloft.net>
Acked-by: Kyle McMartin <kyle@parisc-linux.org>
Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Cc: <linux-arch@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Add empty definition of mmiowb() since some drivers need it. Uncached
writes are strongly ordered on AVR32. They may be delayed if the
dcache is busy doing a writeback, but AFAICT that's not what this
macro is supposed to deal with, at least on UP systems.
We might have to revisit this definition when a SMP-capable AVR32 CPU
comes along, depending on how the busses and cache coherency stuff
end up being implemented.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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Using readb/writeb to implement these breaks NOR flash support. I
can't see any reason why regular memcpy and memset shouldn't work.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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Fix the I/O access macros so that they work with externally connected
devices accessed in little-endian mode over any bus width:
* Use a set of macros to define I/O port- and memory operations
borrowed from MIPS.
* Allow subarchitecture to specify address- and data-mangling
* Implement at32ap-specific port mangling (with build-time
configurable bus width. Only one bus width at a time supported
for now.)
* Rewrite iowriteN and friends to use write[bwl] and friends
(not the __raw counterparts.)
This has been tested using pata_pcmcia to access a CompactFlash card
connected to the EBI (16-bit bus width.)
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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These are all defined in terms of ioremap/iounmap since port I/O
isn't really different from memory-mapped I/O on AVR32.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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The first parameter to __raw_writes[bwl] and __raw_reads[bwl] should
be a void __iomem *, not unsigned long.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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A number of new drivers require io{read,write}{8,16,32}{be,} family of io
operations. These are provided for the AVR32 by this patch in the form of
a series of macros.
Access to the (memory mapped) io space through these macros is defined to
be little endian only as little endian devices (such as PCI) are the main
consumer of IO access. If high speed access is required,
io{read,write}{16,32}be macros are supplied to perform native big endian
access to this io space.
Signed-off-by: Ben Nizette <ben@mallochdigital.com>
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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This adds support for the Atmel AVR32 architecture as well as the AT32AP7000
CPU and the AT32STK1000 development board.
AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for
cost-sensitive embedded applications, with particular emphasis on low power
consumption and high code density. The AVR32 architecture is not binary
compatible with earlier 8-bit AVR architectures.
The AVR32 architecture, including the instruction set, is described by the
AVR32 Architecture Manual, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf
The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It
features a 7-stage pipeline, 16KB instruction and data caches and a full
Memory Management Unit. It also comes with a large set of integrated
peripherals, many of which are shared with the AT91 ARM-based controllers from
Atmel.
Full data sheet is available from
http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf
while the CPU core implementation including caches and MMU is documented by
the AVR32 AP Technical Reference, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf
Information about the AT32STK1000 development board can be found at
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918
including a BSP CD image with an earlier version of this patch, development
tools (binaries and source/patches) and a root filesystem image suitable for
booting from SD card.
Alternatively, there's a preliminary "getting started" guide available at
http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links
to the sources and patches you will need in order to set up a cross-compiling
environment for avr32-linux.
This patch, as well as the other patches included with the BSP and the
toolchain patches, is actively supported by Atmel Corporation.
[dmccr@us.ibm.com: Fix more pxx_page macro locations]
[bunk@stusta.de: fix `make defconfig']
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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