| Commit message (Collapse) | Author | Age |
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Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch is to add the third mmc controller support _only_
for pxa310.
On zylonite, the third controller support one slot.
Signed-off-by: Bridge Wu <bridge.wu@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch is to add the second mmc controller support for pxa3xx.
It's valid for pxa3[0|1|2]0.
On zylonite, the second controller has no slot.
Signed-off-by: Bridge Wu <bridge.wu@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patchis to add the first mmc controller support for pxa3xx.
It's valid for pxa3[0|1|2]0.
On zylonite, the first controller supports two slots, this patch
only support the first one right now.
Signed-off-by: Bridge Wu <bridge.wu@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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FFUART and friends are already defined as __REG(x) in pxa-regs.h.
Instead of redefining them here, we can just provide the __REG macro.
Including asm/arch/hardware.h is not an option because this physical
addresses are needed here.
This is a fix for the compiler warnings generated by 4663/1.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Acked-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1. make pxa2xx_spi.c use ssp_request() and ssp_free() to get the common
information of the designated SSP port.
2. remove those IRQ/memory request code, ssp_request() has done that for
the driver
3. the SPI platform device is thus made psuedo, no resource (memory/IRQ)
has to be defined, all will be retreived by ssp_request()
4. introduce ssp_get_clk_div() to handle controller difference in clock
divisor setting
5. use clk_xxx() API for clock enable/disable, and clk_get_rate() to
handle the different SSP clock frequency between different processors
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1. change SSP register definitions from absolute virtual addresses to
offsets
2. use __raw_writel()/__raw_readl() for functions of ssp_xxxx()
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1. define "struct ssp_device" for SSP information, which is requested
and released by function ssp_request()/ssp_free()
2. modify the ssp_init() and ssp_exit() to use the interface
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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the bootloader
Also, use existing register and bit definitions instead of numbers.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Acked-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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* orion: (26 commits)
[ARM] Orion: implement power-off method for QNAP TS-109/209
[ARM] Orion: add support for QNAP TS-109/TS-209
[ARM] Orion: I2C support
[I2C] i2c-mv64xxx: Don't set i2c_adapter.retries
[I2C] Split mv643xx I2C platform support
[ARM] Orion: enable CONFIG_RTC_DRV_M41T80 for D-Link DNS-323
[ARM] Orion defconfig
[ARM] Orion: add support for Orion/MV88F5181 based D-Link DNS-323
[ARM] Orion: MV88F5181 support bits
[ARM] Orion: Buffalo/Revogear Kurobox Pro support
[ARM] OrionNAS RD board support
[ARM] Orion: support for Marvell Orion-2 (88F5281) Development Board
[ARM] Orion: common platform setup for Gigabit Ethernet port
[ARM] Orion: platform device registration for UART, USB and NAND
[ARM] Orion: system timer support
[ARM] Orion edge GPIO IRQ support
[ARM] Orion: IRQ support
[ARM] Orion: provide GPIO method for enabling hardware assisted blinking
[ARM] Orion: GPIO support
[ARM] Orion: programable address map support
...
Conflicts:
arch/arm/Kconfig
arch/arm/Makefile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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add MV88F5181 support bits required by D-link DNS-323 patch
Signed-off-by: Herbert Valerio Riedel <hvr@gnu.org>
Acked-by: Tzachi Perelstein <tzachi@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This is a pre-requisite for implementing proper hardware accelerated
GPIO LED flashing, and since we want proper locking, it's sensible to provide
the orion specific orion_gpio_set_blink() implementation within
mach-orion/gpio.c. The functions orion_gpio_set_blink() and gpio_set_value()
implicitly turn off each others state.
Signed-off-by: Herbert Valerio Riedel <hvr@gnu.org>
Acked-by: Tzachi Perelstein <tzachi@marvell.com>
Acked-by: Nicolas Pitre <nico@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Acked-by: David Brownell <david-b@pacbell.net>
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The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The Feroceon is a family of independent ARMv5TE compliant CPU core
implementations, supporting a variable depth pipeline and out-of-order
execution. The Feroceon is configurable with VFP support, and the
later models in the series are superscalar with up to two instructions
per clock cycle.
This patch adds the initial low-level cache/TLB handling for this core.
Signed-off-by: Assaf Hoffman <hoffman@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
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's3c2410', 'sa1100' and 'vfp' into devel
* at91: (24 commits)
[ARM] 4615/4: sam926[13]ek buttons updated
[ARM] 4765/1: [AT91] AT91CAP9A-DK board support
[ARM] 4764/1: [AT91] AT91CAP9 core support
[ARM] 4738/1: at91sam9261: Remove udc pullup enabling in board initialisation
[ARM] 4761/1: [AT91] Board-support for NEW_LEDs
[ARM] 4760/1: [AT91] SPI CS0 errata on AT91RM9200
[ARM] 4759/1: [AT91] Buttons on CSB300
[ARM] 4758/1: [AT91] LEDs
[ARM] 4757/1: [AT91] UART initialization
[ARM] 4756/1: [AT91] Makefile cleanup
[ARM] 4755/1: [AT91] NAND update
[ARM] 4754/1: [AT91] SSC library support
[ARM] 4753/1: [AT91] Use DMA_BIT_MASK
[ARM] 4752/1: [AT91] RTT, RTC and WDT peripherals on SAM9
[ARM] 4751/1: [AT91] ISI peripheral on SAM9263
[ARM] 4750/1: [AT91] STN LCD displays on SAM9261
[ARM] 4734/1: at91sam9263ek: include IRQ for Ethernet PHY
[ARM] 4646/1: AT91: configurable HZ, default to 128
[ARM] 4688/1: at91: speed-up irq processing
[ARM] 4657/1: AT91: Header definition update
...
* ep93xx:
[ARM] 4671/1: ep93xx: remove obsolete gpio_line_* operations
[ARM] 4670/1: ep93xx: implement IRQT_BOTHEDGE gpio irq sense type
[ARM] 4669/1: ep93xx: simplify GPIO code and cleanups
[ARM] 4668/1: ep93xx: implement new GPIO API
* iop:
[ARM] 4770/1: GLAN Tank: correct physmap_flash_data width field
[ARM] 4732/1: GLAN Tank: register rtc-rs5c372 i2c device
[ARM] 4708/1: iop: update defconfigs for 2.6.24
* kprobes:
ARM kprobes: let's enable it
ARM kprobes: special hook for the kprobes breakpoint handler
ARM kprobes: prevent some functions involved with kprobes from being probed
ARM kprobes: don't let a single-stepped stmdb corrupt the exception stack
ARM kprobes: add the kprobes hook to the page fault handler
ARM kprobes: core code
ARM kprobes: instruction single-stepping support
* ks8695:
[ARM] 4603/1: KS8695: debugfs interface to view pin state
[ARM] 4601/1: KS8695: PCI support
* misc:
[ARM] remove duplicate includes
[ARM] CONFIG_DEBUG_STACK_USAGE
[ARM] 4689/1: small comment wrap fix
[ARM] 4687/1: Trivial arch/arm/kernel/entry-common.S comment fix
[ARM] 4666/1: ixp4xx: fix sparse warnings in include/asm-arm/arch-ixp4xx/io.h
[ARM] remove reference to non-existent MTD_OBSOLETE_CHIPS
[SERIAL] 21285: Report baud rate back via termios
[ARM] Remove pointless casts from void pointers,
[ARM] Misc minor interrupt handler cleanups
[ARM] Remove at91_lcdc.h
[ARM] ARRAY_SIZE() cleanup
[ARM] Update mach-types
* msm:
[ARM] msm: dma support for MSM7X00A
[ARM] msm: board file for MACH_HALIBUT (QCT MSM7200A)
[ARM] msm: irq and timer support for ARCH_MSM7X00A
[ARM] msm: core platform support for ARCH_MSM7X00A
* s3c2410: (33 commits)
[ARM] 4795/1: S3C244X: Add armclk and setparent call
[ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code
[ARM] 4793/1: S3C24XX: Add IRQ->GPIO pin mapping function
[ARM] 4792/1: S3C24XX: Remove warnings from debug-macro.S
[ARM] 4791/1: S3C2412: Make fclk a parent of msysclk
[ARM] 4790/1: S3C2412: Fix parent selection for msysclk.
[ARM] 4789/1: S3C2412: Add missing CLKDIVN register values
[ARM] 4788/1: S3C24XX: Fix paramet to s3c2410_dma_ctrl if S3C2410_DMAF_AUTOSTART used.
[ARM] 4787/1: S3C24XX: s3c2410_dma_request() should return the allocated channel number
[ARM] 4786/1: S3C2412: Add SPI FIFO controll constants
[ARM] 4785/1: S3C24XX: Add _SHIFT definitions for S3C2410_BANKCON registers
[ARM] 4784/1: S3C24XX: Fix GPIO restore glitches
[ARM] 4783/1: S3C24XX: Add s3c2410_gpio_getpull()
[ARM] 4782/1: S3C24XX: Define FIQ_START for any FIQ users
[ARM] 4781/1: S3C24XX: DMA suspend and resume support
[ARM] 4780/1: S3C2412: Allow for seperate DMA channels for TX and RX
[ARM] 4779/1: S3C2412: Add s3c2412_gpio_set_sleepcfg() call
[ARM] 4778/1: S3C2412: Add armclk and init from DVS state
[ARM] 4777/1: S3C24XX: Ensure clk_set_rate() checks the set_rate method for the clk
[ARM] 4775/1: s3c2410: fix compilation error if only s3c2442 cpu is selected
...
* sa1100:
[ARM] sa1100: add clock source support
* vfp:
[ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support
[ARM] 4583/1: ARMv7: Add VFPv3 support
[ARM] 4582/2: Add support for the common VFP subarchitecture
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This patch adds the support for VFPv3 (the kernel currently supports
VFPv2). The main difference is 32 double registers (compared to 16).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch allows the VFP support code to run correctly on CPUs
compatible with the common VFP subarchitecture specification (Appendix
B in the ARM ARM v7-A and v7-R edition). It implements support for VFP
subarchitecture 2 while being backwards compatible with
subarchitecture 1.
On VFP subarchitecture 1, the arithmetic exceptions are asynchronous
(or imprecise as described in the old ARM ARM) unless the FPSCR.IXE
bit is 1. The exceptional instructions can be read from FPINST and
FPINST2 registers. With VFP subarchitecture 2, the arithmetic
exceptions can also be synchronous and marked by the FPEXC.DEX bit
(the FPEXC.EX bit is cleared). CPUs implementing the synchronous
arithmetic exceptions don't have the FPINST and FPINST2 registers and
accessing them would trigger and undefined exception.
Note that FPEXC.EX bit has an additional meaning on subarchitecture 1
- if it isn't set, there is no additional information in FPINST and
FPINST2 that needs to be saved at context switch or when lazy-loading
the VFP state of a different thread.
The patch also removes the clearing of the cumulative exception flags in
FPSCR when additional exceptions were raised. It is up to the user
application to clear these bits.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add the reverse of s3c2410_gpio_getirq to convert
a IRQ number into a GPIO pin number.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Remove warnings left in include/asm-arm/arch-s3c2410/debug-macro.S
whilst these where being experimented with.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add S3C2412_CLKDIVN_DVSEN and S3C2412_CLKDIVN_HALFHCLK definitions to
the S3C2412_CLKDIVN set.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add control constants for the S3C2412 SPI unit FIFO.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add definitions to allow easier decomposotion of the contents of
the S3C2410_BANKON registers
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add the call s3c2410_gpio_getpull() to return the
current state of the pin's pull-up.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Ensure FIQ_START is defined to allow anyone to use FIQ code on
an S3C24XX based CPU.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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If an DMA channel was active at suspend, then ensure that
it is correctly reconfigured when the system resumes.
Note, the previous policy was for each driver to handle their
own reconfiguration on resume. The policy has been changed to
make the individual driver's job easier.
Signed-off-by: Ben Dooks <ben-linux@flfuf.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The current S3C24XX DMA code does not allow for an peripheral
that has one channel for RX and another for TX.
This patch adds a per-cpu dma operation to select the transmit
or receive channel, and adds support to the S3C2412 for the
seperate DMA channels for TX and RX.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add s3c2412_gpio_set_sleepcfg() to allow the setting of the sleep
configuration of the GPIO blocks.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch fixes compilation error if only a machine with
s3c2442 cpu is selected but without s3c2440 cpu selected.
Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Ensure that if the RTC IRQ is not selected for wake in the
base configuration, then the PWRCFG has the same value set
in it.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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S3C2412_GPESLPCON does not exist in the register
mappings, so remove it.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The S3C2412 IIS engine differs from the previous
SoC in the range, so add a set of register definitions
in a seperate file for it.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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If the watchdog reset fails and we decided to take the jump
to zero approach, allow 50ms for the UARTS to drain the FIFOs
before calling into a bootloader that may flush the output.
Also reduece the waits and the timeout values as 5 seconds is
rather long.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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If the hard reset routine is using the watchdog, then
ensure that the clock for the watchdog has been enabled
before we try and issue a reset.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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behaviour.
Add the S3C2412_PWRCFG values for the action taken on detecting that
the battery is flat.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add S3C2412 register definitions.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Signed-off-by: Brian Swetland <swetland@google.com>
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- core header files for arch-msm
- Kconfig and Makefiles to enable ARCH_MSM7X00A builds
- MSM7X00A specific arch_idle
- peripheral iomap and irq number definitions
Signed-off-by: Brian Swetland <swetland@google.com>
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Don't lose __iomem in casts. Use __force to cast __iomem addresses to
integers. Use __force to cast u32 to __le32 and vice versa.
Signed-off-by: Pavel Roskin <proski@gnu.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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include/asm-arm/arch-at91/at91_lcdc.h (which is still present in latest
git) has been superseeded by include/video/atmel_lcdc.h, so let's remove
it.
Signed-off-by: Jan Altenberg <jan.altenberg@linutronix.de>
Cc: Andrew Victor <andrew@sanpeople.com>
Cc: Nicolas Ferre <nicolas.ferre@rfo.atmel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch adds a debug interface (if CONFIG_DEBUG_FS is selected) to
display the basic configuration and current state of the GPIO pins on
the Kendin/Micrel KS8695 processor.
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The kprobes code is already able to cope with reentrant probes, so its
handler must be called outside of the region protected by undef_lock.
If ever this lock is released when handlers are called then this commit
could be reverted.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Nicolas Pitre <nico@marvell.com>
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This is a full implementation of Kprobes including Jprobes and
Kretprobes support.
This ARM implementation does not follow the usual kprobes double-
exception model. The traditional model is where the initial kprobes
breakpoint calls kprobe_handler(), which returns from exception to
execute the instruction in its original context, then immediately
re-enters after a second breakpoint (or single-stepping exception)
into post_kprobe_handler(), each time the probe is hit.. The ARM
implementation only executes one kprobes exception per hit, so no
post_kprobe_handler() phase. All side-effects from the kprobe'd
instruction are resolved before returning from the initial exception.
As a result, all instructions are _always_ effectively boosted
regardless of the type of instruction, and even regardless of whether
or not there is a post-handler for the probe.
Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: Quentin Barnes <qbarnes@gmail.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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This is the code implementing instruction single-stepping for kprobes
on ARM.
To get around the limitation of no Next-PC and no hardware single-
stepping, all kprobe'd instructions are split into three camps:
simulation, emulation, and rejected. "Simulated" instructions are
those instructions which behavior is reproduced by straight C code.
"Emulated" instructions are ones that are copied, slightly altered
and executed directly in the instruction slot to reproduce their
behavior. "Rejected" instructions are ones that could be simulated,
but work hasn't been put into simulating them. These instructions
should be very rare, if not unencountered, in the kernel. If ever
needed, code could be added to simulate them.
One might wonder why this and the ptrace singlestep facility are not
sharing some code. Both approaches are fundamentally different because
the ptrace code regains control after the stepped instruction by installing
a breakpoint after the instruction itself, and possibly at the location
where the instruction might be branching to, instead of simulating or
emulating the target instruction.
The ptrace approach isn't suitable for kprobes because the breakpoints
would have to be moved back, and the icache flushed, everytime the
probe is hit to let normal code execution resume, which would have a
significant performance impact. It is also racy on SMP since another
CPU could, with the right timing, sail through the probe point without
being caught. Because ptrace single-stepping always result in a
different process to be scheduled, the concern for performance is much
less significant.
On the other hand, the kprobes approach isn't (currently) suitable for
ptrace because it has no provision for proper user space memory
protection and translation, and even if that was implemented, the gain
wouldn't be worth the added complexity in the ptrace path compared to
the current approach.
So, until kprobes does support user space, both kprobes and ptrace are
best kept independent and separate.
Signed-off-by: Quentin Barnes <qbarnes@gmail.com>
Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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With the new GPIO methods in place the old gpio_line_* methods are redundant,
so this patch finally removes the old legacy gpio_line_* wrappers.
Signed-off-by: Herbert Valerio Riedel <hvr@gnu.org>
Acked-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch renumbers the (virtual) GPIO line numbering to have all
irq-capable gpio lines <= EP93XX_GPIO_LINE_MAX_IRQ by swapping the
port f range with the port c range; This simplifies code such as
#define IRQ_EP93XX_GPIO(x) (64 + (((x) + (((x) >> 2) & 8)) & 0x1f))
or
if (line >= 0 && line < 16) {
/* Port A/B */
} else if (line >= 40 && line < 48) {
/* Port F */
}
considerably; in addition to the renumbering this patch also
introduces macro constants EP93XX_GPIO_LINE_MAX_IRQ and
EP93XX_GPIO_LINE_MAX, and replaces most magic numbers by those and
invocations of gpio_to_irq()/irq_to_gpio().
Signed-off-by: Herbert Valerio Riedel <hvr@gnu.org>
Acked-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Implement new GPIO API for ep93xx platform as defined in Documentation/gpio.txt
and provide transitional __deprecated wrappers for the previous gpio_line_*
functions.
Signed-off-by: Herbert Valerio Riedel <hvr@gnu.org>
Acked-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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