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* [ARM] 4130/1: Add L220 support to RealView/EBCatalin Marinas2007-02-15
| | | | | | | This patch enables the L220 on the RealView/EB MPCore platform. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge Realview GIC codeRussell King2007-02-15
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| * [ARM] 4109/2: Add support for the RealView/EB MPCore revC platformCatalin Marinas2007-02-15
| | | | | | | | | | | | | | | | | | | | | | The kernel originally supported revB only. This patch enables revC by default and adds a config option for building the kernel for the revB platform. Since the SCU base address was hard-coded in the proc-v6.S file (and only valid for RealView/EB revB), this patch also adds a more generic support for defining the SCU information. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] 4190/2: Add the secondary GIC support for the RealView/EBCatalin Marinas2007-02-15
| | | | | | | | | | | | | | | | | | | | MPCore platform This patch adds the registration of the secondary GIC on the baseboard, together with the IRQ chaining setup. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] 4108/2: Allow multiple GIC interrupt controllers in a systemCatalin Marinas2007-02-15
| | | | | | | | | | | | | | | | | | The current implementation only assumes one GIC to be present in the system. However, there are platforms with more than one cascaded interrupt controllers (RealView/EB MPCore for example). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 4135/1: Add support for the L210/L220 cache controllersCatalin Marinas2007-02-11
| | | | | | | | | | | | | | | | | | This patch adds the support for the L210/L220 (outer) cache controller. The cache range operations are done by index/way since L2 cache controller only accepts physical addresses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] Convert DMA cache handling to take const void * argsRussell King2007-02-08
| | | | | | | | | | | | | | | | | | The DMA cache handling functions take virtual addresses, but in the form of unsigned long arguments. This leads to a little confusion about what exactly they take. So, convert them to take const void * instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 4134/1: Add generic support for outer cachesCatalin Marinas2007-02-08
| | | | | | | | | | | | | | | | | | The outer cache can be L2 as on RealView/EB MPCore platform or even L3 or further on ARMv7 cores. This patch adds the generic support for flushing the outer cache in the DMA operations. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 4133/1: Add ISB after changes to CP15 registersCatalin Marinas2007-02-08
| | | | | | | | | | | | | | | | | | | | | | According to ARM ARM, changes to the CP15 registers are only guaranteed to be visible after an Instruction Synchronization Barrier (ISB). This patch adds the ISB at the end of set_cr and set_copro_access functions and also moves them further down in the file, below the isb macro definition. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 4129/1: Add barriers after the TLB operationsCatalin Marinas2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | The architecture specification states that TLB operations are guaranteed to be complete only after the execution of a DSB (Data Synchronisation Barrier, former Data Write Barrier or Drain Write Buffer). The branch target cache invalidation is also needed. The ISB (Instruction Synchronisation Barrier, formerly Prefetch Flush) is needed unless there will be a return from exception before the corresponding mapping is used (i.e. user mappings). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 4127/1: Flush the prefetch buffer after changing the DACRCatalin Marinas2007-02-08
| | | | | | | | | | | | | | | | The ARM Architecture Reference Manual specifies that a prefetch flush is needed after changing the DACR register (chapter B2.7.6). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 4126/1: Add the ARM specific barriersCatalin Marinas2007-02-08
|/ | | | | | | | There are three barriers - ISB, DMB and DSB for different scenarious. This patch adds their definitions in the system.h file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4033/1: Add separate Avila board setup codeMichael-Luke Jones2007-02-06
| | | | | | | | | | | | This patch adds support for the Gateworks Avila Network Platform in a separate set of setup files to the IXDP425. This is necessary now that a driver for the Avila CF card slot is available. It also adds support for a minor variant on the Avila board known as the Loft, which has a different number of maximum PCI devices. Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Improve csum_fold, cleanup csum_tcpudp_magic()Russell King2007-02-06
| | | | | | | | | | | | | | | csum_fold doesn't need two assembly instructions to perform its task, it can simply add the high and low parts together by rotating by 16 bits, and the carry into the upper-16 bits will automatically happen. Also, since csum_tcpudp_magic() is just csum_tcpudp_nofold + csum_fold, use those two functions to achieve this. Also note that there is a csum_fold() at the end of ip_fast_csum() as well, so use the real csum_fold() there as well. Boot tested on Versatile. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] oprofile: add ARM11 SMP supportRussell King2007-02-06
| | | | | | | Add the glue for ARM11 SMP oprofile support, which also supports the performance monitor in the coherency unit. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4111/1: Allow VFP to work with thread migration on SMPCatalin Marinas2007-01-25
| | | | | | | | | | The current lazy saving of the VFP registers is no longer possible with thread migration on SMP. This patch implements a per-CPU vfp-state pointer and the saving of the VFP registers at every context switch. The registers restoring is still performed in a lazy way. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4106/1: S3C2410: typo fixes in register definitionsMatt Reimer2007-01-24
| | | | | | | | The Trcd* bits of the S3C24xx BANKCON6 and BANKCON7 registers are misspelled in include/asm-arm/arch-s3c2410/regs-mem.h as Trdc*. Signed-off-by: Matt Reimer <mreimer@vpop.net> Acked-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4095/1: S3C24XX: Fix GPIO set for Bank ABen Dooks2007-01-24
| | | | | | | | | | | | | GPIO bank A can only be output or a special function, and the regs-gpio.h header has mistakenly got this as input or output. The mistake is carried on into the gpio.c s3c2410_gpio_cfgpin() call which will set the wrong value if S3C2410_GPIO_OUTPUT is passed. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4086/1: AT91: Whitespace cleanupAndrew Victor2007-01-24
| | | | | | | A couple of whitespace cleanups, mainly in the AT91 header files. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4085/1: AT91: Header fixes.Andrew Victor2007-01-24
| | | | | | | | | | | Fix two typo's where AT01_* was used instead of AT91_*. [Patch from Wojtek Kaniewski] Fix definition of AT91_SMC_EXNWMODE for the SAM9 processors. [Patch from Wu Xuan] Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Resolve fuse and direct-IO failures due to missing cache flushesRussell King2007-01-08
| | | | | | | | | | | | | | | fuse does not work on ARM due to cache incoherency issues - fuse wants to use get_user_pages() to copy data from the current process into kernel space. However, since this accesses userspace via the kernel mapping, the kernel mapping can be out of date wrt data written to userspace. This can lead to unpredictable behaviour (in the case of fuse) or data corruption for direct-IO. This resolves debian bug #402876 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4082/1: iop3xx: fix iop33x gpio register offsetDan Williams2007-01-06
| | | | | | | | iop33x gpio offset is correct in include/asm-arm/arch-iop33x/iop33x.h, but include/asm-arm/hardware/iop3xx.h adds 4. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4081/1: Add definition for TI Sync Serial ProtocolPhilipp Zabel2007-01-02
| | | | | | | | Of the possible SSP frame formats (FRF bits in SSCR0), only SSCR0_PSP is defined. Other possible formats are Motorola SPI (0<<4), TI SSP (1<<4) and Microwire (2<<4). Attached patch adds a definition SSCR0_TISSP. This mode is used for the sound codec attached to the PXA272 SSP1 of some HTC PDA phones. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4080/1: Fix for the SSCR0_SlotsPerFrm macroPhilipp Zabel2007-01-02
| | | | | | | The SSCR0_SlotsPerFrm macro writes a 3-bit value to bits [2:0], while the correct location of FRDC in SSCR0 is at bits [26:24]. This patch adds the missing "<< 24". Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4078/1: Fix ARM copypage cache coherency problemsRichard Purdie2006-12-30
| | | | | | | | | | | | | If PG_dcache_dirty is set for a page, we need to flush the source page before performing any copypage operation using a different virtual address. This fixes the copypage implementations for XScale, StrongARM and ARMv6. This patch fixes segmentation faults seen in the dynamic linker under the usage patterns in glibc 2.4/2.5. Signed-off-by: Richard Purdie <rpurdie@rpsys.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4077/1: iop13xx: fix __io() macroDan Williams2006-12-30
| | | | | | | | | | Since iop13xx defines the PCI I/O spaces with physical resource addresses the __io macro needs to perform the physical to virtual conversion. I incorrectly assumed that this would be handled by ioremap, but drivers (like e1000) directly dereference the address returned from __io. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4074/1: Flat loader stack alignmentPaul Brook2006-12-30
| | | | | | | | | | | | The ARM EABI requires doubleword (8-byte) stack alignment at all public entry points. The patch below makes the bFLT loader honour this. It's always safe to start with a doubleword aligned stack so it doesn't seem worth making this conditional on CONFIG_AEABI. Paul Signed-off-by: Paul Brook <paul@codesourcery.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4073/1: Prevent s3c24xx drivers from including asm/arch/hardware.h and ↵Arnaud Patard2006-12-30
| | | | | | | | | | | | | | | | | asm/arch/irqs.h As reminded in http://lkml.org/lkml/2006/12/23/26, one should use asm/hardware.h and asm/irq.h but absent-minded devs like me tends to use asm/arch/hardware.h and/or asm/arch/irqs.h. This patch aims at preventing such things. In order to make it work, I had to modify asm-arm/irq.h too so that it can be included from assembly files. Also, as a side effect, I had to modify some headers who were using the asm/arch/hardware.h or asm/arch/irqs.h. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4063/1: ep93xx: fix IRQ_EP93XX_GPIO?MUX numberingLennert Buytenhek2006-12-30
| | | | | | | | Fix incorrect IRQ numbering in arch-ep93xx/irqs.h (source: Applied Data Systems 2.6.17 kernel tree.) Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4057/1: ixp23xx: unconditionally enable hardware coherencyLennert Buytenhek2006-12-17
| | | | | | | | | | | | | On ixp23xx, it was thought to be necessary to disable coherency to work around certain silicon errata. This turns out not to be the case -- none of the documented errata workarounds require disabling coherency, and disabling coherency does not work around any existing errata. Furthermore, all ixp23xx models do support coherency, so we should just unconditionally enable coherency for all ixp23xx. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4055/1: iop13xx: fix phys_io/io_pg_offst for iq81340mc/scLennert Buytenhek2006-12-17
| | | | | | | | The phys_io/io_pg_offst machine record variables were being set to bogus values, causing problems when enabling DEBUG_LL. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4054/1: ep93xx: add HWCAP_CRUNCHLennert Buytenhek2006-12-17
| | | | | | | | Add HWCAP_CRUNCH so that the dynamic linker knows whether it can use Crunch-optimised libraries or not. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix warnings from asm/system.hRussell King2006-12-17
| | | | | | | Move adjust_cr() into arch/arm/mm/mmu.c, and move irqflags.h to a more appropriate place in the header file. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4049/1: S3C24XX: fix sparse warning due to upf_t in regs-serial.hBen Dooks2006-12-17
| | | | | | | | | | | | | | | | | Change the include/asm-arm/arch-s3c2410/regs-serial.h platform data to use the prorper type (upf_t) for the uart_flags. Fix all the other parts of arch/arm/mach-s3c2410 to include <linux/serial_core.h> and all other uses of the include file. mach-rx3715.c:101:18: warning: incorrect type in initializer (different base types) mach-rx3715.c:101:18: expected unsigned long [unsigned] uart_flags mach-rx3715.c:101:18: got restricted unsigned int [usertype] [force] <noident> Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4045/1: S3C24XX: remove old VA for non-shared areasBen Dooks2006-12-17
| | | | | | | | | Remove old (and non-shared) VA addresses from the mappings in arch/arm/mach-s3c2410/map.h and anywhere they are being mapped in arch/arm/mach-s3c2410 Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4042/1: H1940: Fix sparse errors from VA addressesBen Dooks2006-12-17
| | | | | | | | | | Fix address-space conversion errors from passing addresses generated from include/asm-arm/arch-s3c2410/map.h by adding an __force argument to the `void __iomem *` for all the virtual addresses. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4041/1: S3C24XX: Fix sparse errors from VA addressesBen Dooks2006-12-17
| | | | | | | | | | Fix address-space conversion errors from passing addresses generated from include/asm-arm/arch-s3c2410/map.h by adding an __force argument to the `void __iomem *` for all the virtual addresses. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4039/1: S3C24XX: Fix copyrights in include/asm-arm/arch-s3c2410 (mach)Ben Dooks2006-12-17
| | | | | | | | | Fix copyright notices in include/asm-arm/arch-s3c2410 to actually have `Copyright` in the line. This patch deals with all the core files. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4038/1: S3C24XX: Fix copyrights in include/asm-arm/arch-s3c2410 (core)Ben Dooks2006-12-17
| | | | | | | | | Fix copyright notices in include/asm-arm/arch-s3c2410 to actually have `Copyright` in the line. This patch deals with all the core files. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Add more syscallsRussell King2006-12-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add: sys_unshare sys_set_robust_list sys_get_robust_list sys_splice sys_arm_sync_file_range sys_tee sys_vmsplice sys_move_pages sys_getcpu Special note about sys_arm_sync_file_range(), which is implemented as: asmlinkage long sys_arm_sync_file_range(int fd, unsigned int flags, loff_t offset, loff_t nbytes) { return sys_sync_file_range(fd, offset, nbytes, flags); } We can't export sys_sync_file_range() directly on ARM because the argument list someone picked does not fit in the available registers. Would be nice if... there was an arch maintainer review mechanism for new syscalls before they hit the kernel. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2006-12-13
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 4017/1: [Jornada7xx] - Updating Jornada720.c [ARM] 3992/1: i.MX/MX1 CPU Frequency scaling support [ARM] Provide a method to alter the control register [ARM] 4016/1: prefetch macro is wrong wrt gcc's "delete-null-pointer-checks" [ARM] Remove empty fixup function [ARM] 4014/1: include drivers/hid/Kconfig [ARM] 4013/1: clocksource driver for netx [ARM] 4012/1: Clocksource for pxa [ARM] Clean up ioremap code [ARM] Unuse another Linux PTE bit [ARM] Clean up KERNEL_RAM_ADDR [ARM] Add sys_*at syscalls [ARM] 4004/1: S3C24XX: UDC remove implict addition of VA to regs [ARM] Formalise the ARMv6 processor name string [ARM] Handle HWCAP_VFP in VFP support code [ARM] 4011/1: AT91SAM9260: Fix compilation with NAND driver [ARM] 4010/1: AT91SAM9260-EK board: Prepare for MACB Ethernet support
| *-. [ARM] Merge AT91 and devel branchesRussell King2006-12-13
| |\ \ | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3992/1: i.MX/MX1 CPU Frequency scaling supportPavel Pisa2006-12-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support to change MX1 CPU frequency at runtime. Tested on PiKRON's PiMX1 board and seems to be fully stable up to 200 MHz end even as low as 8 MHz. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Provide a method to alter the control registerRussell King2006-12-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX needs to tweak the control register to support CPU frequency scaling. Rather than have folk blindly try and change the control register by writing to it and then wondering why it doesn't work, provide a method (which is safe for UP only, and therefore only available for UP) to achieve this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 4016/1: prefetch macro is wrong wrt gcc's "delete-null-pointer-checks"Nicolas Pitre2006-12-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | optimization The gcc manual says: |`-fdelete-null-pointer-checks' | Use global dataflow analysis to identify and eliminate useless | checks for null pointers. The compiler assumes that dereferencing | a null pointer would have halted the program. If a pointer is | checked after it has already been dereferenced, it cannot be null. | Enabled at levels `-O2', `-O3', `-Os'. Now the problem can be seen with this test case: #include <linux/prefetch.h> extern void bar(char *x); void foo(char *x) { prefetch(x); if (x) bar(x); } Because the constraint to the inline asm used in the prefetch() macro is a memory operand, gcc assumes that the asm code does dereference the pointer and the delete-null-pointer-checks optimization kicks in. Inspection of generated assembly for the above example shows that bar() is indeed called unconditionally without any test on the value of x. Of course in the prefetch case there is no real dereference and it cannot be assumed that a null pointer would have been caught at that point. This causes kernel oopses with constructs like hlist_for_each_entry() where the list's 'next' content is prefetched before the pointer is tested against NULL, and only when gcc feels like applying this optimization which doesn't happen all the time with more complex code. It appears that the way to prevent delete-null-pointer-checks optimization to occur in this case is to make prefetch() into a static inline function instead of a macro. At least this is what is done on x86_64 where a similar inline asm memory operand is used (I presume they would have seen the same problem if it didn't work) and resulting code for the above example confirms that. An alternative would consist of replacing the memory operand by a register operand containing the pointer, and use the addressing mode explicitly in the asm template. But that would be less optimal than an offsettable memory reference. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Unuse another Linux PTE bitRussell King2006-12-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | L_PTE_ASID is not really required to be stored in every PTE, since we can identify it via the address passed to set_pte_at(). So, create set_pte_ext() which takes the address of the PTE to set, the Linux PTE value, and the additional CPU PTE bits which aren't encoded in the Linux PTE value. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Add sys_*at syscallsRussell King2006-12-09
| | | | | | | | | | | | | | | | | | | | | | | | Later glibc requires the *at syscalls. Add them. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 4004/1: S3C24XX: UDC remove implict addition of VA to regsBen Dooks2006-12-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the implicit addition of a virtual address to the UDC registers. This should have been done by ioremap() in the driver, not by a static map. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Handle HWCAP_VFP in VFP support codeRussell King2006-12-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't set HWCAP_VFP in the processor support file; not only does it depend on the processor features, but it also depends on the support code being present. Therefore, only set it if the support code detects that we have a VFP coprocessor attached. Also, move the VFP handling of the coprocessor access register into the VFP support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | [PATCH] Optimize D-cache alias handling on forkRalf Baechle2006-12-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Virtually index, physically tagged cache architectures can get away without cache flushing when forking. This patch adds a new cache flushing function flush_cache_dup_mm(struct mm_struct *) which for the moment I've implemented to do the same thing on all architectures except on MIPS where it's a no-op. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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