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* page table handling cleanupJan Beulich2007-07-16
| | | | | | | | | | | | Kill pte_rdprotect(), pte_exprotect(), pte_mkread(), pte_mkexec(), pte_read(), pte_exec(), and pte_user() except where arch-specific code is making use of them. Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: Andi Kleen <andi@firstfloor.org> Cc: Christoph Hellwig <hch@infradead.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'ioat-md-accel-for-linus' of ↵Linus Torvalds2007-07-13
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://lost.foo-projects.org/~dwillia2/git/iop * 'ioat-md-accel-for-linus' of git://lost.foo-projects.org/~dwillia2/git/iop: (28 commits) ioatdma: add the unisys "i/oat" pci vendor/device id ARM: Add drivers/dma to arch/arm/Kconfig iop3xx: surface the iop3xx DMA and AAU units to the iop-adma driver iop13xx: surface the iop13xx adma units to the iop-adma driver dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines md: remove raid5 compute_block and compute_parity5 md: handle_stripe5 - request io processing in raid5_run_ops md: handle_stripe5 - add request/completion logic for async expand ops md: handle_stripe5 - add request/completion logic for async read ops md: handle_stripe5 - add request/completion logic for async check ops md: handle_stripe5 - add request/completion logic for async compute ops md: handle_stripe5 - add request/completion logic for async write ops md: common infrastructure for running operations with raid5_run_ops md: raid5_run_ops - run stripe operations outside sh->lock raid5: replace custom debug PRINTKs with standard pr_debug raid5: refactor handle_stripe5 and handle_stripe6 (v3) async_tx: add the async_tx api xor: make 'xor_blocks' a library routine for use with async_tx dmaengine: make clients responsible for managing channels dmaengine: refactor dmaengine around dma_async_tx_descriptor ...
| * iop3xx: surface the iop3xx DMA and AAU units to the iop-adma driverDan Williams2007-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the platform device definitions and the architecture specific support routines (i.e. register initialization and descriptor formats) for the iop-adma driver. Changelog: * add support for > 1k zero sum buffer sizes * added dma/aau platform devices to iq80321 and iq80332 setup * fixed the calculation in iop_desc_is_aligned * support xor buffer sizes larger than 16MB * fix places where software descriptors are assumed to be contiguous, only hardware descriptors are contiguous for up to a PAGE_SIZE buffer size * convert to async_tx * add interrupt support * add platform devices for 80219 boards * do not call platform register macros in driver code * remove switch() statements for compatible register offsets/layouts * change over to bitmap based capabilities * remove unnecessary ARM assembly statement * checkpatch.pl fixes * gpl v2 only correction * phys move to dma_async_tx_descriptor Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * iop13xx: surface the iop13xx adma units to the iop-adma driverDan Williams2007-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the platform device definitions and the architecture specific support routines (i.e. register initialization and descriptor formats) for the iop-adma driver. Changelog: * added 'descriptor pool size' to the platform data * add base support for buffer sizes larger than 16MB (hw max) * build error fix from Kirill A. Shutemov * rebase for async_tx changes * add interrupt support * do not call platform register macros in driver code * remove unnecessary ARM assembly statement * checkpatch.pl fixes * gpl v2 only correction Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dmaengine: driver for the iop32x, iop33x, and iop13xx raid enginesDan Williams2007-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel(R) IOP series of i/o processors integrate an Xscale core with raid acceleration engines. The capabilities per platform are: iop219: (2) copy engines iop321: (2) copy engines (1) xor and block fill engine iop33x: (2) copy and crc32c engines (1) xor, xor zero sum, pq, pq zero sum, and block fill engine iop34x (iop13xx): (2) copy, crc32c, xor, xor zero sum, and block fill engines (1) copy, crc32c, xor, xor zero sum, pq, pq zero sum, and block fill engine The driver supports the features of the async_tx api: * asynchronous notification of operation completion * implicit (interupt triggered) handling of inter-channel transaction dependencies The driver adapts to the platform it is running by two methods. 1/ #include <asm/arch/adma.h> which defines the hardware specific iop_chan_* and iop_desc_* routines as a series of static inline functions 2/ The private platform data attached to the platform_device defines the capabilities of the channels 20070626: Callbacks are run in a tasklet. Given the recent discussion on LKML about killing tasklets in favor of workqueues I did a quick conversion of the driver. Raid5 resync performance dropped from 50MB/s to 30MB/s, so the tasklet implementation remains until a generic softirq interface is available. Changelog: * fixed a slot allocation bug in do_iop13xx_adma_xor that caused too few slots to be requested eventually leading to data corruption * enabled the slot allocation routine to attempt to free slots before returning -ENOMEM * switched the cleanup routine to solely use the software chain and the status register to determine if a descriptor is complete. This is necessary to support other IOP engines that do not have status writeback capability * make the driver iop generic * modified the allocation routines to understand allocating a group of slots for a single operation * added a null xor initialization operation for the xor only channel on iop3xx * support xor operations on buffers larger than the hardware maximum * split the do_* routines into separate prep, src/dest set, submit stages * added async_tx support (dependent operations initiation at cleanup time) * simplified group handling * added interrupt support (callbacks via tasklets) * brought the pending depth inline with ioat (i.e. 4 descriptors) * drop dma mapping methods, suggested by Chris Leech * don't use inline in C files, Adrian Bunk * remove static tasklet declarations * make iop_adma_alloc_slots easier to read and remove chances for a corrupted descriptor chain * fix locking bug in iop_adma_alloc_chan_resources, Benjamin Herrenschmidt * convert capabilities over to dma_cap_mask_t * fixup sparse warnings * add descriptor flush before iop_chan_enable * checkpatch.pl fixes * gpl v2 only correction * move set_src, set_dest, submit to async_tx methods * move group_list and phys to async_tx Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | USB: pxa2xx_udc: use generic gpio layerMilan Svoboda2007-07-12
| | | | | | | | | | | | | | | | | | | | This patch lets the pxa2xx_udc use the generic gpio layer, on the relevant PXA and IXP systems. Signed-off-by: Milan Svoboda <msvoboda@ra.rockwell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2007-07-12
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (50 commits) [ARM] sa1100: remove boot time RTC initialisation [ARM] sa1100: stop doing our own rtc management over suspend [ARM] 4474/1: Do not check the PSR_F_BIT in valid_user_regs [ARM] 4473/2: Take the HWCAP definitions out of the elf.h file [ARM] pxa: move platform devices to separate header file [ARM] pxa: move device registration into CPU-specific file [ARM] pxa: remove boot time RTC initialisation [ARM] pxa: stop doing our own rtc management over suspend [ARM] 4451/1: pxa: make dma.c generic and remove cpu specific dma code [ARM] 4450/1: pxa: add pxa25x_init_irq() and pxa27x_init_irq() [ARM] 4440/1: PXA: enable the checking of ICIP2 for IRQs [ARM] 4438/1: PXA: remove #ifdef .. #endif from pxa_gpio_demux_handler() [ARM] 4437/1: PXA: move the GPIO IRQ initialization code to pxa_init_irq_gpio() [ARM] 4436/1: PXA: move low IRQ initialization code to pxa_init_irq_low() [ARM] 4435/1: PXA: remove PXA_INTERNAL_IRQS [ARM] 4434/1: PXA: remove PXA_IRQ_SKIP [ARM] pxa: Fix PXA27x suspend type validation, remove pxa_pm_prepare() [ARM] pxa: move pm_ops structure into CPU specific files [ARM] pxa: introduce cpu_is_pxaXXX macros [ARM] pxa: remove MMC register defines from pxa-regs.h ...
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| *-----------. \ Merge branches 'at91', 'davinci', 'imx', 'iop', 'ixp', 'ks8695', 'misc', ↵Russell King2007-07-12
| |\ \ \ \ \ \ \ \ | | | | | |_|_|_|/ | | | | |/| | | | | | | | | | | | | 'pxa' and 's3c' into devel
| | | | | | | | * [ARM] 4451/1: pxa: make dma.c generic and remove cpu specific dma codeEric Miao2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the number of dma channels varies between pxa25x and pxa27x, it introduces some specific code in dma.c. This patch moves the specific code to pxa25x.c and pxa27x.c and makes dma.c more generic. 1. add pxa_init_dma() for dma initialization, the number of channels are passed in by the argument 2. add a "prio" field to the "struct pxa_dma_channel" for the channel priority, and is initialized in pxa_init_dma() 3. use a general priority comparison with the channels "prio" field so to remove the processor specific pxa_for_each_dma_prio macro, this is not lightning fast as the original one, but it is acceptable as it happens when requesting dma, which is usually not so performance critical Signed-off-by: eric miao <eric.miao@marvell.com> Acked-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * [ARM] 4440/1: PXA: enable the checking of ICIP2 for IRQsEric Miao2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ICIP2 is not examined during IRQ entrance, this patch add the checking if the processor is PXA27x or later, with CoreG bits in CPUID (Core Generation) > 1 Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * [ARM] 4435/1: PXA: remove PXA_INTERNAL_IRQSEric Miao2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. define PXA_GPIO_IRQ_BASE to be right after the internal IRQs, and define PXA_GPIO_IRQ_NUM to be 128 for all PXA2xx variants 2. make the code specific to the high IRQ numbers (32..64) to be PXA27x specific 3. add a function pxa_init_irq_high() to initialize the internal high IRQ chip, the invoke of this function could be moved to PXA27x specific initialization code Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * [ARM] 4434/1: PXA: remove PXA_IRQ_SKIPEric Miao2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. PXA_IRQ_SKIP is defined to be 7 on PXA25x so that the first IRQ starts from zero. This makes IRQ numbering inconsistent between PXA25x and PXA27x. Remove this macro so that the same IRQ_XXXXX definition has the same value on both PXA25x and PXA27x. 2. make IRQ_SSP3..IRQ_PWRI2C valid only if PXA27x is defined, this avoids unintentional use of these macros on PXA25x Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * [ARM] pxa: introduce cpu_is_pxaXXX macrosRussell King2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * [ARM] pxa: remove MMC register defines from pxa-regs.hRussell King2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pxamci.h redefines the MMC registers differently so they can be used with ioremap. Remove the incompatible definitions from pxa-regs.h. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * [ARM] pxa: remove useless pxa_pm_finish() functionRussell King2007-07-12
| | | | | |_|_|/ | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pxa_pm_finish() does nothing but return zero. The core code does nothing with this return value, and will not try to call the finish method in the pm_ops structure if it is NULL. Therefore, we can remove this useless function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | * [ARM] 4474/1: Do not check the PSR_F_BIT in valid_user_regsCatalin Marinas2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running Linux in non-secure mode (on ARM1176 for example), depending on the CP15 secure configuration register, the CPSR.F bit (6) might only be modified from the secure mode. However, the valid_user_regs() function checks for this bit being cleared. With commit a6c61e9d, a SIGSEGV is forced in handle_signal() if the user registers are not considered valid. The patch also ensures that the CPSR.A bit is cleared and the USR mode is set if the CPU does not support the 26bit user mode. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | * [ARM] 4473/2: Take the HWCAP definitions out of the elf.h fileCatalin Marinas2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch moves the HWCAP definitions and the extern elf_hwcap declaration to the hwcap.h header file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | * [ARM] 4453/1: Fully Decode ARM instruction set state in show_regs() tombstoneGeorge G. Davis2007-07-12
| | | | | |_|/ | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM show_regs() tombstone only partially decodes which ARM ISA was executing at the time a fault occurred displaying either "(T)" for the Thumb case or nothing at all for other cases. This patch therefore explicitly identifies which state the processor is in at the time of a fault: ARM, Thumb, Jazelle or JazelleEE. Signed-off-by: George G. Davis <gdavis@mvista.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * [ARM] 4377/1: KS8695: GPIO driverAndrew Victor2007-07-12
| | | | | |/ | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver to control the GPIO pins on the KS8695 processor. The driver natively supports the Generic GPIO interface. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * [ARM] 4426/2: Netgear WG302 v2 and WAG302 v2 supportImre Kaloz2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support for the Netgear WG302 v2 and WAG302 v2 AccessPoint series. This patch relies on the patch "Gateway 7001 series support" minimally, as they only have UART2 connected. Updated to stay below the 80 char limit in uncompress.h Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Signed-off-by: Deepak Saxena <dsaxena@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * [ARM] 4425/2: Gateway 7001 series supportImre Kaloz2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support for the Gateway 7001 AccessPoint series. Updated to stay below the 80 char limit in uncompress.h Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Signed-off-by: Deepak Saxena <dsaxena@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * [ARM] 4385/2: ixdp425: NAND supportVladimir Barinov2007-07-12
| | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IXDP425 NAND support (arch specific part). The generic platform driver that is used by ixdp425 platfrom is already in upstream kernel in 2.6.22-rc1. Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Signed-off-by: Ruslan Sushko <rsushko@ru.mvista.com> Signed-off-by: Deepak Saxena <dsaxena@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * / [ARM] 4373/1: i.MX/MX1 GPIO support implementationPavel Pisa2007-07-12
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for generic input output for MX1 family. The implementation prevents allocation of one pin by two users, but does not store pointer to the user description permanently, because this solution would have bigger memory overhead. The simple way to integrate code with per BSP pins setup and allocation is required else all GPIO registration checking is useless. The function imx_gpio_setup_multiple_pins() can be used for this purpose in future. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | [ARM] 4432/5: davinci: pin mux supportVladimir Barinov2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support pin multiplexing configurations driver for TI DaVinci SoC Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Acked-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | [ARM] 4457/2: davinci: GPIO supportVladimir Barinov2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support GPIO driver for TI DaVinci SoC Signed-off-by: Vladimir Barinov <vbarino@ru.mvista.com> Acked-by: David Brownell <david-b@pacbell.net> Acked-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | [ARM] 4430/1: davinci: clock control supportVladimir Barinov2007-07-12
| | |/ | | | | | | | | | | | | | | | | | | | | | Support clock control driver for TI DaVinci SoC Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] 4428/1: modify at91 includes to handle non-MMU at91x40 familyGreg Ungerer2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the common at91 hardware support to deal with the non-MMU at91x40 family. The base RAM (which is most likely not DRAM) is set to the configured value. Virtual IO device mapping is set to be 1 to 1 with the physical addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] 4427/1: base Atmel at91x40 architecture definesGreg Ungerer2007-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Base at91x40 architecture support defines. These parts are somewhat simpler than the ARM9 Atmel based parts. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] 4391/1: make at91 debug unit support optionalGreg Ungerer2007-07-12
| |/ | | | | | | | | | | | | | | | | | | | | | | | | The AT91x40 family doesn't have the debug unit like its bigger brothers. But it does have the ID and extension registers (with the bit meanings the same). Reorganize at91_dbgu.h to cater for this. This also affects the load uncompressor, since it outputs to the debug port. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | PCI: remove pci_dac_dma_... APIsJan Beulich2007-07-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on replies to a respective query, remove the pci_dac_dma_...() APIs (except for pci_dac_dma_supported() on Alpha, where this function is used in non-DAC PCI DMA code). Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: Andi Kleen <ak@suse.de> Cc: Jesse Barnes <jesse.barnes@intel.com> Cc: Christoph Hellwig <hch@infradead.org> Acked-by: David Miller <davem@davemloft.net> Cc: Jeff Garzik <jeff@garzik.org> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | PCI: Use a weak symbol for the empty version of pcibios_add_platform_entries()Michael Ellerman2007-07-11
|/ | | | | | | | | | | | | | | I'm not sure if this is going to fly, weak symbols work on the compilers I'm using, but whether they work for all of the affected architectures I can't say. I've cc'ed as many arch maintainers/lists as I could find. But assuming they do, we can use a weak empty definition of pcibios_add_platform_entries() to avoid having an empty definition on every arch. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* Introduce fixed sys_sync_file_range2() syscall, implement on PowerPC and ARMDavid Woodhouse2007-06-28
| | | | | | | | | | | | | | | | | | | | | | | | | Not all the world is an i386. Many architectures need 64-bit arguments to be aligned in suitable pairs of registers, and the original sys_sync_file_range(int, loff_t, loff_t, int) was therefore wasting an argument register for padding after the first integer. Since we don't normally have more than 6 arguments for system calls, that left no room for the final argument on some architectures. Fix this by introducing sys_sync_file_range2(int, int, loff_t, loff_t) which all fits nicely. In fact, ARM already had that, but called it sys_arm_sync_file_range. Move it to fs/sync.c and rename it, then implement the needed compatibility routine. And stop the missing syscall check from bitching about the absence of sys_sync_file_range() if we've implemented sys_sync_file_range2() instead. Tested on PPC32 and with 32-bit and 64-bit userspace on PPC64. Signed-off-by: David Woodhouse <dwmw2@infradead.org> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Paul Mackerras <paulus@samba.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [ARM] Update show_regs/oops register formatRussell King2007-06-18
| | | | | | | | | | | | Add the kernel release and version information to the output of show_regs/oops. Add the CPU PSR register. Avoid using printk to output partial lines; always output a complete line. Re-combine the "Control" and "Table + DAC" lines after nommu separated them; we don't want to waste vertical screen space needlessly. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4445/1: ANUBIS: Fix CPLD registersBen Dooks2007-06-11
| | | | | | | | Update the ANUBIS register definitions inline with the specs and ensure they are registered correctly. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4444/2: OSIRIS: CPLD suspend fixBen Dooks2007-06-11
| | | | | | | | Ensure the CPLD 8bit settings are preserved over a suspend/resume cycle as the CPU sends a hard-reset at resume time. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4442/1: OSIRIS: Fix CPLD register definitionsBen Dooks2007-06-11
| | | | | | | | Fix the CPLD register definitions to correctly mirror the documentation Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] VFP: fix section mismatch errorRussell King2007-06-10
| | | | | | | | | | | | Fix a real section mismatch issue; the test code is thrown away after initialisation, but if we do not detect the VFP hardware, it is left hooked into the exception handler. Any VFP instructions which are subsequently executed risk calling the discarded exception handler. Introduce a new "null" handler which returns to the "unrecognised fault" return address. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4421/1: AT91: Value of _KEY fields.Andrew Victor2007-06-03
| | | | | | | | | | | Use the actual value (0xA5) for the AT91_SHDW_KEY and AT91_WDT_KEY register fields instead of a bitmask. This is consistent with how AT91_RSTC_KEY is defined, and is easier to use in code. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4422/1: Fix default value handling in gpio_direction_output (PXA)Bill Gatliff2007-06-02
| | | | | | | | | The default value passed through to pxa_gpio_mode() is lost due to a missing GPIO_DFLT_HIGH mask for nonzero values. The enclosed patch fixes this programming error. Signed-off-by: Bill Gatliff <bgat@billgatliff.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4394/1: ARMv7: Add the TLB range operationsCatalin Marinas2007-05-30
| | | | | | | | | We are currently using the ARMv6 operations but need to duplicate some of the code because of the introduction of the new CPU barrier instructions in ARMv7. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4412/1: S3C2412: reset errata fixBen Dooks2007-05-30
| | | | | | | | | | | | | The S3C2412 has an reset-errata where the clock may cause a glitch switching back to EXTCLK. We force a switch to EXTCLK before writing the reset register to force use of the CLKCON sync logic to properly switch. Fix problem reported by Matthieu Castet. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] use __used attributeDavid Rientjes2007-05-30
| | | | | | | | Use the newly introduced __used attribute in place of the deprecated __attribute_used__. Functionally the same. Signed-off-by: David Rientjes <rientjes@google.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] enable arbitary speed tty ioctls and split input/output speedAlan Cox2007-05-28
| | | | | | | | | | | | Add the ioctls and values needed for this to the ARM26/ARM32 ports. The actual code has been in the base kernel for a while and automatically turns on when a port sets the required defines. [RMK: also added termbits.h changes to avoid build breakage] Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4406/1: Trivial NSLU2 / NAS-100D header & setup code cleanupMichael-Luke Jones2007-05-26
| | | | | | | | | | This trivial patch updates the nslu2 and nas-100d headers to remove pointless GPIO defines, and updates nslu2-setup.c accordingly. In addition minor style cleanups to some comments are included. Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4405/1: NSLU2, DSM-G600 frequency fixup codeMichael-Luke Jones2007-05-26
| | | | | | | | | | This patch is required as the frequency fixup in nslu2_init does not run sufficiently early in the boot sequence to take effect. In addition the dsmg600 setup code behaviour has been improved such that a 'fixup' routine is avoided. Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4402/1: S3C2443: Add physical address of HSMMC controllerBen Dooks2007-05-26
| | | | | | | Add physical address of HSMMC to include/asm-arm/arch-s3c2410/map.h Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4401/1: S3C2443: Add definitions for port GPIOJBen Dooks2007-05-26
| | | | | | | Add definitions for S3C2443 functions in GPIOJ Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2007-05-21
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: (22 commits) [ARM] spelling fixes [ARM] at91_adc parenthesis balance [ARM] 4400/1: S3C24XX: Add high-speed MMC device definition [ARM] 4399/2: S3C2443: Fix SMDK2443 nand timings [ARM] 4398/1: S3C2443: Fix watchdog IRQ number [ARM] 4397/1: S3C2443: remove SDI0/1 IRQ ambiguity [ARM] 4396/1: S3C2443: Add missing HCLK clocks [ARM] 4395/1: S3C24XX: add include of <linux/sysdev.h> to relevant machines [ARM] 4388/1: no need for arm/mm mmap range checks for non-mmu [ARM] 4387/1: fix /proc/cpuinfo formatting for pre-ARM7 parts [ARM] ARMv6: add CPU_HAS_ASID configuration [ARM] integrator: fix pci_v3 compile error with DEBUG_LL [ARM] gic: Fix gic cascade irq handling [ARM] Silence OMAP kernel configuration warning [ARM] Update ARM syscalls [ARM] 4384/1: S3C2412/13 SPI registers offset correction [ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files [ARM] 4382/1: iop13xx: fix msi support [ARM] Remove Integrator/CP SMP platform support [ARM] 4378/1: KS8695: Serial driver fix ...
| * [ARM] at91_adc parenthesis balanceMariusz Kozlowski2007-05-20
| | | | | | | | | | | | | | Trivial unbalanced parenthesis macro fix. Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] 4400/1: S3C24XX: Add high-speed MMC device definitionBen Dooks2007-05-20
| | | | | | | | | | | | | | | | Add definition for high-speed MMC/SD device and add to SMDK2443 device list. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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