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* Add cmpxchg_local to armMathieu Desnoyers2008-02-07
| | | | | | | | | | Use the new generic cmpxchg_local (disables interrupt). Also use the generic cmpxchg as fallback if SMP is not set. Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [ARM] pxa: silence warnings from cpu_is_xxx() macrosRussell King2008-01-10
| | | | | | | | If only a single CPU type is selected, __cpu_is_xxx() doesn't use its argument. This causes the compiler to issue a warning about an unused variable in the parent function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] sched: sched_cacheflush is now unusedRalf Baechle2007-07-19
| | | | | | | | Since Ingo's recent scheduler rewrite which was merged as commit 0437e109e1841607f2988891eaa36c531c6aa6ac sched_cacheflush is unused. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2007-05-09
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (28 commits) ARM: OMAP: Fix GCC-reported compile time bug ARM: OMAP: restore CONFIG_GENERIC_TIME ARM: OMAP: partial LED fixes ARM: OMAP: add SoSSI clock (call propagate_rate for childrens) ARM: OMAP: FB sync with N800 tree (support for dynamic SRAM allocations) ARM: OMAP: Sync framebuffer headers with N800 tree ARM: OMAP: Mostly cosmetic to sync up with linux-omap tree ARM: OMAP: Fix gpmc header ARM: OMAP: Add mailbox support for IVA [ARM] armv7: add Makefile and Kconfig entries [ARM] armv7: add support for asid-tagged VIVT I-cache [ARM] armv7: add dedicated ARMv7 barrier instructions [ARM] armv7: Add ARMv7 cacheid macros [ARM] armv7: add support for ARMv7 cores. [ARM] Fix ARM branch relocation range [ARM] 4363/1: AT91: Remove legacy PIO definitions [ARM] 4361/1: AT91: Build error ARM: OMAP: Sync core code with linux-omap ARM: OMAP: Sync headers with linux-omap ARM: OMAP: h4 must have blinky leds!! ...
| * [ARM] armv7: add dedicated ARMv7 barrier instructionsCatalin Marinas2007-05-08
| | | | | | | | | | | | | | | | | | Starting with ARMv7, there are dedicated instruction for the ISB, DSB and DMB barriers and there is no need to execute them as CP15 operations. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] armv7: add support for ARMv7 cores.Catalin Marinas2007-05-08
| | | | | | | | | | | | | | This patch adds support for the ARMv7 cores. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Remove tas()Jeff Dike2007-05-08
| | | | | | | | | | | | | | | | | | | | tas() has no users, so get rid of it. Signed-off-by: Jeff Dike <jdike@linux.intel.com> Cc: <linux-arch@vger.kernel.org> Cc: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | move die notifier handling to common codeChristoph Hellwig2007-05-08
|/ | | | | | | | | | | | | | | | | | | | | | | This patch moves the die notifier handling to common code. Previous various architectures had exactly the same code for it. Note that the new code is compiled unconditionally, this should be understood as an appel to the other architecture maintainer to implement support for it aswell (aka sprinkling a notify_die or two in the proper place) arm had a notifiy_die that did something totally different, I renamed it to arm_notify_die as part of the patch and made it static to the file it's declared and used at. avr32 used to pass slightly less information through this interface and I brought it into line with the other architectures. [akpm@linux-foundation.org: build fix] [akpm@linux-foundation.org: fix vmalloc_sync_all bustage] [bryan.wu@analog.com: fix vmalloc_sync_all in nommu] Signed-off-by: Christoph Hellwig <hch@lst.de> Cc: <linux-arch@vger.kernel.org> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [ARM] Add ability to dump exception stacks to kernel backtracesRussell King2007-04-21
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4298/1: fix memory barriers for DMA coherent and SMP platformsLennert Buytenhek2007-04-01
| | | | | | | | | | | | | | | | | | | This patch: - Switches mb/rmb/wmb back to being full-blown DMBs on ARM SMP systems, since mb/rmb/wmb are required to order Normal memory accesses as well. - Enables the use of DMB and ISB on XSC3 (which is an ARMv5TE ISA core but conforms to the ARMv6 memory ordering model and supports the various ARMv6 barriers.) - Makes DMA coherent platforms (only ixp23xx at the moment) map mb/rmb/wmb to dmb(), as on DMA coherent platforms, DMA consistent mappings are done as Normal mappings, which are weakly ordered. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Acked-by: David Howells <dhowells@redhat.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4241/1: Define mb() as compiler barrier on a uniprocessor systemCatalin Marinas2007-03-02
| | | | | | | | | | Currently, the mb() is defined as a DMB operation on ARMv6, even for UP systems. This patch defines mb() as a compiler barrier only. For the SMP case, the smp_* variants should be used anyway and the patch defines them as DMB. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4133/1: Add ISB after changes to CP15 registersCatalin Marinas2007-02-08
| | | | | | | | | | | According to ARM ARM, changes to the CP15 registers are only guaranteed to be visible after an Instruction Synchronization Barrier (ISB). This patch adds the ISB at the end of set_cr and set_copro_access functions and also moves them further down in the file, below the isb macro definition. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4126/1: Add the ARM specific barriersCatalin Marinas2007-02-08
| | | | | | | | There are three barriers - ISB, DMB and DSB for different scenarious. This patch adds their definitions in the system.h file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix warnings from asm/system.hRussell King2006-12-17
| | | | | | | Move adjust_cr() into arch/arm/mm/mmu.c, and move irqflags.h to a more appropriate place in the header file. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Provide a method to alter the control registerRussell King2006-12-13
| | | | | | | | | | i.MX needs to tweak the control register to support CPU frequency scaling. Rather than have folk blindly try and change the control register by writing to it and then wondering why it doesn't work, provide a method (which is safe for UP only, and therefore only available for UP) to achieve this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Handle HWCAP_VFP in VFP support codeRussell King2006-12-08
| | | | | | | | | | | | Don't set HWCAP_VFP in the processor support file; not only does it depend on the processor features, but it also depends on the support code being present. Therefore, only set it if the support code detects that we have a VFP coprocessor attached. Also, move the VFP handling of the coprocessor access register into the VFP support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: manage the CP15 thingsHyok S. Choi2006-09-27
| | | | | | | | | | | | | | | | | | | | | | | All the current CP15 access codes in ARM arch can be categorized and conditioned by the defines as follows: Related operation Safe condition a. any CP15 access !CPU_CP15 b. alignment trap CPU_CP15_MMU c. D-cache(C-bit) CPU_CP15 d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 || CPU_ARM720 || CPU_ARM740 || CPU_XSCALE || CPU_XSC3 ) e. alternate vector CPU_CP15 && !CPU_ARM740 f. TTB CPU_CP15_MMU g. Domain CPU_CP15_MMU h. FSR/FAR CPU_CP15_MMU For example, alternate vector is supported if and only if "CPU_CP15 && !CPU_ARM740" is satisfied. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3852/1: convert atomic bitops and __xchg over to ↵Lennert Buytenhek2006-09-25
| | | | | | | | | | raw_local_irq_{save,restore} Thomas Gleixner noticed that bitops.h should also use the raw_* irq disable/enable variants, and __xchg needs them as well. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Add ARM irqtrace supportRussell King2006-09-20
| | | | | | This adds support for irqtrace for lockdep on ARM. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] remove set_wmb - arch removalSteven Rostedt2006-07-15
| | | | | | | | | | | | | | | | set_wmb should not be used in the kernel because it just confuses the code more and has no benefit. Since it is not currently used in the kernel this patch removes it so that new code does not include it. All archs define set_wmb(var, value) to do { var = value; wmb(); } while(0) except ia64 and sparc which use a mb() instead. But this is still moot since it is not used anyway. Hasn't been tested on any archs but x86 and x86_64 (and only compiled tested) Signed-off-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2006-06-20
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (42 commits) [ARM] Fix tosa build error [ARM] 3610/1: Make reboot work on Versatile [ARM] 3609/1: S3C24XX: defconfig update for s3c2410_defconfig [ARM] 3591/1: Anubis: IDE device definitions [ARM] Include asm/hardware.h not asm/arch/hardware.h [ARM] 3594/1: Poodle: Add touchscreen support + other updates [ARM] 3564/1: sharpsl_pm: Abstract some machine specific parameters [ARM] 3561/1: Poodle: Correct the MMC/SD power control [ARM] 3593/1: Add reboot and shutdown handlers for Zaurus handhelds [ARM] 3599/1: AT91RM9200 remove global variables [ARM] 3607/1: AT91RM9200 misc fixes [ARM] 3605/1: AT91RM9200 Power Management [ARM] 3604/1: AT91RM9200 New boards [ARM] 3603/1: AT91RM9200 remove old files [ARM] 3592/1: AT91RM9200 Serial driver update [ARM] 3590/1: AT91RM9200 Platform devices support [ARM] 3589/1: AT91RM9200 DK/EK board update [ARM] 3588/1: AT91RM9200 CSB337/637 board update [ARM] 3587/1: AT91RM9200 hardware headers [ARM] 3586/1: AT91RM9200 header update ...
| * [ARM] 3593/1: Add reboot and shutdown handlers for Zaurus handheldsRichard Purdie2006-06-19
| | | | | | | | | | | | | | | | | | | | | | Patch from Richard Purdie Add functionality to allow machine specific reboot handlers on ARM. Add machine specific reboot and poweroff handlers for all PXA Zaurus models. Signed-off-by: Richard Purdie <rpurdie@rpsys.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge git://git.infradead.org/hdrcleanup-2.6Linus Torvalds2006-06-20
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.infradead.org/hdrcleanup-2.6: (63 commits) [S390] __FD_foo definitions. Switch to __s32 types in joystick.h instead of C99 types for consistency. Add <sys/types.h> to headers included for userspace in <linux/input.h> Move inclusion of <linux/compat.h> out of user scope in asm-x86_64/mtrr.h Remove struct fddi_statistics from user view in <linux/if_fddi.h> Move user-visible parts of drivers/s390/crypto/z90crypt.h to include/asm-s390 Revert include/media changes: Mauro says those ioctls are only used in-kernel(!) Include <linux/types.h> and use __uXX types in <linux/cramfs_fs.h> Use __uXX types in <linux/i2o_dev.h>, include <linux/ioctl.h> too Remove private struct dx_hash_info from public view in <linux/ext3_fs.h> Include <linux/types.h> and use __uXX types in <linux/affs_hardblocks.h> Use __uXX types in <linux/divert.h> for struct divert_blk et al. Use __u32 for elf_addr_t in <asm-powerpc/elf.h>, not u32. It's user-visible. Remove PPP_FCS from user view in <linux/ppp_defs.h>, remove __P mess entirely Use __uXX types in user-visible structures in <linux/nbd.h> Don't use 'u32' in user-visible struct ip_conntrack_old_tuple. Use __uXX types for S390 DASD volume label definitions which are user-visible S390 BIODASDREADCMB ioctl should use __u64 not u64 type. Remove unneeded inclusion of <linux/time.h> from <linux/ufs_fs.h> Fix private integer types used in V4L2 ioctls. ... Manually resolve conflict in include/linux/mtd/physmap.h
| * Don't include linux/config.h from anywhere else in include/David Woodhouse2006-04-26
| | | | | | | | Signed-off-by: David Woodhouse <dwmw2@infradead.org>
* | [PATCH] ARM: Fix XScale PMD settingDeepak Saxena2006-05-31
|/ | | | | | | | | | | | The ARM Architecture Reference Manual lists bit 4 of the PMD as "implementation defined" and it must be set to zero on Intel XScale CPUs or the cache does not behave properly. Found by Mike Rapoport while debugging a flash issue on the PXA255: http://marc.10east.com/?l=linux-arm-kernel&m=114845287600782&w=1 Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [ARM] 3377/2: add support for intel xsc3 coreLennert Buytenhek2006-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Lennert Buytenhek This patch adds support for the new XScale v3 core. This is an ARMv5 ISA core with the following additions: - L2 cache - I/O coherency support (on select chipsets) - Low-Locality Reference cache attributes (replaces mini-cache) - Supersections (v6 compatible) - 36-bit addressing (v6 compatible) - Single instruction cache line clean/invalidate - LRU cache replacement (vs round-robin) I attempted to merge the XSC3 support into proc-xscale.S, but XSC3 cores have separate errata and have to handle things like L2, so it is simpler to keep it separate. L2 cache support is currently a build option because the L2 enable bit must be set before we enable the MMU and there is no easy way to capture command line parameters at this point. There are still optimizations that can be done such as using LLR for copypage (in theory using the exisiting mini-cache code) but those can be addressed down the road. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3364/1: [cleanup] warning fix - definitions for enable_hlt and disable_hltBen Dooks2006-03-15
| | | | | | | | | | | Patch from Ben Dooks The enable_hlt and disable_hlt should be declared in include/asm/setup.h. This fixes sparse errors from arch/arm/kernel/process.c Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] arm: task_thread_info()Al Viro2006-01-12
| | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] sched: add cacheflush() asmIngo Molnar2006-01-12
| | | | | | | | | | Add per-arch sched_cacheflush() which is a write-back cacheflush used by the migration-cost calibration code at bootup time. Signed-off-by: Ingo Molnar <mingo@elte.hu> Cc: Nick Piggin <nickpiggin@yahoo.com.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [ARM] No need to include asm/proc-fns.h into asm/system.hRussell King2005-11-16
| | | | | | | | | In the old days when arm26/arm32 was combined into the same architecture, proc-fns.h provided the xchg implementation for arm26 CPUs. Since we no longer combine these two, this include is no longer required. Remove it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM SMP: Add ARMv6 memory barriersRussell King2005-07-26
| | | | | | | | Convert explicit gcc asm-based memory barriers into smp_mb() calls. These change between barrier() and the ARMv6 data memory barrier instruction depending on whether ARMv6 SMP is enabled. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM SMP: Use exclusive load/store for __xchgRussell King2005-07-26
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Don't try to send a signal to pid0Russell King2005-06-30
| | | | | | | | | If we receive an unrecognised abort during boot, don't try to send a signal to pid0, but instead report the current state. This leads to less confusing debug reports. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM SMP: __xchg supportRussell King2005-06-28
| | | | | | This enables the existing __xchg implementation to be used on SMP. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] sched: cleanup context switch lockingNick Piggin2005-06-25
| | | | | | | | | | | | | | | | Instead of requiring architecture code to interact with the scheduler's locking implementation, provide a couple of defines that can be used by the architecture to request runqueue unlocked context switches, and ask for interrupts to be enabled over the context switch. Also replaces the "switch_lock" used by these architectures with an oncpu flag (note, not a potentially slow bitflag). This eliminates one bus locked memory operation when context switching, and simplifies the task_running function. Signed-off-by: Nick Piggin <nickpiggin@yahoo.com.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] arm: irqs_disabled() type fixAndrew Morton2005-06-21
| | | | | | | | | | | kernel/sched.c: In function `__might_sleep': kernel/sched.c:5461: warning: int format, long unsigned int arg (arg 3) We expect irqs_disabled() to return an int (poor man's bool). Acked-by: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] ARM SMP: Fix PXA/SA11x0 suspend resume crashRussell King2005-06-19
| | | | | | | We need to re-initialise the stack pointers for undefined, IRQ and abort mode handlers whenever we resume. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: showregsRussell King2005-04-17
| | | | | | | | Fix show_regs() to provide a backtrace. Provide a new __show_regs() function which implements the common subset of show_regs() and die(). Add prototypes to asm-arm/system.h Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-16
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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