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* block: Make the integrity mapped property a bio flagMartin K. Petersen2010-10-15
| | | | | | | | | | | | | | Previously we tracked whether the integrity metadata had been remapped using a request flag. This was fine for low-level retries. However, if an I/O was redriven by upper layers we would end up remapping again, causing the retry to fail. Deprecate the REQ_INTEGRITY flag and introduce BIO_MAPPED_INTEGRITY which enables filesystems to notify lower layers that the bio in question has already been remapped. Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Jens Axboe <jaxboe@fusionio.com>
* sg: fix a warning in blk_rq_aligned() callNamhyung Kim2010-09-16
| | | | | | | | | 2nd argument of blk_rq_aligned() has changed to 'unsigned long' by the previous commit 'block: fix an address space warning in blk-map.c'. That commit neglected to update a user of that function. Signed-off-by: Namhyung Kim <namhyung@gmail.com> Signed-off-by: Jens Axboe <jaxboe@fusionio.com>
* zfcp: Report scatter gather limit for DIX protection informationChristof Schmitt2010-09-10
| | | | | | | | | | | | | | When sending DIX integrity segments with an I/O request, the restriction for the maximum number of segments is still the same for the zfcp hardware. Report the new sg_prot_tablesize for the SCSI host, so that the number of integrity segments plus the number of data segments is not larger than the hardware limit. This results in using half of the hardware segments for integrity data and the other half for regular data. Reviewed-by: Swen Schillig <swen@vnet.ibm.com> Signed-off-by: Christof Schmitt <christof.schmitt@de.ibm.com> Signed-off-by: Jens Axboe <axboe@carl.home.kernel.dk>
* block/scsi: Provide a limit on the number of integrity segmentsMartin K. Petersen2010-09-10
| | | | | | | | | | | | | | | Some controllers have a hardware limit on the number of protection information scatter-gather list segments they can handle. Introduce a max_integrity_segments limit in the block layer and provide a new scsi_host_template setting that allows HBA drivers to provide a value suitable for the hardware. Add support for honoring the integrity segment limit when merging both bios and requests. Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Jens Axboe <axboe@carl.home.kernel.dk>
* Consolidate min_not_zeroMartin K. Petersen2010-09-10
| | | | | | | | We have several users of min_not_zero, each of them using their own definition. Move the define to kernel.h. Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Jens Axboe <axboe@carl.home.kernel.dk>
* Merge branch 'for-linus' of ↵Linus Torvalds2010-08-22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (58 commits) drm/i915,intel_agp: Add support for Sandybridge D0 drm/i915: fix render pipe control notify on sandybridge agp/intel: set 40-bit dma mask on Sandybridge drm/i915: Remove the conflicting BUG_ON() drm/i915/suspend: s/IS_IRONLAKE/HAS_PCH_SPLIT/ drm/i915/suspend: Flush register writes before busy-waiting. i915: disable DAC on Ironlake also when doing CRT load detection. drm/i915: wait for actual vblank, not just 20ms drm/i915: make sure eDP PLL is enabled at the right time drm/i915: fix VGA plane disable for Ironlake+ drm/i915: eDP mode set sequence corrections drm/i915: add panel reset workaround drm/i915: Enable RC6 on Ironlake. drm/i915/sdvo: Only set is_lvds if we have a valid fixed mode. drm/i915: Set up a render context on Ironlake drm/i915 invalidate indirect state pointers at end of ring exec drm/i915: Wake-up wait_request() from elapsed hang-check (v2) drm/i915: Apply i830 errata for cursor alignment drm/i915: Only update i845/i865 CURBASE when disabled (v2) drm/i915: FBC is updated within set_base() so remove second call in mode_set() ...
| * drm/i915,intel_agp: Add support for Sandybridge D0Zhenyu Wang2010-08-22
| | | | | | | | | | Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: fix render pipe control notify on sandybridgeZhenyu Wang2010-08-22
| | | | | | | | | | | | | | | | This one is missed in last pipe control fix for sandybridge, that really unmask interrupt bit for notify in render engine IMR. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * agp/intel: set 40-bit dma mask on SandybridgeZhenyu Wang2010-08-22
| | | | | | | | | | Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Remove the conflicting BUG_ON()Chris Wilson2010-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | We now attempt to free "active" objects following a GPU hang as either the GPU will be reset or the hang is permenant. In either case, the GPU writes will not be flushed to main memory and it should be safe to return that memory back to the system. The BUG_ON(active) is thus overkill and can erroneously fire after a EIO. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915/suspend: s/IS_IRONLAKE/HAS_PCH_SPLIT/Chris Wilson2010-08-22
| | | | | | | | | | | | | | For the shared paths on the next generation chipsets. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915/suspend: Flush register writes before busy-waiting.Chris Wilson2010-08-22
| | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * i915: disable DAC on Ironlake also when doing CRT load detection.Dave Airlie2010-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Like on Sandybridge, disabling the DAC here when doing CRT load detect avoids forever hangs waiting on the hardware. test procedure on HP 2740p: boot with no VGA plugged in, start X, plug in VGA monitor (1280x1024) chvt 3 machine hangs waiting forever. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: wait for actual vblank, not just 20msJesse Barnes2010-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Waiting for a hard coded 20ms isn't always enough to make sure a vblank period has actually occurred, so add code to make sure we really have passed through a vblank period (or that the pipe is off when disabling). This prevents problems with mode setting and link training, and seems to fix a bug like https://bugs.freedesktop.org/show_bug.cgi?id=29278, but on an HP 8440p instead. Hopefully also fixes https://bugs.freedesktop.org/show_bug.cgi?id=29141. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: make sure eDP PLL is enabled at the right timeJesse Barnes2010-08-18
| | | | | | | | | | | | | | We need to make sure the eDP PLL is enabled before the pipes or planes, so do it as part of the DP prepare mode set function. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * drm/i915: fix VGA plane disable for Ironlake+Jesse Barnes2010-08-18
| | | | | | | | | | | | | | | | | | | | We need to use I/O port instructions to access VGA registers on Ironlake+, and it doesn't hurt on other platforms, so switch the VGA plane disable function over to using them. Move it to init time as well while we're at it, no need to repeatedly disable the VGA plane with every mode set and DPMS event. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * drm/i915: eDP mode set sequence correctionsJesse Barnes2010-08-18
| | | | | | | | | | | | | | | | We should disable the panel first when shutting down an eDP link. And when turning one on, the panel needs to be enabled before link training or eDP I/O won't be enabled. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * drm/i915: add panel reset workaroundJesse Barnes2010-08-18
| | | | | | | | | | | | | | | | Ironlake requires that we clear the reset panel bit during power sequences and restore it afterwards. Uncondtionally add code to do that since it should be harmless on SNB+. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * drm/i915: Enable RC6 on Ironlake.Zou Nan hai2010-08-09
| | | | | | | | | | | | | | | | RC6 allows the GPU to enter a lower power state when the GPU is idle. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> [anholt: Fixed the !renderctx error path to actually not enable RC6.] Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915/sdvo: Only set is_lvds if we have a valid fixed mode.Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we have failed to ascertain the fixed mode for the LVDS panel, then trust the pixel clock ranges reported for the connection when determing valid modes. This makes intel_sdvo_mode_valid() consistent with intel_lvds_mode_valid() which is also a no-op is there is no fixed mode defined. (Since the mode is both validated by SDVO and LVDS, why are checking against an LVDS fixed mode in SDVO...) By only defining is_lvds to be true when we actually have an LVDS output with a fixed mode, we avoid various potential NULL deferences where the assumption is made that all LVDS outputs have a fixed mode. References: Bug 29449 - [Q35] failure to read EDID/vbios for LVDS, no mode => no output https://bugs.freedesktop.org/show_bug.cgi?id=29449 The primary failure in this bug is not finding the EDID and determining the correct fixed panel mode. However, this patch should fix the secondary issue of not enabling any of the standard modes for the panel either. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Set up a render context on IronlakeZou Nan hai2010-08-09
| | | | | | | | | | | | | | | | RC6 power state requires a logical render context in place for saving render context. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915 invalidate indirect state pointers at end of ring execZou Nan hai2010-08-09
| | | | | | | | | | | | | | | | This is required by the spec, and without this some 3D programs will hang after resume from RC6 we enable that. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Wake-up wait_request() from elapsed hang-check (v2)Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If our watchdog fires and we see that the GPU is idle, but that we are still waiting on an interrupt, forcibly wake-up the waiter. i915_do_wait_request() should not be racy, yet there are persistent reports that 945GM hangs whilst the GPU is idle. This implies that the hardware is not quite as coherent as the documentation claims - a write followed by a flush is supposed to be coherent in main memory before the flush is retired and the irq is emitted. This seems to be a sensible and elegant guard to force the wait to timeout. v2: Daniel Vetter pointed out that a warning would be useful to explain why the machine appeared to stall. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Apply i830 errata for cursor alignmentChris Wilson2010-08-09
| | | | | | | | | | | | | | | | i830 requires 32bpp cursors to be aligned to 16KB, so we have to expose the alignment parameter to i915_gem_attach_phys_object(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Only update i845/i865 CURBASE when disabled (v2)Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | The i845 and i865 have a peculiarlity in that CURBASE is not the trigger for the vsync update of the cursor registers but instead the modification of that register is prohibited whilst the cursor is enabled. Reorder the write sequence for CURPOS, CURCNTR and CURBASE on i845 to i865 to match. v2: Remove the checks for i845/i865 from within i9xx_cursor_update() Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: FBC is updated within set_base() so remove second call in mode_set()Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | The FBC is dependent upon a few details of the framebuffer so it is required to be updated within set_base(), so remove the redundant call from mode_set(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915/edp: Flush the write before waiting for PLLsChris Wilson2010-08-09
| | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Ensure that while(INREG()) are bounded (v2)Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new macro, wait_for, to simplify the act of waiting on a register to change state. wait_for() takes three arguments, the condition to inspect on every loop, the maximum amount of time to wait and whether to yield the cpu for a length of time after each check. v2: Upgrade failure messages to DRM_ERROR on the suggestion of Eric Anholt. We do not expect to hit these conditions as they reflect programming errors, so if we do we want to be notified. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915/ringbuffer: Set ring->gem_buffer = NULL on init unwindChris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | The cleanup path for early abort failed to nullify the gem_buffer. The likely consequence of this is zero, since a failure here should mean aborting the module load. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Update watermarks for Ironlake after dpms changesChris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we only remembered to update the watermarks for i9xx, and incorrectly assumed that the crtc->enabled flag was valid at that point in the dpms cycle. Note that on my x201s this makes a SR bug on pipe 1 much easier to hit. (Since before this patch when disabling pipe 0, we either didn't update the watermarks at all, or when we did we still thought we had two pipes enabled and so disabled SR.) References: Bug 28969 - [Arrandale] Screen flickers, suspect Self-Refresh https://bugs.freedesktop.org/show_bug.cgi?id=28969 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915/opregion: Use ASLE response codes defined in 0.1Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | | | Within i915_opregion.c there are two blocks of semantically identical ASLE response codes defined. Only one of those matches the ACPI IGD OpRegion Specification 0.1, use those. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Matthew Garrett <mjg59@srcf.ucam.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915/display: Add pipe/plane information to dpms debuggingChris Wilson2010-08-09
| | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Truncate the shmem backing pages on purgeChris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | | | shmfs doesn't actually implement i_ops->truncate() so we were not immedatiately releasing the backing pages when shrinking the gfx cache under OOM. Instead use a combination of truncate_inode_pages() and i_ops->truncate_range() as is used by shmem_delete_inode(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Write to display base last.Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | Writing to the DSPBASE register triggers the double-buffered update to all the control registers, so always write it last in the update sequence. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Enable aspect/centering panel fitting for Ironlake.Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | v2: Hook in DP paths to keep FULLSCREEN panel fitting on eDP. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915/sdvo: Markup a few constant strings.Chris Wilson2010-08-09
| | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Record error batch buffers using iomemChris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | | | Directly read the GTT mapping for the contents of the batch buffers rather than relying on possibly stale CPU caches. Also for completeness scan the flushing/inactive lists for the current buffers - we are collecting error state after all. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Maintain LRU order of inactive objects upon access by CPU (v2)Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to reduce the penalty of fallbacks under memory pressure and to avoid a potential immediate ping-pong of evicting a mmaped buffer, we move the object to the tail of the inactive list when a page is freshly faulted or the object is moved into the CPU domain. We choose not to protect the CPU objects from casual eviction, preferring to keep the GPU active for as long as possible. v2: Daniel Vetter found a bug where I forgot that pinned objects are kept off the inactive list. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Implement fair lru eviction across both rings. (v2)Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based in a large part upon Daniel Vetter's implementation and adapted for handling multiple rings in a single pass. This should lead to better gtt usage and fixes the page-fault-of-doom triggered. The fairness is provided by scanning through the GTT space amalgamating space in rendering order. As soon as we have a contiguous space in the GTT large enough for the new object (and its alignment), evict any object which lies within that space. This should keep more objects resident in the GTT. Doing throughput testing on a PineView machine with cairo-perf-trace indicates that there is very little difference with the new LRU scan, perhaps a small improvement... Except oddly for the poppler trace. Reference: Bug 15911 - Intermittent X crash (freeze) https://bugzilla.kernel.org/show_bug.cgi?id=15911 Bug 20152 - cannot view JPG in firefox when running UXA https://bugs.freedesktop.org/show_bug.cgi?id=20152 Bug 24369 - Hang when scrolling firefox page with window in front https://bugs.freedesktop.org/show_bug.cgi?id=24369 Bug 28478 - Intermittent graphics lockups due to overflow/loop https://bugs.freedesktop.org/show_bug.cgi?id=28478 v2: Attempt to clarify the logic and order of eviction through the use of comments and macros. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Move the eviction logic to its own file.Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | The eviction code is the gnarly underbelly of memory management, and is clearer if kept separated from the normal domain management in GEM. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Use a common seqno for all rings.Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | This will be used by the eviction logic to maintain fairness between the rings. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: prepare for fair lru evictionDaniel Vetter2010-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This does two little changes: - Add an alignment parameter for evict_something. It's not really great to whack a carefully sized hole into the gtt with the wrong alignment. Especially since the fallback path is a full evict. - With the inactive scan stuff we need to evict more that one object, so move the unbind call into the helper function that scans for the object to be evicted, too. And adjust its name. No functional changes in this patch, just preparation. Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Append the object onto the inactive list on binding.Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | | | In order to properly track bound objects, they need to exist on one of the inactive/active lists or be pinned. As this is a requirement, do the work inside i915_gem_bind_to_gtt() rather than dotted around the callsites. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Capture the overlay status upon a GPU hang.Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | v2: Add the interrupt status and address. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Use an uncommon name for the local dev_priv in macrosChris Wilson2010-08-09
| | | | | | | | | | | | | | | | Using dev_priv__ avoids sparse complaining about shadowed variables in the *LP_RING() macros. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Inline ringbuffer_emit()Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | As the function has been reduced to a store plus increment, the body is now smaller than the call so inline it. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Move ringbuffer accounting to begin/advance.Chris Wilson2010-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | As we check that the ringbuffer will not wrap upon emission, we do not need to check that incrementing the tail wrapped every time. However, we do upon advancing just in case the tail is now pointing at the very end of the ring. Likewise we can account for the space used during emission in begin() and avoid decrementing it for every emit. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Unroll wrapping of the ringbuffer.Chris Wilson2010-08-09
| | | | | | | | | | | | | | The tail is quadword aligned, so we can add two MI_NOOP as a time. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Emit a backtrace if we attempt to rebind a pinned bufferChris Wilson2010-08-09
| | | | | | | | | | | | | | | | This debugging trace was useful for finding the fbcon regression on i965, and it may prove useful again in future. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Disable the cursor for DPMS_OFFChris Wilson2010-08-09
| | | | | | | | | | | | | | | | The comments have long desired that we should switch off the cursor along with the display plane, make it so. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
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