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path: root/drivers/spi/au1550_spi.c
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* spi: fix platform driver hotplug/coldplugKay Sievers2008-04-11
| | | | | | | | | | | | Since 43cc71eed1250755986da4c0f9898f9a635cb3bf, the platform modalias is prefixed with "platform:". Add MODULE_ALIAS() to the hotpluggable SPI platform drivers, to allow module auto loading. [dbrownell@users.sourceforge.net: more drivers: registration fixes] Signed-off-by: Kay Sievers <kay.sievers@vrfy.org> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* au1550_spi: fix prototype of irq handlerJan Nikitenko2008-03-13
| | | | | | | | | | Remove struct pt_regs *regs from prototype of au1550_spi_irq handler to avoid warning in request_irq(). Also fix comment type leadin. Signed-off-by: Jan Nikitenko <jan.nikitenko@gmail.com> Signed-off-by: David Brownell <david-b@pacbell.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* SPI controller drivers: check for unsupported modesDavid Brownell2007-07-17
| | | | | | | | | | | | | | Minor SPI controller driver updates: make the setup() methods reject spi->mode bits they don't support, by masking aginst the inverse of bits they *do* support. This insures against misbehavior later when new mode bits get added. Most controllers can't support SPI_LSB_FIRST; more handle SPI_CS_HIGH. Support for all four SPI clock/transfer modes is routine. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* au1550 SPI controller driverJan Nikitenko2007-05-08
Here is a driver for the Alchemy au1550 PSC (Programmable Serial Controller) in SPI master mode. It supports dma transfers using the Alchemy descriptor based dma controller for 4-8 bits per word SPI transfers. For 9-24 bits per word transfers, pio irq based mode is used to avoid setup of dma channels from scratch on each number of bits per word change. Tested with au1550; this may also work on other MIPS Alchemy cpus, like au1200/au1210/au1250. Used extensively with SD card connected via SPI; this handles 8.1MHz SPI clock transfers using dma without any problem (the highest SPI clock freq possible with au1550 running on 324MHz). The driver supports sharing of SPI bus by multiple devices. All features of Alchemy SPI mode are supported (all SPI modes, msb/lsb first, bits per word in 4-24 range). As the SPI clock of the controller depends on main input clock that shall be configured externally, platform data structure for au1550 SPI controller driver contains mainclk_hz attribute to define the input clock rate. From this value, dividers of the controller for SPI clock are set up for required frequency. Signed-off-by: Jan Nikitenko <jan.nikitenko@gmail.com> Whitespace and section fixups. Remove partial workaround for platform setup bug in dma_mask setup; it couldn't work with multiple controllers. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>