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path: root/drivers/scsi/qla2xxx/qla_def.h
Commit message (Expand)AuthorAge
* [SCSI] qla2xxx: Add sysfs node for displaying board temperature.Andrew Vasquez2010-12-23
* [SCSI] qla2xxx: Added support for quiescence mode for ISP82xx.Saurav Kashyap2010-12-23
* [SCSI] qla2xxx: Change MSI initialization from using incorrect request_irq pa...Mike Hernandez2010-12-09
* [SCSI] qla2xxx: Remove port down retry count.Chad Dupuis2010-10-25
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6Linus Torvalds2010-10-22
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| * [SCSI] qla2xxx: Increase SG table size to support large IO size per scsi comm...Giridhar Malavali2010-09-05
| * [SCSI] qla2xxx: Handle MPI timeout indicated by AE8002Madhuranath Iyengar2010-09-05
* | [SCSI] qla2xxx: Fix vport delete issuesArun Easi2010-09-05
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* [SCSI] qla2xxx: Update copyright banner.Giridhar Malavali2010-07-28
* [SCSI] qla2xxx: Rearranged and cleaned up the code for processing the pending...Giridhar Malavali2010-07-28
* [SCSI] qla2xxx: Check for golden firmware and show version if availableMadhuranath Iyengar2010-07-28
* [SCSI] qla2xxx: Use GFF_ID to check FCP-SCSI FC4 type before logging into Nx_...Chad Dupuis2010-07-28
* [SCSI] qla2xxx: Removed dependency for SRB structure for Marker processingGiridhar Malavali2010-07-28
* [SCSI] qla2xxx: Handle outstanding mbx cmds on hung f/w scenarios.Santosh Vernekar2010-07-27
* [SCSI] qla2xxx: Support for loading Unified ROM Image (URI) format firmware f...Harish Zunjarrao2010-07-27
* [SCSI] qla2xxx: Add internal loopback support for ISP81xx.Sarang Radke2010-07-27
* [SCSI] qla2xxx: Correct use-after-free oops seen during EH-abort.Giridhar Malavali2010-07-27
* [SCSI] qla2xxx: Updates to ISP82xx support.Giridhar Malavali2010-05-16
* [SCSI] qla2xxx: T10 DIF support added.Arun Easi2010-05-16
* [SCSI] qla2xxx: Support for asynchronous TM and Marker IOCBs.Madhuranath Iyengar2010-05-16
* [SCSI] qla2xxx: Provide common framework for BSG and IOCB commands.Madhuranath Iyengar2010-05-16
* [SCSI] qla2xxx: Limit mailbox command contention for ADISC requests.Andrew Vasquez2010-05-16
* [SCSI] qla2xxx: Further generalization of SRB CTX infrastructure.Andrew Vasquez2010-05-16
* [SCSI] qla2xxx: Add char device to increase driver use countHarish Zunjarrao2010-05-16
* [SCSI] qla2xxx: Add ISP82XX support.Giridhar Malavali2010-05-01
* [SCSI] qla2xxx: Add APEX support.Sarang Radke2010-04-11
* [SCSI] qla2xxx: Re-organized BSG interface specific code.Giridhar Malavali2010-04-11
* [SCSI] qla2xxx: Add BSG support for FC ELS/CT passthrough and vendor commands.Giridhar Malavali2010-01-18
* [SCSI] qla2xxx: Correct FCP2 recovery handling.Andrew Vasquez2010-01-17
* [SCSI] qla2xxx: Extend base EEH support in qla2xxx.Andrew Vasquez2009-12-30
* [SCSI] qla2xxx: fix for multiqueue in MISX disabled caseAnirban Chakraborty2009-12-10
* [SCSI] qla2xxx: Queue depth ramp up/down modification changes.Giridhar Malavali2009-12-10
* [SCSI] qla2xxx: Set the size of the host buffer used to fetch DCBX and XGMAC ...Giridhar Malavali2009-12-04
* [SCSI] qla2xxx: Add firmware-dump kobject uevent notification.Andrew Vasquez2009-12-04
* [SCSI] qla2xxx: Correctly set FCF_TAPE_PRESENT flag based on scsi-device.Santosh Vernekar2009-09-12
* [SCSI] qla2xxx: Add asynchronous-login support.Andrew Vasquez2009-09-05
* [SCSI] qla2xxx: Generalize srb structure usage.Andrew Vasquez2009-09-05
* [SCSI] qla2xxx: Fix to ensure driver works in sinlge queue mode if multiqueue...Anirban Chakraborty2009-08-22
* [SCSI] qla2xxx: Fix __LITTLE_ENDIAN definition warningsDave Jones2009-08-22
* [SCSI] qla2xxx: Reduce lock-contention during do-work processing.Andrew Vasquez2009-06-08
* [SCSI] qla2xxx: Fallback to 'golden-firmware' operation on supported ISPs.Andrew Vasquez2009-06-08
* [SCSI] qla2xxx: Correct queue-creation bug when driver loaded in QoS mode.Anirban Chakraborty2009-06-08
* [SCSI] qla2xxx: Export TLV data on supported ISPs.Andrew Vasquez2009-06-08
* [SCSI] qla2xxx: Export XGMAC statistics on supported ISPs.Andrew Vasquez2009-06-08
* [SCSI] qla2xxx: Use port number to compute nvram/vpd parameter offsets.Anirban Chakraborty2009-05-20
* [SCSI] qla2xxx: Remove reference to request queue from scsi request block.Anirban Chakraborty2009-05-20
* [SCSI] qla2xxx: Add CPU affinity support.Anirban Chakraborty2009-05-20
* [SCSI] qla2xxx: Add QoS support.Anirban Chakraborty2009-05-20
* [SCSI] qla2xxx: Export additional FCoE attributes for application support.Andrew Vasquez2009-05-20
* [SCSI] qla2xxx: Don't cache VPD data for newer ISPs.Andrew Vasquez2009-04-03
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-09 23:52:30 -0400
> can be included directly #endif #include <linux/compiler.h> #include <asm/assembler.h> #include <asm/system.h> #include <asm/byteorder.h> #include <asm/types.h> /* * These have to be done with inline assembly: that way the bit-setting * is guaranteed to be atomic. All bit operations return 0 if the bit * was cleared before the operation and != 0 if it was not. * * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). */ /** * set_bit - Atomically set a bit in memory * @nr: the bit to set * @addr: the address to start counting from * * This function is atomic and may not be reordered. See __set_bit() * if you do not require the atomic guarantees. * Note that @nr may be almost arbitrarily large; this function is not * restricted to acting on a single-word quantity. */ static __inline__ void set_bit(int nr, volatile void * addr) { __u32 mask; volatile __u32 *a = addr; unsigned long flags; unsigned long tmp; a += (nr >> 5); mask = (1 << (nr & 0x1F)); local_irq_save(flags); __asm__ __volatile__ ( DCACHE_CLEAR("%0", "r6", "%1") M32R_LOCK" %0, @%1; \n\t" "or %0, %2; \n\t" M32R_UNLOCK" %0, @%1; \n\t" : "=&r" (tmp) : "r" (a), "r" (mask) : "memory" #ifdef CONFIG_CHIP_M32700_TS1 , "r6" #endif /* CONFIG_CHIP_M32700_TS1 */ ); local_irq_restore(flags); } /** * clear_bit - Clears a bit in memory * @nr: Bit to clear * @addr: Address to start counting from * * clear_bit() is atomic and may not be reordered. However, it does * not contain a memory barrier, so if it is used for locking purposes, * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() * in order to ensure changes are visible on other processors. */ static __inline__ void clear_bit(int nr, volatile void * addr) { __u32 mask; volatile __u32 *a = addr; unsigned long flags; unsigned long tmp; a += (nr >> 5); mask = (1 << (nr & 0x1F)); local_irq_save(flags); __asm__ __volatile__ ( DCACHE_CLEAR("%0", "r6", "%1") M32R_LOCK" %0, @%1; \n\t" "and %0, %2; \n\t" M32R_UNLOCK" %0, @%1; \n\t" : "=&r" (tmp) : "r" (a), "r" (~mask) : "memory" #ifdef CONFIG_CHIP_M32700_TS1 , "r6" #endif /* CONFIG_CHIP_M32700_TS1 */ ); local_irq_restore(flags); } #define smp_mb__before_clear_bit() barrier() #define smp_mb__after_clear_bit() barrier() /** * change_bit - Toggle a bit in memory * @nr: Bit to clear * @addr: Address to start counting from * * change_bit() is atomic and may not be reordered. * Note that @nr may be almost arbitrarily large; this function is not * restricted to acting on a single-word quantity. */ static __inline__ void change_bit(int nr, volatile void * addr) { __u32 mask; volatile __u32 *a = addr; unsigned long flags; unsigned long tmp; a += (nr >> 5); mask = (1 << (nr & 0x1F)); local_irq_save(flags); __asm__ __volatile__ ( DCACHE_CLEAR("%0", "r6", "%1") M32R_LOCK" %0, @%1; \n\t" "xor %0, %2; \n\t" M32R_UNLOCK" %0, @%1; \n\t" : "=&r" (tmp) : "r" (a), "r" (mask) : "memory" #ifdef CONFIG_CHIP_M32700_TS1 , "r6" #endif /* CONFIG_CHIP_M32700_TS1 */ ); local_irq_restore(flags); } /** * test_and_set_bit - Set a bit and return its old value * @nr: Bit to set * @addr: Address to count from * * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ static __inline__ int test_and_set_bit(int nr, volatile void * addr) { __u32 mask, oldbit; volatile __u32 *a = addr; unsigned long flags; unsigned long tmp; a += (nr >> 5); mask = (1 << (nr & 0x1F)); local_irq_save(flags); __asm__ __volatile__ ( DCACHE_CLEAR("%0", "%1", "%2") M32R_LOCK" %0, @%2; \n\t" "mv %1, %0; \n\t" "and %0, %3; \n\t" "or %1, %3; \n\t" M32R_UNLOCK" %1, @%2; \n\t" : "=&r" (oldbit), "=&r" (tmp) : "r" (a), "r" (mask) : "memory" ); local_irq_restore(flags); return (oldbit != 0); } /** * test_and_clear_bit - Clear a bit and return its old value * @nr: Bit to set * @addr: Address to count from * * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ static __inline__ int test_and_clear_bit(int nr, volatile void * addr) { __u32 mask, oldbit; volatile __u32 *a = addr; unsigned long flags; unsigned long tmp; a += (nr >> 5); mask = (1 << (nr & 0x1F)); local_irq_save(flags); __asm__ __volatile__ ( DCACHE_CLEAR("%0", "%1", "%3") M32R_LOCK" %0, @%3; \n\t" "mv %1, %0; \n\t" "and %0, %2; \n\t" "not %2, %2; \n\t" "and %1, %2; \n\t" M32R_UNLOCK" %1, @%3; \n\t" : "=&r" (oldbit), "=&r" (tmp), "+r" (mask) : "r" (a) : "memory" ); local_irq_restore(flags); return (oldbit != 0); } /** * test_and_change_bit - Change a bit and return its old value * @nr: Bit to set * @addr: Address to count from * * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ static __inline__ int test_and_change_bit(int nr, volatile void * addr) { __u32 mask, oldbit; volatile __u32 *a = addr; unsigned long flags; unsigned long tmp; a += (nr >> 5); mask = (1 << (nr & 0x1F)); local_irq_save(flags); __asm__ __volatile__ ( DCACHE_CLEAR("%0", "%1", "%2") M32R_LOCK" %0, @%2; \n\t" "mv %1, %0; \n\t" "and %0, %3; \n\t" "xor %1, %3; \n\t" M32R_UNLOCK" %1, @%2; \n\t" : "=&r" (oldbit), "=&r" (tmp) : "r" (a), "r" (mask) : "memory" ); local_irq_restore(flags); return (oldbit != 0); } #include <asm-generic/bitops/non-atomic.h> #include <asm-generic/bitops/ffz.h> #include <asm-generic/bitops/__ffs.h> #include <asm-generic/bitops/fls.h> #include <asm-generic/bitops/fls64.h> #ifdef __KERNEL__ #include <asm-generic/bitops/sched.h> #include <asm-generic/bitops/find.h> #include <asm-generic/bitops/ffs.h> #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> #endif /* __KERNEL__ */ #ifdef __KERNEL__ #include <asm-generic/bitops/ext2-non-atomic.h> #include <asm-generic/bitops/ext2-atomic.h> #include <asm-generic/bitops/minix.h> #endif /* __KERNEL__ */ #endif /* _ASM_M32R_BITOPS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-09 23:52:29 -0400