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* pinctrl: berlin: fix an error code in berlin_pinctrl_probe()Dan Carpenter2014-07-04
| | | | | | | | | | We are returning success here because PTR_ERR(NULL) is zero. We should be returning -ENODEV. Fixes: 3de68d331c24 ('pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Fix potential null pointer dereferenceSachin Kamat2014-06-19
| | | | | | | | | kzalloc can fail. Add a null check to avoid null pointer dereference error while accessing the pointer later. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v3.16-1' of ↵Linus Torvalds2014-06-03
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into next Pull pin control changes from Linus Walleij: "This is the bulk of pin control changes for the v3.16 development cycle: - Antoine Tenart made the get_group_pins() vtable entry optional. - Antoine also provides an entirely new driver for the Marvell Berlin SoC. This is unrelated to the existing MVEBU hardware driver and warrants its own separate driver. - reflected from the GPIO subsystem there is a number of refactorings to make pin control drivers with gpiochips use the new gpiolib irqchip helpers. The following drivers were converted to use the new infrastructure: * ST Microelectronics STiH416 and friends * The Atmel AT91 * The CSR SiRF (Prima2) * The Qualcomm MSM series - massive improvements in the Qualcomm MSM driver from Bjorn Andersson, Andy Gross and Kumar Gala. Among those new support for the IPQ8064 and MSM8x74 SoC variants. - support for the Freescale i.MX6 SoloX SoC variant. - massive improvements in the Allwinner sunxi driver from Boris Brezillon, Maxime Ripard and Chen-Yu Tsai. - Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto, Wolfram Sang and Magnus Damm. - Cleanups and refactorings of the nVidia Tegra driver from Stepgen Warren. - the Exynos driver now supports the Exynos3250 SoC. - Intel BayTrail updates from Jin Yao, Mika Westerberg. - the MVEBU driver now supports the Orion5x SoC variants, which is part of the effort of getting rid of the old Marvell kludges in arch/arm/mach-orion5x - Rockchip driver updates from Heiko Stuebner. - a ton of cleanups and janitorial patches from Axel Lin. - some minor fixes and improvements here and there" * tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits) pinctrl: sirf: fix a bad conflict resolution pinctrl: msm: Add more MSM8X74 pin definitions pinctrl: qcom: ipq8064: Fix naming convention pinctrl: msm: Add missing sdc1 and sdc3 groups pinctrl: sirf: switch to using allocated state container pinctrl: Enable "power-source" to be extracted from DT files pinctrl: sunxi: create irq/pin mapping during init pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy pinctrl: berlin: Use devm_ioremap_resource() pinctrl: sirf: fix typo for GPIO bank number pinctrl: sunxi: depend on RESET_CONTROLLER pinctrl: sunxi: fix pin numbers passed to register offset helpers pinctrl: add pinctrl driver for imx6sx pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs pinctrl: msm: switch to using generic GPIO irqchip helpers pinctrl: sunxi: Fix multiple registration issue pinctrl: sunxi: Fix recursive dependency pinctrl: berlin: add the BG2CD pinctrl driver pinctrl: berlin: add the BG2 pinctrl driver pinctrl: berlin: add the BG2Q pinctrl driver ...
| * pinctrl: sirf: fix a bad conflict resolutionLinus Walleij2014-05-30
| | | | | | | | | | | | | | | | | | | | Commit 294d1351ff47726f0f110b88e816cbafe89512fb "pinctrl: sirf: switch to using allocated state container" caused a build conflict due to a bad conflict resolution when cherry-picking the patch. Fix it up. Cc: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Add more MSM8X74 pin definitionsAndy Gross2014-05-29
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds pin definitiones for the MSM8x74 TLMM. New definitions include: BLSP devices (I2C, UART, SPI, and UIM), mi2s, gp clk, pdm, gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted pins. Signed-off-by: Andy Gross <agross@codeaurora.org> Acked-By: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: ipq8064: Fix naming conventionKumar Gala2014-05-29
| | | | | | | | | | | | | | | | Drop underscore in spdif_groups to match all other groups. Signed-off-by: Kumar Gala <galak@codeaurora.org> Reviewed-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Add missing sdc1 and sdc3 groupsBjorn Andersson2014-05-28
| | | | | | | | | | Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sirf: switch to using allocated state containerLinus Walleij2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | This rewrites the SIRF pinctrl driver to allocate a state container for the GPIO chip, just as is done for the pin controller, and use the gpiochip_add_pin_range() to add the range from the gpiochip side rather than adding the range from the pinctrl side. All resulting changes are done in order to pass around a state container rather than refer to a static global object. Acked-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Enable "power-source" to be extracted from DT filesIvan T. Ivanov2014-05-28
| | | | | | | | | | | | | | | | | | Add "power-source" property to generic options used for DT parsing files. This enables drivers, which use generic pin configurations, to get the value passed to this property. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: create irq/pin mapping during initChen-Yu Tsai2014-05-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The irq/pin mapping is used to lookup the pin to mux to the irq function when the irq is enabled. It is created when gpio_to_irq is called. Creating the mapping during init allows us to map the interrupts directly from the device tree. Originally the IRQ to pin mapping was created when gpio_to_irq was called with a GPIO handle. The mapping in turn is used to mux the pin into EINT mode. If the mapping is created during gpio_to_irq, we can't use the interrupts directly, i.e. through the DT with "interrupts = <&pio A 4>". Instead we'd have to use "gpios = <&pio A B>", then pass the gpio through to gpio_to_irq. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpyBenoit Taine2014-05-27
| | | | | | | | | | | | | | | | This issue was reported by coccicheck using the semantic patch at scripts/coccinelle/api/memdup.cocci Signed-off-by: Benoit Taine <benoit.taine@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: berlin: Use devm_ioremap_resource()Jingoo Han2014-05-27
| | | | | | | | | | | | | | | | | | Use devm_ioremap_resource() because devm_request_and_ioremap() is obsoleted by devm_ioremap_resource(). Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sirf: fix typo for GPIO bank numberBarry Song2014-05-27
| | | | | | | | | | | | | | | | | | | | | | | | | | The patch 7420d2d09b12: "pinctrl: sirf: switch driver to use gpiolib irqchip helpers" from Apr 15, 2014, leads to the following static checker warning: drivers/pinctrl/sirf/pinctrl-sirf.c:578 sirfsoc_gpio_handle_irq() warn: buffer overflow 'sgpio_chip.sgpio_bank' 5 <= 31 Cc: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: depend on RESET_CONTROLLERMaxime Ripard2014-05-27
| | | | | | | | | | | | | | | | | | The A31 R_PIO driver depends on the reset framework in a mandatory way. Express this by adding a depends on the reset framework in Kconfig Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: fix pin numbers passed to register offset helpersChen-Yu Tsai2014-05-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pin numbers passed to sunxi_*_reg helpers to get the correct registers should be the pin offset for the PIO block, not the absolute number we use that is based on the alphanumeric labels Allwinner uses. This patch subtracts .pin_base from the pin number passed to these functions, so the driver accesses the correct registers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: add pinctrl driver for imx6sxAnson Huang2014-05-27
| | | | | | | | | | | | | | | | | | Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core driver. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occursAlexander Stein2014-05-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit 80cc3732 (pinctrl/at91: convert driver to use gpiolib irqchip) gpiochip_set_chained_irqchip is called for PIOC, PIOD and PIOE. The associated GPIO chip for the IRQ chip is overwritten each time, because they share the same hard IRQ line. Thus if an IRQ occurs on PIOC or PIOD, gpio_irq_handler will only check on PIOE (the assigned GPIO chip) where no event occured. Thus the IRQ will not be cleared, retriggering the ISR. Fix that (like done before) by only set the PIOC GPIO chip to the IRQ chip and walk the list in the irq handler. Signed-off-by: Alexander Stein <alexanders83@web.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: switch to using generic GPIO irqchip helpersLinus Walleij2014-05-22
| | | | | | | | | | | | | | | | | | | | This switches the Qualcomm MSM pin control driver over to using the generic GPIO irqchip helpers. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Josh Cartwright <joshc@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Fix multiple registration issueMaxime Ripard2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When the support for the PRCM muxer on the A31 has been added, the global static pinctl_desc definition has been left as is. Unfortunately, this structure is used to register the pinctrl device, and prior to this registration, we set the name and pins field. Since this structure is shared across instances, that means that the latest registered pinctrl device wins in setting the name, pins and pins numbers, which is not really a good thing. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Fix recursive dependencyMaxime Ripard2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following configuration error: drivers/pinctrl/sunxi/Kconfig:3:error: recursive dependency detected! drivers/pinctrl/sunxi/Kconfig:3: symbol PINCTRL_SUNXI is selected by PINCTRL_SUN4I_A10 drivers/pinctrl/sunxi/Kconfig:9: symbol PINCTRL_SUN4I_A10 default value contains PINCTRL_SUNXI Add a new intermedia PINCTRL_SUNXI_COMMON, that superseeds the PINCTRL_SUNXI one. We still need to keep PINCTRL_SUNXI at the moment in order to preserve bisectability. Indeed, during that merge window, we also introduced the MACH_SUN* symbols. Since it's going through different trees, we can't rely on the fact that the options will be there, while ARCH_SUNXI still select PINCTRL_SUNXI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: berlin: add the BG2CD pinctrl driverAntoine Tenart2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | Add the pin-controller driver for the Berlin BG2Q SoC, with definition of its groups and functions. Pin control registers are part of chip/ system control registers, which will be represented by a single node. Until a proper driver for the chip/system control is available, register the corresponding regmap in pinctrl driver probe. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: berlin: add the BG2 pinctrl driverAntoine Tenart2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | Add the pin-controller driver for the Berlin BG2 SoC, with definition of its groups and functions. Pin control registers are part of chip/ system control registers, which will be represented by a single node. Until a proper driver for the chip/system control is available, register the corresponding regmap in pinctrl driver probe. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: berlin: add the BG2Q pinctrl driverAntoine Tenart2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | Add the pin-controller driver for the Berlin BG2Q SoC, with definition of its groups and functions. Pin control registers are part of chip/ system control registers, which will be represented by a single node. Until a proper driver for the chip/system control is available, register the corresponding regmap in pinctrl driver probe. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCsAntoine Tenart2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell Berlin boards have a group based pinmuxing mechanism. This adds the core driver support. We actually do not need any information about the pins here and only have the definition of the groups. Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set to mode 0: Group Modes Offset Base Offset LSB Bit Width GSM12 3 sm_base 0x40 0x10 0x2 Ball Group Mode 0 Mode 1 Mode 2 BK4 GSM12 UART0_RX IrDA0_RX GPIO9 BH6 GSM12 UART0_TX IrDA0_TX GPIO10 So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need to set (sm_base + 0x40 + 0x10) &= ff3fffff. As pin control registers are part of either chip control or system control registers, that deal with a bunch of other functions we rely on a regmap instead of exclusively remapping any resources. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: baytrail: Add pull type, strength and open drain to debugfs outputMika Westerberg2014-05-22
| | | | | | | | | | | | | | | | | | In case of resolving power management or similar issues it might be useful to have these properties included in the debugfs output. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: baytrail: Register GPIO chip after chip->to_irq is setJin Yao2014-05-22
| | | | | | | | | | | | | | | | | | | | If chip->to_irq is NULL ACPI GPIO helpers don't register GPIO event handlers thus preventing any ACPI GPIO triggered events. Solve this by calling gpiochip_add() after we have set up drivers chip->to_irq hook. Signed-off-by: Jin Yao <yao.jin@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: baytrail: Add back Baytrail-T ACPI IDJin Yao2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the x86 dynamic IRQ allocation problem has been resolved with commmit 62a08ae2a576 (genirq: x86: Ensure that dynamic irq allocation does not conflict), we can add back Baytrail-T ACPI ID to the pinctrl driver. This makes the driver to work on Asus T100 where it is needed for several things like ACPI GPIO events and SD card detection. References: https://bugzilla.kernel.org/show_bug.cgi?id=68291 Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Jin Yao <yao.jin@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a73a4: Allow Multiplatform BuildMagnus Damm2014-05-22
| | | | | | | | | | | | | | | | | | Add #ifdefs to allow r8a73a4 Multiplatform build. Needed to enable r8a73a4 Multiplatform support. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: sh73a0: Allow Multiplatform BuildMagnus Damm2014-05-22
| | | | | | | | | | | | | | | | | | Add #ifdefs to allow sh73a0 Multiplatform build. Needed to enable sh73a0 Multiplatform support. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a7740: Allow Multiplatform BuildMagnus Damm2014-05-22
| | | | | | | | | | | | | | | | | | Add #ifdefs to allow r8a7740 Multiplatform build. Needed to enable r8a7740 Multiplatform support. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: Don't set the pinmux_irq irq field for multiplatformLaurent Pinchart2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | In the multiplatform kernel case the IRQs associated with the PFC GPIOs are specified through DT. The pinmux_irq irq field is thus ignored by the code, and doesn't need to be set. This will allow removing the mach/irq.h include from pfc-*.c files that was required for the irq_pin() macro used to initialize the irq field. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Enable the pinctrl Kconfig options by defaultMaxime Ripard2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | Enable the freshly introduced Kconfig options whenever their matching architecture is enabled. Since the Kconfig symbols for these machines are going through a different tree, keep PINCTRL_SUNXI around for the moment to avoid breaking the defconfig. It should be removed eventually. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: base regmap supplied by a sysconHeiko Stübner2014-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | This allows the basic registers of the general register files to be supplied by a syscon instead of being mapped locally. The GRF registers contain a lot more than pinctrl functions like dma, usb-phy and general soc control and status registers, intermixed with the iomux, pull and drive-strength registers. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: only map bank0-pull-region when pmu regmap missingHeiko Stübner2014-05-09
| | | | | | | | | | | | | | | | | | When the pmu registers are supplied through a syscon regmap we do not need to map the registers ourself. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: let pmu registers be supplied by a sysconHeiko Stübner2014-05-09
| | | | | | | | | | | | | | | | | | | | Currently the pmu registers containing pin pull settings on the rk3188 are mapped locally when bank0 is instantiated. Add an alternative that can resolve the pmu from a syscon phandle. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: rockchip_pinctrl in rockchip_get_bank_dataHeiko Stübner2014-05-09
| | | | | | | | | | | | | | | | | | Convert rockchip_get_bank_data to use the struct rockchip_pinctrl because later on we need to check a value from it when registering the gpio banks. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: use regmaps instead of raw mappingsHeiko Stübner2014-05-09
| | | | | | | | | | | | | | | | This allows us to use syscons in the future. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: do not require 2nd register areaHeiko Stübner2014-05-09
| | | | | | | | | | | | | | | | | | | | | | Deprecate secondary register area for rk3188 pulls. Instead use big enough initial mapping of grf registers to catch all. The now deprecated register is still supported though. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'sunxi-pinctrl-for-3.16' of https://github.com/mripard/linux into ↵Linus Walleij2014-05-09
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devel Pinctrl cleanup and reworks for 3.16 This serie of patch: - Moves the Allwinner pinctrl driver to a folder of its own - removes the sunxi-pinctrl-pins header, and split the driver into a core one, with all the logic, and smaller drivers, one for each SoC, that declare the pins, and will provide to the core the set of pins. - And does a few cleanups here and there.
| | * pinctrl: sunxi: Move the reset handling functions out of the coreMaxime Ripard2014-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way that reset is handled right now is that it is made optional for every pinctrl driver, while actually, it isn't used at all for the main pin controllers so far, and while it's mandatory for the A31's secondary pin controller. Move the reset functions out of the core and in the driver, where they can be made mandatory. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * pinctrl: sunxi: Introduce per-driver Kconfig optionsMaxime Ripard2014-05-04
| | | | | | | | | | | | | | | | | | | | | Add one Kconfig option for each driver. This will allow to better control which driver is enabled, instead of having either all or nothing. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * pinctrl: sunxi: Move Allwinner A20 pinctrl driver to a driver of its ownMaxime Ripard2014-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the pin description to a driver specific to be. This is the final step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. We can finally remove that header, and remove all the driver part of the pinctrl-sunxi core. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * pinctrl: sunxi: Move Allwinner A31 special pins driver to a driver of its ownMaxime Ripard2014-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * pinctrl: sunxi: Move Allwinner A31 pinctrl driver to a driver of its ownMaxime Ripard2014-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * pinctrl: sunxi: Move Allwinner A13 pinctrl driver to a driver of its ownMaxime Ripard2014-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * pinctrl: sunxi: Move Allwinner A10s pinctrl driver to a driver of its ownMaxime Ripard2014-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * pinctrl: sunxi: Move Allwinner A10 pinctrl driver to a driver of its ownMaxime Ripard2014-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * pinctrl: sunxi: Libraryse the driverMaxime Ripard2014-05-04
| | | | | | | | | | | | | | | | | | | | | This will allow to have multiple drivers using the same core code, and eventually, retire pinctrl-sunxi-pins.h Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * pinctrl: sunxi: Switch to devm_ioremap_resourceMaxime Ripard2014-05-04
| | | | | | | | | | | | | | | | | | | | | | | | The previous code was calling of_iomap, which doesn't do any resource management, and doesn't call request_mem_region either. Use devm_ioremap_resource that do both. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * pinctrl: sunxi: Replace hardcoded pin defines by a macroMaxime Ripard2014-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | We previously had an evergrowing (and exhaustive) list of the pins that could be used on any Allwinner SoCs. These defines were then used by each pinctrl driver to declare the list of functions for this pin. Since it's pretty much all boilerplate, we can remove it just by a single macro. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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