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* sh-pfc: r8a7791: Fix definition of MOD_SEL3Phil Edworthy2014-04-23
| | | | | | | | There is a missing 0 entry from the MOD_SEL3 table. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* sh-pfc: r8a7790: Fix definition of IPSR5Guido Piasenza2014-04-23
| | | | | | | | | The extra entry in the table makes SCIFA0_B, and all peripherals after it, fail. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: single: Clear pin interrupts enabled by bootloaderTony Lindgren2014-04-23
| | | | | | | | | | | | | | | | | | | | | Since we set up device wake-up interrupts as pinctrl-single interrupts, we now must use the standard request_irq and related functions to manage them. If the pin interrupts are enabled for some pins at boot, the wake-up events can show up as constantly pending at least on omaps and will hang the system unless the related device driver clears the event at the device. To fix this, let's clear the interrupt flags during init, and print out a warning so the board maintainers can update their drivers to do proper request_irq for the driver specific wake-up events. Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: as3722: fix handling of GPIO invert bitAndrew Bresticker2014-04-22
| | | | | | | | | | | | | | | | | | | | The AS3722_GPIO_INV bit will always be blindly overwritten by as3722_pinctrl_gpio_set_direction() and will be ignored when setting the value of the GPIO in as3722_gpio_set() since the enable_gpio_invert flag is never set. This will cause an initially inverted GPIO to toggle when requested as an output, which could be problematic if, for example, the GPIO controls a critical regulator. Instead of setting up the enable_gpio_invert flag, just leave the invert bit alone and check it before setting the GPIO value. Cc: <stable@vger.kernel.org> # v3.14+ Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl/TB10x: Fix signedness bugChristian Ruppert2014-04-22
| | | | | | | | | | | | In the TB10x pin database, a port index of -1 is used to indicate unmuxed GPIO pin groups. This bug fixes a 'cast to unsigned' bug of this value. Thanks to Dan Carpenter for highlighting this. CC: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Rename Broadcom Capri pinctrl driverSherman Yin2014-04-14
| | | | | | | | | | | | | | | | | To be consistent with other Broadcom drivers, the Broadcom Capri pinctrl driver and its related CONFIG option are renamed to bcm281xx. Devicetree compatible string and binding documentation use "brcm,bcm11351-pinctrl" to match the machine binding here: Documentation/devicetree/bindings/arm/bcm/bcm11351.txt This driver supports pinctrl on BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155 SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: msm: Correct interrupt code for TLMM v2Bjorn Andersson2014-04-14
| | | | | | | | | Acking interrupts are done differently between on v2 and v3, so add an extra attribute to the pingroup struct to let the platform definitions control this. Also make sure to start dual edge detection by detecting the rising edge. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: nomadik: delete stray debug printLinus Walleij2014-04-14
| | | | | | I left this in by mistake, get rid of it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: handle first half of rk3188-bank0 correctlyHeiko Stübner2014-04-14
| | | | | | | | | | | The first half of pinbank 0 only has one muxing function (as gpios) and does not have a special mux-register. Therefore ensure that no other mux function can be selected and also do not write to a non-existent register. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: add return value to rockchip_set_muxHeiko Stübner2014-04-14
| | | | | | | | | In a following change, rockchip_set_mux gets the possibility to fail. Therefore add a return value to it and honor error codes in functions using rockchip_set_mux. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: fix offset of mux registers for rk3188Beniamino Galvani2014-04-14
| | | | | | | | | | | | | | | | | | | | | | | | The correct value of .mux_offset for rk3188 seems to be 0x60 instead of 0x68. Heiko adds: GPIO0 only has the second two IOMUX registers: - GRF_GPIO0C_IOMUX at 0x68 - GRF_GPIO0D_IOMUX at 0x6c which I guess is where my mistake comes from. It looks like there does no iomux register exist at all for the first 16 pins. In any case, the current number is wrong, and the 0x60 offset is the correct one, but I guess we need to determine what the affected pins do - do they always have a gpio mux or such? Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'gpio-v3.15-1' of ↵Linus Torvalds2014-04-03
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull bulk of gpio updates from Linus Walleij: "A pretty big chunk of changes this time, but it has all been on rotation in linux-next and had some testing. Of course there will be some amount of fixes on top... - Merged in a branch of irqchip changes from Thomas Gleixner: we need to have new callbacks from the irqchip to determine if the GPIO line will be eligible for IRQs, and this callback must be able to say "no". After some thinking I got the branch from tglx and have switched all current users over to use this. - Based on tglx patches, we have added some generic irqchip helpers in the gpiolib core. These will help centralize code when GPIO drivers have simple chained/cascaded IRQs. Drivers will still define their irqchip vtables, but the gpiolib core will take care of irqdomain set-up, mapping from local offsets to Linux irqs, and reserve resources by marking the GPIO lines for IRQs. - Initially the PL061 and Nomadik GPIO/pin control drivers have been switched over to use the new gpiochip-to-irqchip infrastructure with more drivers expected for the next kernel cycle. The factoring of just two drivers still makes it worth it so it is already a win. - A new driver for the Synopsys DesignWare APB GPIO block. - Modify the DaVinci GPIO driver to be reusable also for the new TI Keystone architecture. - A new driver for the LSI ZEVIO SoCs. - Delete the obsolte tnetv107x driver. - Some incremental work on GPIO descriptors: have gpiod_direction_output() use a logical level, respecting assertion polarity through ACTIVE_LOW flags, adding gpiod_direction_output_raw() for the case where you want to set that very value. Add gpiochip_get_desc() to fetch a GPIO descriptor from a specific offset on a certain chip inside driver code. - Switch ACPI GPIO code over to using gpiochip_get_desc() and get rid of gpio_to_desc(). - The ACPI GPIO event handling code has been reworked after encountering an actual real life implementation. - Support for ACPI GPIO operation regions. - Generic GPIO chips can now be assigned labels/names from platform data. - We now clamp values returned from GPIO drivers to the boolean [0,1] range. - Some improved documentation on how to use the polarity flag was added. - a large slew of incremental driver updates and non-critical fixes. Some targeted for stable" * tag 'gpio-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (80 commits) gpio: rcar: Add helper variable dev = &pdev->dev gpio-lynxpoint: force gpio_get() to return "1" and "0" only gpio: unmap gpio irqs properly pch_gpio: set value before enabling output direction gpio: moxart: Actually set output state in moxart_gpio_direction_output() gpio: moxart: Avoid forward declaration gpio: mxs: Allow for recursive enable_irq_wake() call gpio: samsung: Add missing "break" statement gpio: twl4030: Remove redundant assignment gpio: dwapb: correct gpio-cells in binding document gpio: iop: fix devm_ioremap_resource() return value checking pinctrl: coh901: convert driver to use gpiolib irqchip pinctrl: nomadik: convert driver to use gpiolib irqchip gpio: pl061: convert driver to use gpiolib irqchip gpio: add IRQ chip helpers in gpiolib pinctrl: nomadik: factor in platform data container pinctrl: nomadik: rename secondary to latent gpio: Driver for SYSCON-based GPIOs gpio: generic: Use platform_device_id->driver_data field for driver flags pinctrl: coh901: move irq line locking to resource callbacks ...
| * pinctrl: coh901: convert driver to use gpiolib irqchipLinus Walleij2014-03-26
| | | | | | | | | | | | | | | | This converts the COH901 pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nomadik: convert driver to use gpiolib irqchipLinus Walleij2014-03-26
| | | | | | | | | | | | | | | | This converts the Nomadik pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nomadik: factor in platform data containerLinus Walleij2014-03-25
| | | | | | | | | | | | | | | | | | The old platform data struct is just a leftover from the times when the driver was not probed exclusively from the device tree. Factor this into the general state container and simplify the probe path. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nomadik: rename secondary to latentLinus Walleij2014-03-25
| | | | | | | | | | | | | | | | | | | | The "secondary irq" in the nomadik pin control driver is actually not secondary (as in: can occur any time alongside the ordinary irq), it is a latent IRQ. It is an IRQ that has occurred when the system was in sleep state and has been cached in a special register flagged from the low power management unit (PRCM). Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: coh901: move irq line locking to resource callbacksLinus Walleij2014-03-18
| | | | | | | | | | | | | | | | | | | | This switches the COH901 GPIO driver over to using the .request_resources() and .release_resources() callbacks from the irqchip vtable and separate the calls from the .enable() and .disable() callbacks as the latter cannot really say no to a request, whereas the resource callbacks can. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * gpio: switch drivers to use new callbackLinus Walleij2014-03-18
| | | | | | | | | | | | | | | | | | | | | | | | This switches all GPIO and pin control drivers with irqchips that were using .startup() and .shutdown() callbacks to lock GPIO lines for IRQ usage over to using the .request_resources() and .release_resources() callbacks just introduced into the irqchip vtable. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'pinctrl-v3.15-1' of ↵Linus Torvalds2014-04-01
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control bulk changes from Linus Walleij: "Pin control bulk changes for the v3.15 series, no new core functionality this time, just incremental driver updates: - A large refactoring of the MVEBU (Marvell) driver. - A large refactoring of the Tegra (nVidia) driver. - GPIO interrupt including soft edges support in the STi driver. - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin), pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi (AllWinner), i.MX (Freescale), Baytrail" * tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: tegra: add some missing Tegra114 entries pinctrl: tegra: fix some mistakes in Tegra124 pinctrl: msm: fix up out-of-order merge conflict pinctrl: st: Fix error check for of_irq_to_resource usage pinctrl: tegra: consistency cleanup pinctrl: tegra: dynamically calculate function list of groups pinctrl: tegra: init Tegra20/30 at module_init time pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays pinctrl: st: add pinctrl support for the STiH407 SoC pinctrl: st: Enhance the controller to manage unavailable registers pinctrl: msm: Simplify msm_config_reg() and callers pinctrl: msm: Remove impossible WARN_ON()s pinctrl: msm: Replace lookup tables with math pinctrl: msm: Drop OF_IRQ dependency pinctrl: msm: Drop unused includes pinctrl: msm: Check for ngpios > MAX_NR_GPIO pinctrl: msm: Silence recursive lockdep warning pinctrl: mvebu: silence WARN to dev_warn pinctrl: msm: drop wake_irqs bitmap pinctrl-baytrail: add function mux checking in gpio pin request ...
| * pinctrl: tegra: add some missing Tegra114 entriesStephen Warren2014-03-14
| | | | | | | | | | | | | | | | | | | | | | | | | | Add some missing pin and drive group definitions to the driver. These are all defined in the TRM, but missing from the driver for some reason. Fix a couple of mistakes in the drive group definitions. Much of the diff to tegra114_groups[] is an indentation change due to one of the new group names being long. git diff/show -w will highlight this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: fix some mistakes in Tegra124Stephen Warren2014-03-14
| | | | | | | | | | | | | | | | | | | | A couple of pairs of pin group names were swapped in the table. This caused the wrong register to be programmed. Luckily, this had little effect, if any, since the swapped pins were likely to be programmed identically. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: fix up out-of-order merge conflictLinus Walleij2014-03-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 051a58b4622f0e1b732acb750097c64bc00ddb93 "pinctrl: msm: Simplify msm_config_reg() and callers" removed the local "reg" variable in the msm_config_reg() function, but the earlier commit ed118a5fd951bd2def8249ee251842c4f81fe4bd "pinctrl-msm: Support output-{high,low} configuration" introduced a new switchclause using it. Fix this up by removing the offending register assignment. Reported-by: Kbuild test robot <fengguang.wu@intel.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: st: Fix error check for of_irq_to_resource usageSrinivas Kandagatla2014-03-12
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an error check while using of_irq_to_resource. of_irq_to_resource returns non-zero interrupt number on success and zero on error. The driver was using error check is wrong way. Without this patch the driver will configure interrupt zero if there is no interrupt specified in the node. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: consistency cleanupStephen Warren2014-03-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix Tegra30/114/124 pinmux drivers consistency issues. * Sort all lists of the same object type (e.g. #defines for pins, and the array that defines their names) in the same order. * Whitespace fixes. * Consistency in layout between the 3 drivers. These driver files were also auto-generated, which should allow us to make e.g. the U-Boot drivers completely consistent with the kernel in the future:-) Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: dynamically calculate function list of groupsStephen Warren2014-03-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The per-SoC data structures for Tegra pinctrl stored some information in a redundant way. Specifically, the list of groups that each function could be muxed onto was stored once explicitly, and also as part of the definition of each group. Eliminate this redundancy, and calculate each function's list of valid groups at pinctrl probe time. This removes thousands of lines of code from the pinctrl driver and ~16K from the vmlinux binary size, and adds only about 500uS to the boot process (on Tegra30; newer SoCs will likely be faster still). Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: init Tegra20/30 at module_init timeStephen Warren2014-03-12
| | | | | | | | | | | | | | | | | | The Tegra20/30 pinctrl drivers currently initializes at arch_initcall, whereas Tegra114/124 pinctrl drivers initialize at module_init time. Convert Tegra20/30 to work the same way as the other drivers. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delaysMaxime COQUELIN2014-03-12
| | | | | | | | | | | | | | | | | | | | This patch replaces the raw values with ARRAY_SIZE for assigning the ninput_delays and noutput_delays fields of STiH416's st_pctl_data struct. Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: st: add pinctrl support for the STiH407 SoCGiuseppe Cavallaro2014-03-12
| | | | | | | | | | | | | | | | | | | | | | This patch adds the initial support for pinctrl based on H407 SoC. Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: st: Enhance the controller to manage unavailable registersGiuseppe Cavallaro2014-03-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new logic inside the st pinctrl to manage an unsupported scenario: some sysconfig are not available! This is the case of STiH407 where, although documented, the following registers from SYSCFG_FLASH have been removed from the SoC. SYSTEM_CONFIG3040 Output Enable pad control for all PIO Alternate Functions and SYSTEM_ CONFIG3050 Pull Up pad control for all PIO Alternate Functions Without managing this condition an imprecise external abort will be detect. To do this the patch also reviews the st_parse_syscfgs and other routines to manipulate the registers only if actually available. In any case, for example the st_parse_syscfgs detected an error condition but no action was made in the st_pctl_probe_dt. Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Simplify msm_config_reg() and callersStephen Boyd2014-03-12
| | | | | | | | | | | | | | | | | | | | We don't need to check for a negative reg here because reg is always the same and is always non-negative. Also, collapse the switch statement down for the duplicate cases. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Remove impossible WARN_ON()sStephen Boyd2014-03-12
| | | | | | | | | | | | | | | | | | | | All these functions are limited in what they can pass as the gpio or irq number to whatever is setup during probe. Remove the checks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Replace lookup tables with mathStephen Boyd2014-03-12
| | | | | | | | | | | | | | | | | | We don't need to waste space with these lookup tables, just do the math directly. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Drop OF_IRQ dependencyStephen Boyd2014-03-12
| | | | | | | | | | | | | | | | | | This driver doesn't rely on any functionality living in drivers/of/irq.c to compile. Drop this dependency. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Drop unused includesStephen Boyd2014-03-12
| | | | | | | | | | | | | | | | | | These includes are unused or can be handled via forward declarations. Remove them. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Check for ngpios > MAX_NR_GPIOStephen Boyd2014-03-12
| | | | | | | | | | | | | | | | | | | | Fail the probe and print a warning if SoC specific drivers have more GPIOs than there can be accounted for in the static bitmaps. This should avoid silent corruption/failures in the future. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Silence recursive lockdep warningStephen Boyd2014-03-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a driver calls enable_irq_wake() on a gpio turned interrupt from the msm pinctrl driver we'll get a lockdep warning like so: ============================================= [ INFO: possible recursive locking detected ] 3.14.0-rc3 #2 Not tainted --------------------------------------------- modprobe/52 is trying to acquire lock: (&irq_desc_lock_class){-.....}, at: [<c026aea0>] __irq_get_desc_lock+0x48/0x88 but task is already holding lock: (&irq_desc_lock_class){-.....}, at: [<c026aea0>] __irq_get_desc_lock+0x48/0x88 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&irq_desc_lock_class); lock(&irq_desc_lock_class); *** DEADLOCK *** May be due to missing lock nesting notation 4 locks held by modprobe/52: #0: (&__lockdep_no_validate__){......}, at: [<c04f2864>] __driver_attach+0x48/0x98 #1: (&__lockdep_no_validate__){......}, at: [<c04f2874>] __driver_attach+0x58/0x98 #2: (&irq_desc_lock_class){-.....}, at: [<c026aea0>] __irq_get_desc_lock+0x48/0x88 #3: (&(&pctrl->lock)->rlock){......}, at: [<c04bb4b8>] msm_gpio_irq_set_wake+0x20/0xa8 Silence it by putting the gpios into their own lock class. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mvebu: silence WARN to dev_warnSebastian Hesselbarth2014-03-12
| | | | | | | | | | | | | | | | Pinctrl will WARN on missing DT resources, which is a little bit too noisy. Use dev_warn with FW_BUG instead. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: drop wake_irqs bitmapJosh Cartwright2014-03-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the wake_irqs bitmap is used to track whether there are any gpio's which are configured as wake irqs, and uses this to determine whether or not to call enable_irq_wake()/disable_irq_wake() on the summary interrupt. However, the genirq core already handles this case, by maintaining a 'wake_count' per irq_desc, and only calling into the controlling irq_chip when wake_count transitions 0 <-> 1. Drop this bitmap, and unconditionally call irq_set_irq_wake() on the summary interrupt. Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl-baytrail: add function mux checking in gpio pin requestChew, Kean Ho2014-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | The requested gpio pin must has the func_pin_mux field set to GPIO function by BIOS/FW in advanced. Else, the gpio pin request would fail. This is to ensure that we do not expose any gpio pins which shall be used for alternate functions, for eg: wakeup pin, I/O interfaces for LPSS, etc. Signed-off-by: Chew, Kean Ho <kean.ho.chew@intel.com> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com> Reviewed-by: Darren Hart <dvhart@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: fix some typos and inconsistenciesStephen Warren2014-03-11
| | | | | | | | | | | | | | | | | | | | | | | | drive_dev3_pins in pinctrl-tegra114.c wasn't used; delete it. pinctrl-tegra124.c had quite a few typos. Fix those. pinctrl-tegra124.c had a few mismatches between the *_groups[] ararys and the function lists in tegra124_groups[]. Fix those. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a7791: Add alternative MSIOF pin groupsGeert Uytterhoeven2014-03-04
| | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a7790: Add alternative MSIOF pin groupsGeert Uytterhoeven2014-03-04
| | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge branch 'pinctrl-mvebu' into develLinus Walleij2014-03-03
| |\
| | * Merge tag 'tags/for-mvebu-pinctrl-3xx' into mvebu/pinctrlJason Cooper2014-03-01
| | |\ | | | | | | | | | | | | Sign for-mvebu/pinctrl-3xx
| | | * pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385Thomas Petazzoni2014-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
| | | * pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375Thomas Petazzoni2014-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell Armada 375 is a new ARM SoC from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * | pinctrl: mvebu: dove: use global register regmapSebastian Hesselbarth2014-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a regmap for global registers, get rid of the last remaining hardcoded physical addresses. While at it, also remove DOVE_ prefix from those macros. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| | * | pinctrl: mvebu: dove: use remapped pmu_mpp registersSebastian Hesselbarth2014-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have ioremapped pmu_mpp registers, get rid of hardcoded physical addresses. While at it, also remove DOVE_ prefix from those macros. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| | * | pinctrl: mvebu: dove: use remapped mpp4 registerSebastian Hesselbarth2014-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have an ioremapped mpp4 register, get rid of hardcoded physical addresses. While at it, also remove DOVE_ prefix from those macros. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| | * | pinctrl: mvebu: dove: use remapped mpp base registersSebastian Hesselbarth2014-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have ioremapped mpp base registers, get rid of hardcoded physical addresses. While at it, also remove DOVE_ prefix from those macros. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 03:05:59 -0500