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* Intel IOMMU: IOVA allocation and management routinesKeshavamurthy, Anil S2007-10-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | This code implements a generic IOVA allocation and management. As per Dave's suggestion we are now allocating IO virtual address from Higher DMA limit address rather than lower end address and this eliminated the need to preserve the IO virtual address for multiple devices sharing the same domain virtual address. Also this code uses red black trees to store the allocated and reserved iova nodes. This showed a good performance improvements over previous linear linked list. [akpm@linux-foundation.org: remove inlines] [akpm@linux-foundation.org: coding style fixes] Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Intel IOMMU: PCI generic helper functionKeshavamurthy, Anil S2007-10-22
| | | | | | | | | | | | | | | | | | | | | | | | When devices are under a p2p bridge, upstream transactions get replaced by the device id of the bridge as it owns the PCIE transaction. Hence its necessary to setup translations on behalf of the bridge as well. Due to this limitation all devices under a p2p share the same domain in a DMAR. We just cache the type of device, if its a native PCIe device or not for later use. [akpm@linux-foundation.org: BUG_ON -> WARN_ON+recover] Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Intel IOMMU: DMAR detection and parsing logicKeshavamurthy, Anil S2007-10-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports the upcomming Intel IOMMU hardware a.k.a. Intel(R) Virtualization Technology for Directed I/O Architecture and the hardware spec for the same can be found here http://www.intel.com/technology/virtualization/index.htm FAQ! (questions from akpm, answers from ak) > So... what's all this code for? > > I assume that the intent here is to speed things up under Xen, etc? Yes in some cases, but not this code. That would be the Xen version of this code that could potentially assign whole devices to guests. I expect this to be only useful in some special cases though because most hardware is not virtualizable and you typically want an own instance for each guest. Ok at some point KVM might implement this too; i likely would use this code for this. > Do we > have any benchmark results to help us to decide whether a merge would be > justified? The main advantage for doing it in the normal kernel is not performance, but more safety. Broken devices won't be able to corrupt memory by doing random DMA. Unfortunately that doesn't work for graphics yet, for that need user space interfaces for the X server are needed. There are some potential performance benefits too: - When you have a device that cannot address the complete address range an IOMMU can remap its memory instead of bounce buffering. Remapping is likely cheaper than copying. - The IOMMU can merge sg lists into a single virtual block. This could potentially speed up SG IO when the device is slow walking SG lists. [I long ago benchmarked 5% on some block benchmark with an old MPT Fusion; but it probably depends a lot on the HBA] And you get better driver debugging because unexpected memory accesses from the devices will cause a trappable event. > > Does it slow anything down? It adds more overhead to each IO so yes. This patch: Add support for early detection and parsing of DMAR's (DMA Remapping) reported to OS via ACPI tables. DMA remapping(DMAR) devices support enables independent address translations for Direct Memory Access(DMA) from Devices. These DMA remapping devices are reported via ACPI tables and includes pci device scope covered by these DMA remapping device. For detailed info on the specification of "Intel(R) Virtualization Technology for Directed I/O Architecture" please see http://www.intel.com/technology/virtualization/index.htm Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Cc: Len Brown <lenb@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Get rid of unused variable warning in drivers/pci/hotplug/pci_hotplug_core.cLinus Torvalds2007-10-15
| | | | | | | Commit 5a7ad7f044941316dc98eda2a087a12a7a50649d removed all uses of 'retval', but didn't remove the variable itself. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* more trivial signedness fixes in driversAl Viro2007-10-14
| | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6Linus Torvalds2007-10-12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6: (37 commits) PCI: merge almost all of pci_32.h and pci_64.h together PCI: X86: Introduce and enable PCI domain support PCI: Add 'nodomains' boot option, and pci_domains_supported global PCI: modify PCI bridge control ISA flag for clarity PCI: use _CRS for PCI resource allocation PCI: avoid P2P prefetch window for expansion ROMs PCI: skip ISA ioresource alignment on some systems PCI: remove transparent bridge sizing pci: write file size to inode on proc bus file write pci: use size stored in proc_dir_entry for proc bus files pci: implement "pci=noaer" PCI: fix IDE legacy mode resources MSI: Use correct data offset for 32-bit MSI in read_msi_msg() PCI: Fix incorrect argument order to list_add_tail() in PCI dynamic ID code PCI: i386: Compaq EVO N800c needs PCI bus renumbering PCI: Remove no longer correct documentation regarding MSI vector assignment PCI: re-enable onboard sound on "MSI K8T Neo2-FIR" PCI: quirk_vt82c586_acpi: Omit reading PCI revision ID PCI: quirk amd_8131_mmrbc: Omit reading pci revision ID cpqphp: Use PCI_CLASS_REVISION instead of PCI_REVISION_ID for read ...
| * PCI: Add 'nodomains' boot option, and pci_domains_supported globalJeff Garzik2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * Introduce pci_domains_supported global, hardcoded to zero if !CONFIG_PCI_DOMAINS. * Introduce 'nodomains' boot option, which clears pci_domains_supported on platforms that enable it by default (x86, x86-64, and others when they are converted to use this). Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: modify PCI bridge control ISA flag for clarityGary Hade2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify PCI Bridge Control ISA flag for clarity This patch changes PCI_BRIDGE_CTL_NO_ISA to PCI_BRIDGE_CTL_ISA and modifies it's clarifying comment and locations where used. The change reduces the chance of future confusion since it makes the set/unset meaning of the bit the same in both the bridge control register and bridge_ctl field of the pci_bus struct. Signed-off-by: Gary Hade <garyhade@us.ibm.com> Acked-by: Linas Vepstas <linas@austin.ibm.com> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: avoid P2P prefetch window for expansion ROMsGary Hade2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid creating P2P prefetch window for expansion ROMs Because of the future possibility that P2P prefetch windows will contain address ranges above 4GB some BIOSes are providing space in the P2P non-prefetch windows for expansion ROMs. This is due to expansion ROM BAR 32-bit limitation. When expansion ROM BARs without BIOS assigned address(es) are currently found behind a P2P bridge, the kernel attempts to create a P2P prefetch window for them even though space for them has already been provided in the non-prefetch window. _CRS on some systems with certain resource conservation conscious BIOSes may not provide the extra 1MB or more memory resource needed for the expansion ROM motivated prefetch window causing resource allocation errors. This change corrects the problem by removing IORESOURCE_PREFETCH from the expansion ROM flags initialization. It also removes IORESOURCE_CACHEABLE which seems inappropriate if only non-cacheable memory is available. Signed-off-by: Gary Hade <gary.hade@us.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: skip ISA ioresource alignment on some systemsGary Hade2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Skip ISA ioresource alignment on some systems To conserve limited PCI i/o resource on some IBM multi-node systems, the BIOS allocates (via _CRS) and expects the kernel to use addresses in ranges currently excluded by pcibios_align_resource() [i386/pci/i386.c]. This change allows the kernel to use the currently excluded address ranges on the IBM x3800, x3850, and x3950. Signed-off-by: Gary Hade <gary.hade@us.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: remove transparent bridge sizingGary Hade2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove transparent bridge sizing. Due to code in pci_read_bridge_bases() [drivers/pci/probe.c] the child bus of a transparent bridge already has access to the parent bus resources so transparent bridge sizing appears unnecessary. The bridge sizing includes alignment and granularity adjustments that can cause significantly more memory to be reserved from the parant bus than required by devices on the child bus and allotted by _CRS. Signed-off-by: Gary Hade <gary.hade@us.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pci: write file size to inode on proc bus file writeDavid Rientjes2007-10-12
| | | | | | | | | | | | | | | | | | | | | | When a /proc/bus/pci file is written to, the size of that PCI device's configuration space must be written to the inode. Otherwise, it is possible for the file to specify a size of 0 on stat if a task is holding the same file open. Signed-off-by: David Rientjes <rientjes@google.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pci: use size stored in proc_dir_entry for proc bus filesDavid Rientjes2007-10-12
| | | | | | | | | | | | | | | | | | | | On pci_proc_attach_device(), the size of the PCI configuration space is stored in the proc_dir_entry as the size of the file. Thus, the procfs interface to PCI devices should use it instead of the device directly. Signed-off-by: David Rientjes <rientjes@google.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pci: implement "pci=noaer"Randy Dunlap2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | For cases in which CONFIG_PCIEAER=y (such as distro kernels), allow users to disable PCIE Advanced Error Reporting by using "pci=noaer" on the kernel command line. This can be used to work around hardware or (kernel) software problems. Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: fix IDE legacy mode resourcesYoichi Yuasa2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I got the following error on MIPS Cobalt. PCI: Unable to reserve I/O region #1:8@f00001f0 for device 0000:00:09.1 pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) PCI: Unable to reserve I/O region #3:8@f0000170 for device 0000:00:09.1 pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) pata_via 0000:00:09.1: no available native port The legacy mode IDE resources set the following order. pci_setup_device() Legacy mode ATA controllers have fixed addresses. IDE resources: 0x1F0-0x1F7, 0x3F6, 0x170-0x177, 0x376 | V pcibios_fixup_bus() MIPS Cobalt PCI bus regions have the -0x10000000 offset from PCI resources. pcibios_fixup_bus() fix PCI bus regions. 0x1F0 - 0x10000000 = 0xF00001F0 | V ata_pci_init_one() PCI: Unable to reserve I/O region #1:8@f00001f0 for device 0000:00:09.1 In some architectures, PCI bus regions have the offset from PCI resources. For this reason, pci_setup_device() should set PCI bus regions to dev->resource[]. [akpm@linux-foundation.org: use struct initialiser] Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Greg KH <greg@kroah.com> Cc: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * MSI: Use correct data offset for 32-bit MSI in read_msi_msg()Roland Dreier2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | While reading the MSI code trying to find a reason why MSI wouldn't work for devices that have a 32-bit MSI address capability, I noticed that read_msi_msg() seems to read the message data from the wrong offset in this case. Signed-off-by: Roland Dreier <roland@digitalvampire.org> Acked-by: Eric W. Biederman <ebiederm@xmission.com> Cc: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: Fix incorrect argument order to list_add_tail() in PCI dynamic ID codeMichael Ellerman2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code for dynamically assigning new ids to PCI drivers, store_new_id(), calls list_add_tail() with the list head and new node arguments in reversed order. The result is that every new id written essentially overwrites the previous list of ids. Caught with the help of Rusty's "horribly bad" list_node patch: http://lkml.org/lkml/2007/6/10/10 Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: re-enable onboard sound on "MSI K8T Neo2-FIR"Johannes Goecke2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the "MSI K8T Neo2-FIR" board the BIOS disables the onboard soundcard, if a second PCI soundcard is present. This patch sets the korrect register bit to enable the onboard sound. Removed old code in /drivers/pci/quirks.c that only checks for the PCI-ID and fires on any Board with VIA 8237. New code in /arch/i386/pci/fixup.c checks the DMI-tables and only runs on the specific board. Signed-off-by: Johannes Goecke <goecke@upb.de> Acked-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: quirk_vt82c586_acpi: Omit reading PCI revision IDAuke Kok2007-10-12
| | | | | | | | | | | | Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: quirk amd_8131_mmrbc: Omit reading pci revision IDAuke Kok2007-10-12
| | | | | | | | | | | | | | Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Cc: Peter Oruba <peter.oruba@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * cpqphp: Use PCI_CLASS_REVISION instead of PCI_REVISION_ID for readAuke Kok2007-10-12
| | | | | | | | | | | | | | | | | | | | | | While PCI_CLASS_REVISION and PCI_REVISION_ID are identical, the code here discards the revision content and is only interested in the class number. Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Cc: Krosten Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pci: hotplug: cpqphp: convert to kthread infrastructureChristoph Hellwig2007-10-12
| | | | | | | | | | | | | | Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pci: hotplug: ibmphp: convert to kthreadKristen Carlson Accardi2007-10-12
| | | | | | | | | | | | | | | | | | | | Convert ibmphp to new kthread api Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Cc: Christoph Hellwig <hch@lst.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: is_power_of_2 in drivers/pci/pci.cvignesh babu2007-10-12
| | | | | | | | | | | | | | | | Replacing n & (n - 1) for power of 2 check by is_power_of_2(n) Signed-off-by: vignesh babu <vignesh.babu@wipro.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pciehp: minor cleanups for pciehp_hpc.cKenji Kaneshige2007-10-12
| | | | | | | | | | | | | | | | | | | | Minor cleanups for pciehp_hpc.c. The 80 column rules, removing unnecessary lines, and so on. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pciehp: remove trailing whitespace form pciehp_pci.cKenji Kaneshige2007-10-12
| | | | | | | | | | | | | | | | | | Remove trailing whitespaces from pciehp_pci.c. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pciehp: remove trailing whitespace from pciehp_ctrl.cKenji Kaneshige2007-10-12
| | | | | | | | | | | | | | | | | | Remove trailing whitespaces from pciehp_ctrl.c. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pciehp: remove trailing whitespace from pciehp_core.cKenji Kaneshige2007-10-12
| | | | | | | | | | | | | | | | | | Remove trailing whitespaces from pciehp_core.c. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pciehp: remove trailing whitespace from pciehp_hpc.cKenji Kaneshige2007-10-12
| | | | | | | | | | | | | | | | | | Remove trailing whitespaces from pciehp_hpc.c. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pciehp: remove DBG_XXX_ROUTINEKenji Kaneshige2007-10-12
| | | | | | | | | | | | | | | | | | | | This patch removes DBG_ENTER_ROUTIN, DBG_LEAVE_ROUTINE and related code, which seem no longer needed. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI Hotplug: pciehp: Request control over PCI Express Capability as well as ↵Kristen Carlson Accardi2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | Native hotplug According to the PCI firmware spec (3.0), the OS must claim control over the PCI Express Capability bits in addition to the PCI Express Native Hot Plug feature when executing _OSC. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI Hotplug: pciehp: Dont check bridge control on removeKristen Carlson Accardi2007-10-12
| | | | | | | | | | | | | | | | | | When removing a device with a bridge on it, only read the bridge control register if the adapter is actually present. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pciehp: remove CONFIG_HOTPLUG_PCI_PCIE_POLL_EVENT_MODEKenji Kaneshige2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unnecessary CONFIG_HOTPLUG_PCI_PCIE_EVENT_MODE. The CONFIG_HOTPLUG_PCI_PCIE_POLL_EVENT_MODE option is not needed because polling mechanism can be enabled through 'pciehp_poll_mode' module option. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI Hotplug: cpqphp_ctrl.c: kmalloc + memset conversion to kzallocMariusz Kozlowski2007-10-12
| | | | | | | | | | | | | | | | | | drivers/pci/hotplug/cpqphp_ctrl.c | 79698 -> 79638 (-60 bytes) drivers/pci/hotplug/cpqphp_ctrl.o | 192896 -> 192736 (-160 bytes) Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | sysfs: kill sysfs_update_file()Tejun Heo2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | sysfs_update_file() depends on inode->i_mtime but sysfs iondes are now reclaimable making the reported modification time unreliable. There's only one user (pci hotplug) of this notification mechanism and it reportedly isn't utilized from userland. Kill sysfs_update_file(). Signed-off-by: Tejun Heo <htejun@gmail.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | Drivers: clean up direct setting of the name of a ksetGreg Kroah-Hartman2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | A kset should not have its name set directly, so dynamically set the name at runtime. This is needed to remove the static array in the kobject structure which will be changed in a future patch. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | kobjects: fix up improper use of the kobject name fieldGreg Kroah-Hartman2007-10-12
| | | | | | | | | | | | | | A number of different drivers incorrect access the kobject name field directly. This is not correct as the name might not be in the array. Use the proper accessor function instead.
* | Driver core: change add_uevent_var to use a structKay Sievers2007-10-12
|/ | | | | | | | | | | | | | | | | | This changes the uevent buffer functions to use a struct instead of a long list of parameters. It does no longer require the caller to do the proper buffer termination and size accounting, which is currently wrong in some places. It fixes a known bug where parts of the uevent environment are overwritten because of wrong index calculations. Many thanks to Mathieu Desnoyers for finding bugs and improving the error handling. Signed-off-by: Kay Sievers <kay.sievers@vrfy.org> Cc: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Cc: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* i386: move pciThomas Gleixner2007-10-11
| | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* Fix bogus PCI quirk for e100Benjamin Herrenschmidt2007-09-28
| | | | | | | | | | | | | | | | Linas reported me that some machines were crashing at boot in quirk_e100_interrupt. It appears that this quirk is doing an ioremap directly on a PCI BAR value, which isn't legal and will cause all sorts of bad things to happen on architectures where PCI BARs don't directly match processor bus addresses. This fixes it by using the proper PCI resources instead which is possible since the quirk has been moved by a previous commit to happen late enough for that. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Linas Vepstas <linas@austin.ibm.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* PCI: unhide SMBus on Compaq Deskpro EP 401963-001 motherboardgw.kernel@tnode.com2007-09-11
| | | | | | | | | PCI quirk to unhide SMBus on Compaq Deskpro EP 401963-001 (PCA# 010174) motherboard. Signed-off-by: Greg White <gw.kernel@tnode.com> Acked-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* PCI: remove devinit from pci_read_bridge_basesRalf Baechle2007-09-11
| | | | | | | | | | | | | | | | | | | On MIPS with PCI && !HOTPLUG, I'm currently getting the following modpost warning: MODPOST vmlinux.o WARNING: vmlinux.o(.text+0x1ce128): Section mismatch: reference to .init.text:pci_read_bridge_bases (between 'pcibios_fixup_bus' and 'pcibios_enable_device') On MIPS I have the call chains pci_scan_child_bus -> pcibios_fixup_bus -> pci_read_bridge_bases. pci_scan_child_bus can't be __devinit because it it is an exported symbol, thus pcibios_fixup_bus and pci_read_bridge_bases can't be either. For some reason I don't see this issue on x86; I blame compiler differences. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* Pull events into release branchLen Brown2007-08-25
|\ | | | | | | | | | | | | | | Conflicts: drivers/acpi/video.c Signed-off-by: Len Brown <len.brown@intel.com>
| * ACPI: Schedule /proc/acpi/event for removalLen Brown2007-08-23
| | | | | | | | | | | | | | | | | | | | | | | | Schedule /proc/acpi/event for removal in 6 months. Re-name acpi_bus_generate_event() to acpi_bus_generate_proc_event() to make sure there is no confusion that it is for /proc/acpi/event only. Add CONFIG_ACPI_PROC_EVENT to allow removal of /proc/acpi/event. There is no functional change if CONFIG_ACPI_PROC_EVENT=y Signed-off-by: Len Brown <len.brown@intel.com>
| * ACPI: don't duplicate input events on netlinkZhang Rui2007-08-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous events patch added a netlink event for every user of the legacy /proc/acpi/event interface. However, some users of /proc/acpi/event are really input events, and they already report their events via the input layer. Introduce a new interface, acpi_bus_generate_netlink_event(), which is explicitly called by devices that want to repoprt events via netlink. This allows the input-like events to opt-out of generating netlink events. In summary: events that are sent via netlink: ac/battery/sbs thermal processor thinkpad_acpi dock/bay events that are sent via input layer: button video hotkey thinkpad_acpi hotkey asus_acpi/asus-laptop hotkey sonypi/sonylaptop Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* | acpiphp_ibm: add missing '\n' to error messageJeremy Fitzhardinge2007-08-25
| | | | | | | | | | | | | | | | | | | | | | Add missing \n to error in ibm_find_acpi_device. Signed-off-by: Jeremy Fitzhardinge <jeremy@goop.org> Cc: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Cc: Greg Kroah-Hartman <gregkh@suse.de> Cc: Adrian Bunk <trivial@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Len Brown <len.brown@intel.com>
* | PCI: Run k8t_sound_hostbridge quirk only when neededJean Delvare2007-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The k8t_sound_hostbridge PCI quick fires on my motherboard (Jetway K8M8MS) while it shouldn't: the on-board sound chip is not disabled and is working just fine. Looking at the code, I see that we are running the quirk for two distinct register values (0x88 and 0xc8) and then clear bit 6 (0x40). However value 0x88 already has bit 6 cleared so this is a no-op. This is what happens on my board. Thus I believe that the quirk should only be run for register value 0xc8. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | PCI: disable MSI on RX790Tejun Heo2007-08-22
| | | | | | | | | | | | | | | | | | | | RX790 can't do MSI like its predecessors. Disable MSI on RX790. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | PCI: disable MSI on RD580Tejun Heo2007-08-22
| | | | | | | | | | | | | | | | | | RD580 can't do MSI like its predecessors. Disable MSI on RD580. Signed-off-by: Tejun Heo <teheo@suse.de> CC: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | PCI: disable MSI on RS690Tejun Heo2007-08-22
| | | | | | | | | | | | | | | | | | | | RS690 can't do MSI like its predecessors. Disable MSI on RS690. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Henry Su <henry.su@amd.com> Cc: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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