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path: root/drivers/net/tg3.h
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* tg3: Add link state reporting to UMP firmwareMatt Carlson2008-05-02
| | | | | | | | | | | | | | | | | | | | | All variants of the 5714, 5715, and 5780 offer a feature called the "Universal Management Port". This feature is implemented in firmware and is largely transparent to the driver, except... It turns out that the UMP firmware needs to know the current status of the link. Because the firmware cannot touch the PHY registers while the driver is in control of the device, it needs the driver to report link status changes through an additional handshaking mechanism. Without this handshake, it has been observed in the field that the UMP firmware will not operate correctly. This patch implements the new handshake with the UMP firmware. Since the handshake uses the same mechanism ASF heartbeats use, code was added to detect and wait for completion of a pending previous event. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* tg3: Fix 5761 NVRAM sizesMatt Carlson2008-05-02
| | | | | | | | | | The 5761 NVRAM sizes assigned to the nvram_size member are half as big as they should be. This patch corrects the NVRAM sizes and replaces the hardcoded constants with preprocessor constants for readability. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* tg3: Use constant 500KHz MI clock on adapters with a CPMUMatt Carlson2008-05-02
| | | | | | | | | | | | | | | | | | | | The MI clock is not configured correctly on adapters with the CPMU present. The tg3 driver has code which statically sets the MI clock to be a fraction of the speed at which the core clock is running. However, the CPMU can change the adapter's core clock frequency based on operating conditions. Consequently, the MI will run slow when the core's clock has been slowed down. There is a new 500KHz constant frequency clock available on adapters with a CPMU. This patch removes the static core clock scaling and configures the MI clock to use this new 500KHz clock instead. Running the MI clock at slower speeds will not directly result in data corruption, but it does challenge the PHY read and write routine timeouts. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* tg3: 5701 DMA corruption fixMatt Carlson2008-04-19
| | | | | | | | | | | | | | | | Herbert Xu's commit fb93134dfc2a6e6fbedc7c270a31da03fce88db9, entitled "[TCP]: Fix size calculation in sk_stream_alloc_pskb", has triggered a bug in the 5701 where the 5701 DMA engine will corrupt outgoing packets. This problem only happens when the starting address of the packet matches a certain range of offsets and only when the 5701 is placed downstream of a particular Intel bridge. This patch detects the problematic bridge and if present, readjusts the starting address of the packet data to a dword aligned boundary. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add PHY workaround for 5784Matt Carlson2008-04-04
| | | | | | | | | | | | | | The 5784 B step and newer chips require the PHY DSPs to be fine-tuned based on one-time programmable values stored in the chip. This is essential to achieve optimal PHY operations especially when using long cables. We also need to properly handle the 10Mbit RX bit in the CPMU_CTRL register during PHY reset. Update version to 3.89. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Replace some magic 5704S constantsMatt Carlson2008-01-28
| | | | | | | | | | This patch replaces magic values with preprocessor definitions for the sg_dig_ctrl and sg_dig_status registers. This is preparatory work for the next patch. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Separate requested and actual flow control parametersMatt Carlson2008-01-28
| | | | | | | | | This patch removes the TX and RX flow control flags from tg3_flags and adds two new flow control variables, flowctrl and active_flowctrl. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add A1 revsMatt Carlson2007-11-13
| | | | | | | | | | This patch adds the A1 revision of 5784, 5764, and 5761, and applies all previous bugfixes. In places where the list of devices gets too long, the patch uses a new TG3_FLG3_5761_5784_AX_FIXES flag instead. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Prescaler fixMatt Carlson2007-11-13
| | | | | | | | | | | Internal hardware timers become inaccurate after link events. Clock frequency switches performed by the CPMU fail to adjust timer prescalers. The fix is to detect core clock frequency changes during link events and adjust the timer prescalers accordingly. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Disable GPHY autopowerdownMatt Carlson2007-11-13
| | | | | | | | | | New CPMU devices contend with the GPHY for power management. The GPHY autopowerdown feature is enabled by default in the PHY and thus needs to be disabled after every PHY reset. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Fix nvram selftest failuresMatt Carlson2007-11-13
| | | | | | | | | | | | | Newer devices contain bootcode in the chip's private ROM area. This bootcode is called selfboot. Selfboot can be patched in the device's NVRAM and the patches can have several formats. In one particular format, the checksum calculation needs to be slightly modified. This patch adjusts the NVRAM test code for that case, and add support for the missing formats. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: 5784 / 5764 DMA engine lockup fixMatt Carlson2007-11-13
| | | | | | | | | | 5784 and 5764 devices lock up when the link speed is 10Mbps, the CPMU link speed mode is enabled, and the MAC clock is running at 1.5Mhz. The fix is to run the MAC clock at faster speeds. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: 5784 / 5764 GPHY power down fixMatt Carlson2007-11-13
| | | | | | | | | | | | | | 5784 and 5764 devices fail to link / pass traffic after one load / unload cycle. This happens because of a hardware bug in the new CPMU. During normal operation, the MAC depends on the PHY clock being available. When the PHY is powered down, the clock the MAC depends on is disabled. The fix is to switch the MAC clock to an alternate source before powering down the PHY, and to restore the MAC clock to the PHY source upon device resume. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: PCI command adjustmentMatt Carlson2007-10-22
| | | | | | | | | | | This patch changes the way the driver works with the PCI command register. It adjusts the access size from dwords to words. This patch is done both as a PCI configuration space cleanup and as preparatory work for PCI error recovery. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add management FW version to ethtool reportMatt Carlson2007-10-22
| | | | | | | | | This patch appends the management firmware version to the bootcode firmware string reported through ethtool. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: WOL defaultsMatt Carlson2007-10-10
| | | | | | | | | This patch enables WOL by default if out-of-box WOL is enabled in the NVRAM. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add 5761 supportMatt Carlson2007-10-10
| | | | | | | | | This patch adds rest of the miscellaneous code required to support the 5761. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add 5761 APE supportMatt Carlson2007-10-10
| | | | | | | | | | This patch adds support for the new APE block, present in 5761 chips. APE stands for Application Processing Engine. The primary function of the APE is to process manageability traffic, such as ASF. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add new 5761 NVRAM decode routinesMatt Carlson2007-10-10
| | | | | | | | | This patch adds a new 5761-specific NVRAM strapping decode routine. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add 5784 and 5764 support.Matt Carlson2007-10-10
| | | | | | | | This patch adds the support for 5784 and 5764 devices. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: ASIC decoding and basic CPMU support.Matt Carlson2007-10-10
| | | | | | | | | | | | | Newer products change the way the ASIC revision is obtained. This patch implements how the driver will extract the revision number. This patch also adds preliminary CPMU support. CPMU stands for Central Power Management Unit. The CPMU's role is to put the chip into lower power states when the operating conditions allow it. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Walk PCI capability lists.Matt Carlson2007-10-10
| | | | | | | | | | | Newer tg3 devices shuffle around the registers in PCI configuration space. This patch changes the way the driver accesses the PCI capabilities registers. Hardcoded register locations are replaced with offsets from pci_find_capability() return values. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [NET]: Make NAPI polling independent of struct net_device objects.Stephen Hemminger2007-10-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several devices have multiple independant RX queues per net device, and some have a single interrupt doorbell for several queues. In either case, it's easier to support layouts like that if the structure representing the poll is independant from the net device itself. The signature of the ->poll() call back goes from: int foo_poll(struct net_device *dev, int *budget) to int foo_poll(struct napi_struct *napi, int budget) The caller is returned the number of RX packets processed (or the number of "NAPI credits" consumed if you want to get abstract). The callee no longer messes around bumping dev->quota, *budget, etc. because that is all handled in the caller upon return. The napi_struct is to be embedded in the device driver private data structures. Furthermore, it is the driver's responsibility to disable all NAPI instances in it's ->stop() device close handler. Since the napi_struct is privatized into the driver's private data structures, only the driver knows how to get at all of the napi_struct instances it may have per-device. With lots of help and suggestions from Rusty Russell, Roland Dreier, Michael Chan, Jeff Garzik, and Jamal Hadi Salim. Bug fixes from Thomas Graf, Roland Dreier, Peter Zijlstra, Joseph Fannin, Scott Wood, Hans J. Koch, and Michael Chan. [ Ported to current tree and all drivers converted. Integrated Stephen's follow-on kerneldoc additions, and restored poll_list handling to the old style to fix mutual exclusion issues. -DaveM ] Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Fix msi issue with kexec/kdump.Michael Chan2007-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tina Yang <tina.yang@oracle.com> discovered an MSI related problem when doing kdump. The problem is that the kexec kernel is booted without going through system reset, and as a result, MSI may already be enabled when tg3_init_one() is called. tg3_init_one() calls pci_save_state() which will save the stale MSI state. Later on in tg3_open(), we call pci_enable_msi() to reconfigure MSI on the chip before we reset the chip. After chip reset, we call pci_restore_state() which will put the stale MSI address/data back onto the chip. This is no longer a problem in the latest kernel because pci_restore_state() has been changed to restore MSI state from internal data structures which will guarantee restoring the proper MSI state. But I think we should still fix it. Our save and restore sequence can still cause very subtle problems down the road. The fix is to have our own functions save and restore precisely what we need. We also change it to save and restore state inside tg3_chip_reset() in a more straight forward way. Thanks to Tina for helping to test and debug the problem. [ Bump driver version and release date. -DaveM ] Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add missing NVRAM strapping.Matt Carlson2007-07-11
| | | | | | | | This patch adds a missing NVRAM strapping for 5755 devices. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Enable auto MDI.Matt Carlson2007-07-11
| | | | | | | | | | This patch adds automatic MDI crossover support when autonegotiation is turned off. Automatic MDI crossover allows link to be established without the use of a crossover cable. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* tg3: use flush_work_keventd()Andrew Morton2007-05-09
| | | | | | | | | | | | | | | | | Convert tg3 over to flush_work_keventd(). Remove nasty now-unneeded deadlock avoidance logic. (akpm: bypassed maintainers, sorry. There are other patches which depend on this) Cc: "Maciej W. Rozycki" <macro@linux-mips.org> Cc: David Howells <dhowells@redhat.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Michael Chan <mchan@broadcom.com> Cc: Jeff Garzik <jeff@garzik.org> Cc: Oleg Nesterov <oleg@tv-sign.ru> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [TG3]: Add ASPM workaround.Matt Carlson2007-05-07
| | | | | | | | | | | This patch adds workaround to fix performance problems caused by slow PCIE L1->L0 transitions on ICH8 platforms. Changed all magic numbers to constants as suggested by Jeff Garzik. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add TG3_FLAG_SUPPORT_MSI flag.Michael Chan2007-05-05
| | | | | | | | | | And fix up the code to always allow MSI on 5714 A2. Call tg3_find_peer() earlier because we need that information before we can determine whether we can set TG3_FLAG_SUPPORT_MSI or not. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Eliminate the TG3_FLAG_5701_REG_WRITE_BUG flag.Matt Carlson2007-05-05
| | | | | | | | | | | This patch removes the use of the TG3_FLAG_5701_REG_WRITE_BUG flag. It's logic is only used to set a function pointer and thus the logic can be collapsed and the flag removed. [ Comment tidy by Christoph Hellwig. -DaveM ] Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com>
* [TG3]: Eliminate the TG3_FLAG_GOT_SERDES_FLOWCTL flag.Michael Chan2007-05-05
| | | | | | | This flag does not do anything useful. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: WoL fixes.Gary Zambrano2007-05-05
| | | | | | | | | | Change TG3_FLAG_SERDES_WOL_CAP to TG3_FLAG_WOL_CAP to make it easier to manage WoL. This flag is now used consistently during ethtool WoL setup and power setting changes. Signed-off-by: Gary Zambrano <zambrano@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Exit irq handler during chip reset.Michael Chan2007-03-25
| | | | | | | | | | | | | | | | | | | | | On most tg3 chips, the memory enable bit in the PCI command register gets cleared during chip reset and must be restored before accessing PCI registers using memory cycles. The chip does not generate interrupt during chip reset, but the irq handler can still be called because of irq sharing or irqpoll. Reading a register in the irq handler can cause a master abort in this scenario and may result in a crash on some architectures. Use the TG3_FLAG_CHIP_RESETTING flag to tell the irq handler to exit without touching any registers. The checking of the flag is in the "slow" path of the irq handler and will not affect normal performance. The msi handler is not shared and therefore does not require checking the flag. Thanks to Bernhard Walle <bwalle@suse.de> for reporting the problem. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Eliminate the unused TG3_FLAG_SPLIT_MODE flag.Michael Chan2007-03-25
| | | | | | | | This flag to support multiple PCIX split completions was never used because of hardware bugs. This will make room for a new flag. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: TSO workaround fixes.Michael Chan2007-02-26
| | | | | | | | | | | | | | | | 1. Add race condition check after netif_stop_queue(). tg3_tx() runs without netif_tx_lock and can race with tg3_start_xmit_dma_bug() -> tg3_tso_bug(). 2. Firmware TSO in 5703/5704/5705 also have the same TSO limitation, i.e. they cannot handle TSO headers bigger than 80 bytes. Rename TG3_FL2_HW_TSO_1_BUG to TG3_FL2_TSO_BUG and set this flag on these chips as well. 3. Update version to 3.74. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Use constant for PHY register 0x1e.Michael Chan2007-02-13
| | | | | Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add PHY workaround for 5755M.Michael Chan2007-01-09
| | | | | | | | | | Some PHY trim values need to be fine-tuned on 5755M to be IEEE-compliant. Update version to 3.72. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Power down/up 5906 PHY correctly.Michael Chan2006-12-18
| | | | | | | | The 5906 PHY requires a special register bit to power down and up the PHY. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add TG3_FLG2_IS_NIC flag.Michael Chan2006-12-07
| | | | | | | | | | | Add Tg3_FLG2_IS_NIC flag to unambiguously determine whether the device is NIC or onboard. Previously, the EEPROM_WRITE_PROT flag was overloaded to also mean onboard. With the separation, we can support some devices that are onboard but do not use eeprom write protect. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add 5709 self-test support.Michael Chan2006-09-28
| | | | | Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add 5709 PHY support.Michael Chan2006-09-28
| | | | | | | Add support for the 5709 10/100 PHY. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add basic 5906 support.Michael Chan2006-09-28
| | | | | | | | | Add support for the new 5709 device. This is a new 10/100 Mbps chip. The mailbox access and firmware interface are quite different from all other tg3 chips. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add 5722 and 5756 support.Michael Chan2006-09-28
| | | | | | | Add IDs to support 5722 and 5756. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Improve ASF heartbeat.Michael Chan2006-09-28
| | | | | | | | | | | | | | | | | Change to a different ASF heartbeat message code to improve reliability. There were some reports of unintended resets on real time kernels where the timer may be slow and cause the heartbeat to be late. Netpoll will also have the same problem because the timer irq will be unavailable. Using the new heartbeat code, the ASF firmware will also check the ring condition before resetting the chip when the heartbeat is expiring. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Improve 5704S autoneg.Michael Chan2006-09-28
| | | | | | | | | | Improve 5704S autoneg logic by using a serdes_counter field to keep track of the transient states. This eliminates a 200 msec busy loop in the code. Autoneg will take its course without the driver busy waiting for it to finish. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Fix tx race conditionMichael Chan2006-08-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a subtle race condition between tg3_start_xmit() and tg3_tx() discovered by Herbert Xu <herbert@gondor.apana.org.au>: CPU0 CPU1 tg3_start_xmit() if (tx_ring_full) { tx_lock tg3_tx() if (!netif_queue_stopped) netif_stop_queue() if (!tx_ring_full) update_tx_ring netif_wake_queue() tx_unlock } Even though tx_ring is updated before the if statement in tg3_tx() in program order, it can be re-ordered by the CPU as shown above. This scenario can cause the tx queue to be stopped forever if tg3_tx() has just freed up the entire tx_ring. The possibility of this happening should be very rare though. The following changes are made: 1. Add memory barrier to fix the above race condition. 2. Eliminate the private tx_lock altogether and rely solely on netif_tx_lock. This eliminates one spinlock in tg3_start_xmit() when the ring is full. 3. Because of 2, use netif_tx_lock in tg3_tx() before calling netif_wake_queue(). 4. Change TX_BUFFS_AVAIL to an inline function with a memory barrier. Herbert and David suggested using the memory barrier instead of volatile. 5. Check for the full wake queue condition before getting netif_tx_lock in tg3_tx(). This reduces the number of unnecessary spinlocks when the tx ring is full in a steady-state condition. 6. Update version to 3.65. Signed-off-by: Michael Chan <mchan@broadcom.com> Acked-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add TSO workaround using GSOMichael Chan2006-06-30
| | | | | | | | | | | | | | | | | Use GSO to workaround a rare TSO bug on some chips. This hardware bug may be triggered when the TSO header size is greater than 80 bytes. When this condition is detected in a TSO packet, the driver will use GSO to segment the packet to workaround the hardware bug. Thanks to Juergen Kreileder <jk@blackdown.de> for reporting the problem and collecting traces to help debug the problem. And thanks to Herbert Xu <herbert@gondor.apana.org.au> for providing the GSO mechanism that happens to be the perfect workaround for this problem. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Turn on hw fix for ASF problemsMichael Chan2006-06-30
| | | | | | | Clear a bit to enable a hardware fix for some ASF related problem. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add rx BD workaroundMichael Chan2006-06-30
| | | | | | | | | Add workaround to limit the burst size of rx BDs being DMA'ed to the chip. This works around hardware errata on a number of 5750, 5752, and 5755 chips. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Convert to non-LLTXMichael Chan2006-06-18
| | | | | | | | | | | | | | | | | | Herbert Xu pointed out that it is unsafe to call netif_tx_disable() from LLTX drivers because it uses dev->xmit_lock to synchronize whereas LLTX drivers use private locks. Convert tg3 to non-LLTX to fix this issue. tg3 is a lockless driver where hard_start_xmit and tx completion handling can run concurrently under normal conditions. A tx_lock is only needed to prevent netif_stop_queue and netif_wake_queue race condtions when the queue is full. So whether we use LLTX or non-LLTX, it makes practically no difference. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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