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| * mmc: wmt-sdmmc: Simplify wmt_set_sd_power implementationAxel Lin2013-10-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the code to set/clear BM_SD_OFF bit: | power_inverted: 0 | power_inverted: 1 ------------------------------------------------- enable: 0 | SET BM_SD_OFF | CLEAR BM_SD_OFF ------------------------------------------------- enable: 1 | CLEAR BM_SD_OFF | SET BM_SD_OFF Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci-pci: add Intel Merrifield supportDavid Cohen2013-10-21
| | | | | | | | | | | | | | | | Implement initial SDHCI Intel Merrifield support. This patch is based on previous one from Yunpeng Gao <yunpeng.gao@intel.com>. Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci-esdhc-imx: set actual_clock in clock settingDong Aisheng2013-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables access the actual_clock via sys. root@imx6qsabreauto:~# cat /sys/kernel/debug/mmc0/ios clock: 198000000 Hz actual clock: 198000000 Hz vdd: 17 (2.9 ~ 3.0 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 2 (4 bits) timing spec: 6 (sd uhs SDR104) signal voltage: 0 (1.80 V) Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci-esdhc-imx: correct pre_div for imx6qDong Aisheng2013-09-26
| | | | | | | | | | | | | | | | | | | | | | | | According to spec, the pre_div for imx6q should be 1, or the biggest clock rate we can get is a half of host clock rate. This may cause we can not get the proper clock rate as we want. e.g. if the desired clock is 200Mhz, however, the host clock is 200Mhz too, then it causes the actual clock we get is 100Mhz due to pre_div is 2. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci-esdhc-imx: change pinctrl state according to uhs modeDong Aisheng2013-09-26
| | | | | | | | | | | | | | | | | | | | | | | | | | Without proper pinctrl state, the card may not be able to work on high speed stablely. e.g. SDR104. This patch add pinctrl state switch code according to different uhs mode include 100mhz sate, 200mhz sate and normal state (50Mhz and below). Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci-esdhc-imx: add sd3.0 SDR clock tuning supportDong Aisheng2013-09-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale i.MX6Q/DL uSDHC clock tuning progress is a little different from the standard tuning process defined in host controller spec v3.0. Thus we use platform_execute_tuning instead of standard sdhci tuning. The main difference are: 1) not only generate Buffer Read Ready interrupt when tuning is performing. It generates all other DATA interrupts like the normal data command. 2) SDHCI_CTRL_EXEC_TUNING is not automatically cleared by HW, instead it's controlled by SW. 3) SDHCI_CTRL_TUNED_CLK is not automatically set by HW, it's controlled by SW. 4) the clock delay for every tuning is set by SW. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci-esdhc-imx: support real clock on and off for imx6qDong Aisheng2013-09-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The signal voltage switch flow requires to shutdown and output clock in a specific sequence according to standard host controller v3.0 spec. In that timing, the card must really receive clock or not. However, for i.MX6Q, the uSDHC will not output clock even the clock is enabled until there is command or data in transfer on the bus, which will then cause singal voltage switch always to fail. For i.MX6Q, we clear ESDHC_VENDOR_SPEC_FRC_SDCLK_ON bit to let controller to gate off clock automatically and set that bit to force clock output if clock is on. This is required by SD3.0 support. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci-esdhc: move common esdhc_set_clock to platform driverDong Aisheng2013-09-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need a lot of imx6 specific things into common esdhc_set_clock for support SD3.0 and eMMC DDR mode which is not needed for power pc platforms, so esdhc_set_clock seems not so common anymore. Instead of keeping add platform specfics things into this common API, we choose to move that code into platform driver itself to handle. This can also exclude the dependency between imx and power pc on this headfile and is easy for maintain in the future. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci: allow platform access of sdhci_send_commandDong Aisheng2013-09-26
| | | | | | | | | | | | | | | | It helps for platform code to use it send tuning commands. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci: add hooks for platform specific tuningDong Aisheng2013-09-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tuning of some platforms may not follow the standard host control spec v3.0, e.g. Freescale uSDHC on i.MX6Q/DL. Add a hook here to allow execute platform specific tuning instead of standard host controller tuning. The hook only replaces the tuning process, so it's placed after tuning checking and before the real tuning process. Some notes for the tuning hook: 1) it needs handle lock itself if it wants to access host controller according platform specific implementation. 2) do not need to handle runtime pm since it executes with runtime pm get already. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci-bcm2835: Use sdhci_pltfm_unregister instead of open codedAxel Lin2013-09-25
| | | | | | | | | | | | | | | | This avoid duplicated implementation. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci-bcm-kona: Use sdhci_pltfm_unregister instead of open codedAxel Lin2013-09-25
| | | | | | | | | | | | | | | | | | | | | | This avoid duplicated implementation and also fixes missing iounmap() and release_mem_region() calls in sdhci_bcm_kona_remove(). sdhci_pltfm_init() calls request_mem_region() and ioremap(), thus we need to call the corresponding iounmap() and release_mem_region() calls in sdhci_bcm_kona_remove(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc-socfpga: Staticize dw_mci_socfpga_probeSachin Kamat2013-09-25
| | | | | | | | | | | | | | | | 'dw_mci_socfpga_probe' is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc-socfpga: Remove redundant of_match_ptrSachin Kamat2013-09-25
| | | | | | | | | | | | | | | | | | 'dw_mci_socfpga_match' is always compiled in. Hence of_match_ptr is not necessary. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: mvsdio: Convert to devm_ioremap_resourceSachin Kamat2013-09-25
| | | | | | | | | | | | | | | | devm_request_and_ioremap() is deprecated. Use devm_ioremap_resource() instead. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: core: clean up duplicate macrosJackey Shen2013-09-25
| | | | | | | | | | | | | | | | | | Clean up the duplicate macros: mmc_sd_card_uhs -> mmc_card_uhs mmc_sd_card_set_uhs -> mmc_card_set_uhs Signed-off-by: Jackey Shen <jackey.shen@amd.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: atmel-mci: fix oops in atmci_tasklet_funcRodolfo Giometti2013-09-25
| | | | | | | | | | | | | | | | | | | | | | In some cases, a NULL pointer dereference happens because data is NULL when STATE_END_REQUEST case is reached in atmci_tasklet_func. Cc: <stable@vger.kernel.org> # 3.9+ Signed-off-by: Rodolfo Giometti <giometti@enneenne.com> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: atmel-mci: abort transfer on timeout errorLudovic Desroches2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | When a software timeout occurs, the transfer is not stopped. In DMA case, it causes DMA channel to be stuck because the transfer is still active causing following transfers to be queued but not computed. Cc: <stable@vger.kernel.org> # 3.9+ Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Reported-by: Alexander Morozov <etesial@gmail.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: fix the transfer termination in IDMAC modeSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In IDMAC mode EVENT_XFER_COMPLETE is set when RI/TI of last descriptor is done. So if errors are happened in the middle of data transfers, 'dw_mci_stop_dma' during error handing can be called and eventually prevents this flag to be set. This results in permanent wait for EVENT_XFER_COMPLETE in 'dw_mci_tasklet_func'. Therefore, if dma running is stopped forcibly, EVENT_XFER_COMPLETE should be set. Reported-by: Bing Zhao <bzhao@marvell.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: amend use of idmac sw resetSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | | | | | First, compiling warning along with previous change is removed. [drivers/mmc/host/dw_mmc.c:1890:7: warning: unused variable 'ctrl'] And with the recommendation in manual, IDMAC software reset is followed by dma-reset of the CTRL register in order to terminate the transfer. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: gather each reset code into functionsSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | | | | | There are three resets in CTRL register. FIFO reset is especially used in several points with the same routine. It could be replaced with one function and the others may be applied similarly if needed. So, mci_wait_reset() is modified to allow various bit field of reset. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: rework the code related to cmd/data completionSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | Main change corresponds to dw_mci_command_complete(). And EBE is divided into read and write. Some minor changes for code readability. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: guarantee stop-abort cmd in data errorsSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | In error cases, DTO interrupt may or may not be generated depending on remained data. Stop/Abort command ensures DTO generation for that situation. Currently if 'stop' field of data is empty, there is no stop/abort command. So, it could hang waiting DTO. This change reinforces these cases. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: fix error handling on response errorSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even if response error is detected in case data command, data transfer is continued. It means that data can live in FIFO. Current handling just breaks out the request when seeing the command error. This causes kernel panic in dw_mci_read_data_pio() [host->data = NULL]. And also, FIFO should be guaranteed to be empty. Unable to handle kernel NULL pointer dereference at virtual address 00000018 <...> [<c02af814>] (dw_mci_read_data_pio+0x68/0x198) from [<c02b04b4>] (dw_mci_interrupt+0x374/0x3a0) [<c02b04b4>] (dw_mci_interrupt+0x374/0x3a0) from [<c006b094>] (handle_irq_event_percpu+0x50/0x194) [<c006b094>] (handle_irq_event_percpu+0x50/0x194) from [<c006b214>] (handle_irq_event+0x3c/0x5c) [<c006b214>] (handle_irq_event+0x3c/0x5c) from [<c006de1c>] (handle_fasteoi_irq+0xa4/0x148) [<c006de1c>] (handle_fasteoi_irq+0xa4/0x148) from [<c006aa88>] (generic_handle_irq+0x20/0x30) [<c006aa88>] (generic_handle_irq+0x20/0x30) from [<c000f154>] (handle_IRQ+0x38/0x90) [<c000f154>] (handle_IRQ+0x38/0x90) from [<c00085bc>] (gic_handle_irq+0x34/0x68) [<c00085bc>] (gic_handle_irq+0x34/0x68) from [<c0011f40>] (__irq_svc+0x40/0x70) Exception stack(0xef0b1c00 to 0xef0b1c48) 1c00: 000eb0cf ffffffff 00001300 c01a7738 ef295e10 0000000a c04df298 ef0b1dc0 1c20: ef295ec0 00000000 00000000 00000006 00000000 ef0b1c48 c02b1274 c01a7764 1c40: 20000113 ffffffff [<c0011f40>] (__irq_svc+0x40/0x70) from [<c01a7764>] (__loop_delay+0x0/0xc) Code: e1a00005 e0891006 e0662004 e12fff33 (e59a3018) ---[ end trace a7043b9ba9aed1db ]--- Kernel panic - not syncing: Fatal exception in interrupt Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: control card read thresholdSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | | | | | Card Read Threshold should be ensured that the card clock does not stop in the middle of a block of data being transferred from the card to the Host. Specially, clock stop is allowed in fast transfer such as HS200 or SDR104 mode. And so, it should be enabled. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: adjust the fifoth with block sizeSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | | | This change helps to choose msize, rx_watermark and tx_watermark depending on block size for IDMAC mode. For SDIO block size can be variable, so if these values are set incorrectly, card clock may stop. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: set the supported max/min frequencySeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Both f_max and f_min will be informed for core layer to request valid clock rate. But current setting from 'host->bus_hz' may not represent the max/min frequency properly. Even if host can actually support high speed than bus_hz, core layer will not request clock rate over bus_hz. Basically, f_max/f_min can be set with the values according to spec. And then host will make its best effort to meet the rate. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: move supports-highspeed of quirks to capsSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | 'supports-highspeed' is not one of the quirks but is a capability. So, it's removed from quirks. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: add the capability to support hs200 modeSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | As host controller can support eMMC's HS200 mode at 1.8V or 1.2V, these capability will be added. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: exynos: adjust the clock rate with speed modeSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | Exynos's host has divider logic before 'cclk_in' to controller core. It means that actual clock rate of ciu clock comes from this divider value. So, source clock should be adjusted along with 'ciu_div' which indicates the host's divider ratio. Setting clock rate basically fits the required speed. Specially, 'cclk_in' should have double rate of target speed in case of DDR 8-bit mode. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: exynos: add variable delay tuning sequenceSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | Implements variable delay tuning. In this change, exynos host can determine the correct sampling point for the HS200 and SDR104 speed mode. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: add support tuning schemeSeungwon Jeon2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | For the speed modes HS200 and SDR104, tuning is needed to determine the correct sampling point. Actual tuning procedure is provided by specific host controller driver. This patch defines the tuning command and tuning data. Additionally, 'struct dw_mci_slot' is moved to header file to consider the extensive usages in driver. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: exynos: configure SMU in exynos5420Yuvaraj Kumar C D2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | Exynos5420 Mobile Storage Host controller has Security Management Unit (SMU) for channel 0 and channel 1 (mainly for eMMC). This time, SMU configuration is set for non-encryption mode. Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: move the platform specific init callYuvaraj Kumar C D2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | Current platform specific private data initialization call dw_mci_exynos_priv_init() can be used to do platform specific initialization of SMU and others in future. So the drv_data->init call has moved to dw_mci_probe(). Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: socfpga: move socfpga private initYuvaraj Kumar C D2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently platform specific private data initialization is done by dw_mci_socfpga_priv_init and dw_mci_socfpga_parse_dt. As we already have separate platform specific device tree parser dw_mci_socfpga_parse_dt, move the dw_mci_socfpga_priv_init code to dw_mci_socfpga_parse_dt. We can use the dw_mci_socfpga_priv_init to do some actual platform specific initialization. Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: exynos: move the exynos private initYuvaraj Kumar C D2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently platform specific private data initialization is done by dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt. As we already have separate platform specific device tree parser dw_mci_exynos_parse_dt, move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt. We can use the dw_mci_exynos_priv_init to do some actual platform specific initialization of SMU and etc. Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: Set timeout to max upon resumeDoug Anderson2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The TMOUT register is set to 0xffffffff at probe time but isn't set after suspend/resume. Add an init of this value. No problems were observed without this (it will also be set in __dw_mci_start_request if there is data to send), but it makes the register dump before and after suspend cleaner. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: Honor requests to set the clock to 0Doug Anderson2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the dw_mmc driver would ignore any requests to disable the card's clock. This doesn't seem like a good thing in general, but had one extra bad side effect in the following situation: * mmc core would set clk to 400kHz at boot time while scanning * mmc core would set clk to 0 since no card, but it would be ignored. * suspend to ram and resume; clocks in the dw_mmc IP block are now 0 but dw_mmc thinks that they're 400kHz (it ignored the set to 0). * insert card * mmc core would set clk to 400kHz which would be considered a no-op. Note that if there is no card in the slot and we do a suspend/resume cycle, we _do_ still end up with differences in a dw_mmc register dump, but the differences are clock related and we've got the clock disabled both before and after, so this should be OK. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INTDoug Anderson2013-09-25
| | | | | | | | | | | | | | | | | | | | | | If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up looping around forever. This has been seen to happen on exynos5420 silicon despite the fact that we haven't enabled any wakeup events due to a silicon errata. It is safe to do on all exynos variants. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: dw_mmc: don't queue up a card detect at slot startupDoug Anderson2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MMC subsystem handles looking for a card at probe time. Queuing up our own can race with the rest of the MMC subsystem and cause problems if we get unlucky with timing. Just remove driver own detection triggering. While progressing the request from 'mmc_rescan', if 'dw_mci_work_routine_card' routine is activated, it will cancel the current request. The problem case is that 'mmc_rescan' is prior to 'dw_mci_work_routine_card' from host own. Specifically, the following message shows the detection problem in driver's probing. It would get an err -123 (-ENOMEDIUM) during probe. [ 4.216595] dwmmc_exynos 12210000.dwmmc1: Using internal DMA controller. [ 4.395935] dwmmc_exynos 12210000.dwmmc1: Version ID is 250a [ 4.401948] dwmmc_exynos 12210000.dwmmc1: DW MMC controller at irq 108, 64 bit host data width, 64 deep fifo [ 4.424430] dwmmc_exynos 12210000.dwmmc1: sdr0 mode (irq=108, width=0) [ 4.453975] dwmmc_exynos 12210000.dwmmc1: sdr0 mode (irq=108, width=0) [ 4.459592] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 400000Hz, actual 400000HZ div = 125) [ 4.484258] dwmmc_exynos 12210000.dwmmc1: 1 slots initialized [ 4.485406] dwmmc_exynos 12210000.dwmmc1: sdr0 mode (irq=108, width=0) [ 4.487606] dwmmc_exynos 12210000.dwmmc1: sdr0 mode (irq=108, width=0) [ 4.489794] dwmmc_exynos 12210000.dwmmc1: sdr0 mode (irq=108, width=0) [ 4.509757] mmc1: error -123 whilst initialising SDIO card Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* | Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds2013-11-13
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM updates from Russell King: "Included in this series are: 1. BE8 (modern big endian) changes for ARM from Ben Dooks 2. big.Little support from Nicolas Pitre and Dave Martin 3. support for LPAE systems with all system memory above 4GB 4. Perf updates from Will Deacon 5. Additional prefetching and other performance improvements from Will. 6. Neon-optimised AES implementation fro Ard. 7. A number of smaller fixes scattered around the place. There is a rather horrid merge conflict in tools/perf - I was never notified of the conflict because it originally occurred between Will's tree and other stuff. Consequently I have a resolution which Will forwarded me, which I'll forward on immediately after sending this mail. The other notable thing is I'm expecting some build breakage in the crypto stuff on ARM only with Ard's AES patches. These were merged into a stable git branch which others had already pulled, so there's little I can do about this. The problem is caused because these patches have a dependency on some code in the crypto git tree - I tried requesting a branch I can pull to resolve these, and all I got each time from the crypto people was "we'll revert our patches then" which would only make things worse since I still don't have the dependent patches. I've no idea what's going on there or how to resolve that, and since I can't split these patches from the rest of this pull request, I'm rather stuck with pushing this as-is or reverting Ard's patches. Since it should "come out in the wash" I've left them in - the only build problems they seem to cause at the moment are with randconfigs, and since it's a new feature anyway. However, if by -rc1 the dependencies aren't in, I think it'd be best to revert Ard's patches" I resolved the perf conflict roughly as per the patch sent by Russell, but there may be some differences. Any errors are likely mine. Let's see how the crypto issues work out.. * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (110 commits) ARM: 7868/1: arm/arm64: remove atomic_clear_mask() in "include/asm/atomic.h" ARM: 7867/1: include: asm: use 'int' instead of 'unsigned long' for 'oldval' in atomic_cmpxchg(). ARM: 7866/1: include: asm: use 'long long' instead of 'u64' within atomic.h ARM: 7871/1: amba: Extend number of IRQS ARM: 7887/1: Don't smp_cross_call() on UP devices in arch_irq_work_raise() ARM: 7872/1: Support arch_irq_work_raise() via self IPIs ARM: 7880/1: Clear the IT state independent of the Thumb-2 mode ARM: 7878/1: nommu: Implement dummy early_paging_init() ARM: 7876/1: clear Thumb-2 IT state on exception handling ARM: 7874/2: bL_switcher: Remove cpu_hotplug_driver_{lock,unlock}() ARM: footbridge: fix build warnings for netwinder ARM: 7873/1: vfp: clear vfp_current_hw_state for dying cpu ARM: fix misplaced arch_virt_to_idmap() ARM: 7848/1: mcpm: Implement cpu_kill() to synchronise on powerdown ARM: 7847/1: mcpm: Factor out logical-to-physical CPU translation ARM: 7869/1: remove unused XSCALE_PMU Kconfig param ARM: 7864/1: Handle 64-bit memory in case of 32-bit phys_addr_t ARM: 7863/1: Let arm_add_memory() always use 64-bit arguments ARM: 7862/1: pcpu: replace __get_cpu_var_uses ARM: 7861/1: cacheflush: consolidate single-CPU ARMv7 cache disabling code ...
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| | \
| *-. \ Merge branches 'fixes', 'mmci' and 'sa11x0' into for-nextRussell King2013-11-12
| |\ \ \ | | | |/ | | |/|
| | | * ARM: 7834/1: mmc: mmci: Save and restore register contextUlf Hansson2013-09-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a corresponding power domain exists for the device and it manages to cut the domain regulator while the device is runtime suspended, the IP loses it's registers context. We restore the context in the .runtime_resume callback from the existing register caches to adapt to this situation. We also want to make sure the registers are in a known state while restoring context in the case when the power domain did not drop the power, since there are restrictions for the order of writing to these registers. To handle this, we clear the registers in the .runtime_suspend callback. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rickard Andersson <rickard.andersson@stericsson.com> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: 7833/1: mmc: mmci: Adapt to register write restrictionsUlf Hansson2013-09-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After a write to the MMCICLOCK register data cannot be written to this register for three feedback clock cycles. Writes to the MMCIPOWER register must be separated by three MCLK cycles. Previously no issues has been observered, but using higher ARM clock frequencies on STE- platforms has triggered this problem. The MMCICLOCK register is written to in .set_ios and for some data transmissions for SDIO. We do not need a delay at the data transmission path, because sending and receiving data will require more than three clock cycles. Then we use a simple logic to only delay in .set_ios and thus we don't affect throughput performance. Signed-off-by: Johan Rudholm <jrudholm@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rickard Andersson <rickard.andersson@stericsson.com> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: 7832/1: mmc: mmci: Use optional sleep pinctrl stateUlf Hansson2013-09-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By optionally putting the pins into sleep state in the .runtime_suspend callback we can accomplish two things. One is to minimize current leakage from pins and thus save power, second we can prevent the IP from driving pins output in an uncontrolled manner, which may happen if the power domain drops the domain regulator. When returning from idle, entering .runtime_resume callback, the pins are restored to default state. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rickard Andersson <rickard.andersson@stericsson.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: 7831/1: mmc: mmci: Adapt to new pinctrl handlingUlf Hansson2013-09-19
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need for every driver to fetch a pinctrl handle and to select the default state. Instead this is handled by the device driver core, thus we can remove this piece of code from mmci. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge branch 'for-linus-dma-masks' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds2013-11-13
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull DMA mask updates from Russell King: "This series cleans up the handling of DMA masks in a lot of drivers, fixing some bugs as we go. Some of the more serious errors include: - drivers which only set their coherent DMA mask if the attempt to set the streaming mask fails. - drivers which test for a NULL dma mask pointer, and then set the dma mask pointer to a location in their module .data section - which will cause problems if the module is reloaded. To counter these, I have introduced two helper functions: - dma_set_mask_and_coherent() takes care of setting both the streaming and coherent masks at the same time, with the correct error handling as specified by the API. - dma_coerce_mask_and_coherent() which resolves the problem of drivers forcefully setting DMA masks. This is more a marker for future work to further clean these locations up - the code which creates the devices really should be initialising these, but to fix that in one go along with this change could potentially be very disruptive. The last thing this series does is prise away some of Linux's addition to "DMA addresses are physical addresses and RAM always starts at zero". We have ARM LPAE systems where all system memory is above 4GB physical, hence having DMA masks interpreted by (eg) the block layers as describing physical addresses in the range 0..DMAMASK fails on these platforms. Santosh Shilimkar addresses this in this series; the patches were copied to the appropriate people multiple times but were ignored. Fixing this also gets rid of some ARM weirdness in the setup of the max*pfn variables, and brings ARM into line with every other Linux architecture as far as those go" * 'for-linus-dma-masks' of git://git.linaro.org/people/rmk/linux-arm: (52 commits) ARM: 7805/1: mm: change max*pfn to include the physical offset of memory ARM: 7797/1: mmc: Use dma_max_pfn(dev) helper for bounce_limit calculations ARM: 7796/1: scsi: Use dma_max_pfn(dev) helper for bounce_limit calculations ARM: 7795/1: mm: dma-mapping: Add dma_max_pfn(dev) helper function ARM: 7794/1: block: Rename parameter dma_mask to max_addr for blk_queue_bounce_limit() ARM: DMA-API: better handing of DMA masks for coherent allocations ARM: 7857/1: dma: imx-sdma: setup dma mask DMA-API: firmware/google/gsmi.c: avoid direct access to DMA masks DMA-API: dcdbas: update DMA mask handing DMA-API: dma: edma.c: no need to explicitly initialize DMA masks DMA-API: usb: musb: use platform_device_register_full() to avoid directly messing with dma masks DMA-API: crypto: remove last references to 'static struct device *dev' DMA-API: crypto: fix ixp4xx crypto platform device support DMA-API: others: use dma_set_coherent_mask() DMA-API: staging: use dma_set_coherent_mask() DMA-API: usb: use new dma_coerce_mask_and_coherent() DMA-API: usb: use dma_set_coherent_mask() DMA-API: parport: parport_pc.c: use dma_coerce_mask_and_coherent() DMA-API: net: octeon: use dma_coerce_mask_and_coherent() DMA-API: net: nxp/lpc_eth: use dma_coerce_mask_and_coherent() ...
| * | | DMA-API: mmc: sdhci-acpi: use dma_coerce_mask_and_coherent()Russell King2013-10-31
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | The code sequence: dev->dma_mask = &dev->coherent_dma_mask; dev->coherent_dma_mask = dma_mask; bypasses the architectures check on the DMA mask. It can be replaced with dma_coerce_mask_and_coherent(), avoiding the direct initialization of this mask. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge 3.12-rc6 into driver-core-nextGreg Kroah-Hartman2013-10-19
|\ \ \ | | |/ | |/| | | | | | | | | | We want these fixes here too. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * | ARM: shmobile: update SDHI DT compatibility string to the <unit>-<soc> formatGuennadi Liakhovetski2013-09-21
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Currently DT compatibility strings of both types can be found in the kernel sources: <unit>-<soc> and <soc>-<unit>, whereas a unique format should be followed and the former one is preferred. This patch converts the SDHI MMC driver and its users to the common standard. This is safe for now, since ATM no real products are using this driver with DT. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: Chris Ball <cjb@laptop.org> [Removed r8a7740.dtsi portion as it is not applicable] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-02 16:13:32 -0400