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* Merge tag 'omapdss-for-3.10' of git://gitorious.org/linux-omap-dss2/linux ↵Dave Airlie2013-04-15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next Omapdss patches for 3.10 merge window The biggest changes are: * DSI video mode: automatic clock and timing calculation * Lots of platform data related panel driver cleanups, to prepare for DT * tag 'omapdss-for-3.10' of git://gitorious.org/linux-omap-dss2/linux: (69 commits) drm/omap: add statics to a few structs drm/omap: Fix and improve crtc and overlay manager correlation drm/omap: Take a fb reference in omap_plane_update() drm/omap: Make fixed resolution panels work drm/omap: fix modeset_init if a panel doesn't satisfy omapdrm requirements OMAPDSS: DPI: widen the pck search when using dss fck OMAPDSS: fix dss_fck clock rate rounding omapdss: use devm_clk_get() OMAPDSS: nec-nl8048 panel: Use dev_pm_ops OMAPDSS: DISPC: Revert to older DISPC Smart Standby mechanism for OMAP5 OMAPDSS: DISPC: Configure doublestride for NV12 when using 2D Tiler buffers omapdss: Features: Fix some parameter ranges omapdss: DISPC: add max pixel clock limits for LCD and TV managers OMAPDSS: DSI: Use devm_clk_get() drivers: video: omap2: dss: Use PTR_RET function OMAPDSS: VENC: remove platform_enable/disable calls OMAPDSS: n8x0 panel: remove use of platform_enable/disable OMAPDSS: n8x0 panel: handle gpio data in panel driver OMAPDSS: picodlp panel: remove platform_enable/disable callbacks OMAPDSS: picodlp panel: handle gpio data in panel driver ...
| * drm/omap: add statics to a few structsTomi Valkeinen2013-04-11
| | | | | | | | | | | | Some static structs are not marked as static. Add it. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
| * drm/omap: Fix and improve crtc and overlay manager correlationArchit Taneja2013-04-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omapdrm driver currently takes a config/module arg to figure out the number of crtcs it needs to create. We could create as many crtcs as there are overlay managers in the DSS hardware, but we don't do that because each crtc eats up one DSS overlay, and that reduces the number of planes we can attach to a single crtc. Since the number of crtcs may be lesser than the number of hardware overlay managers, we need to figure out which overlay managers to use for our crtcs. The current approach is to use pipe2chan(), which returns a higher numbered manager for the crtc. The problem with this approach is that it assumes that the overlay managers we choose will connect to the encoders the platform's panels are going to use, this isn't true, an overlay manager connects only to a few outputs/encoders, and choosing any overlay manager for our crtc might lead to a situation where the encoder cannot connect to any of the crtcs we have chosen. For example, an omap5-panda board has just one hdmi output. If num_crtc is set to 1, with the current approach, pipe2chan will pick up the LCD2 overlay manager, which cannot connect to the hdmi encoder at all. The only manager that could have connected to hdmi was the TV overlay manager. Therefore, there is a need to choose our overlay managers keeping in mind the panels we have on that platform. The new approach iterates through all the available panels, creates encoders and connectors for them, and then tries to get a suitable overlay manager to create a crtc which can connect to the encoders. We use the dispc_channel field in omap_dss_output to retrieve the desired overlay manager's channel number, we then check whether the manager had already been assigned to a crtc or not. If it was already assigned to a crtc, we assume that out of all the encoders which intend use this crtc, only one will run at a time. If the overlay manager wan't assigned to a crtc till then, we create a new crtc and link it with the overlay manager. This approach just looks for the best dispc_channel for each encoder. On DSS HW, some encoders can connect to multiple overlay managers. Since we don't try looking for alternate overlay managers, there is a greater possibility that 2 or more encoders end up asking for the same crtc, causing only one encoder to run at a time. Also, this approach isn't the most optimal one, it can do either good or bad depending on the sequence in which the panels/outputs are parsed. The optimal way would be some sort of back tracking approach, where we improve the set of managers we use as we iterate through the list of panels/encoders. That's something left for later. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
| * drm/omap: Take a fb reference in omap_plane_update()Archit Taneja2013-04-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When userspace calls SET_PLANE ioctl, drm core takes a reference of the fb and passes control to the update_plane op defined by the drm driver. In omapdrm, we have a worker thread which queues framebuffers objects received from update_plane and displays them at the appropriate time. It is possible that the framebuffer is destoryed by userspace between the time of calling the ioctl and apply-worker being scheduled. If this happens, the apply-worker holds a pointer to a framebuffer which is already destroyed. Take an extra refernece/unreference of the fb in omap_plane_update() to prevent this from happening. A reference is taken of the fb passed to update_plane(), the previous framebuffer (held by plane->fb) is unreferenced. This will prevent drm from destroying the framebuffer till the time it's unreferenced by the apply-worker. This is in addition to the exisitng reference/unreference in update_pin(), which is taken for the scanout of the plane's current framebuffer, and an unreference the previous framebuffer. Signed-off-by: Archit Taneja <archit@ti.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
| * drm/omap: Make fixed resolution panels workArchit Taneja2013-04-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omapdrm driver requires omapdss panel drivers to expose ops like detect, set_timings and check_timings. These can be NULL for fixed panel DPI, DBI, DSI and SDI drivers. At some places, there are no checks to see if the panel driver has these ops or not, and that leads to a crash. The following things are done to make fixed panels work: - The omap_connector's detect function is modified such that it considers panel types which are generally fixed panels as always connected(provided the panel driver doesn't have a detect op). Hence, the connector corresponding to these panels is always in a 'connected' state. - If a panel driver doesn't have a check_timings op, assume that it supports the mode passed to omap_connector_mode_valid(the 'mode_valid' drm helper function) - The function omap_encoder_update shouldn't really do anything for fixed resolution panels, make sure that it calls set_timings only if the panel driver has one. Signed-off-by: Archit Taneja <archit@ti.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
| * drm/omap: fix modeset_init if a panel doesn't satisfy omapdrm requirementsArchit Taneja2013-04-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | modeset_init iterates through all the registered omapdss devices and has some initial checks to see if the panel has a driver and the required driver ops for it to be usable by omapdrm. The function bails out from modeset_init if a panel doesn't meet the requirements, and stops the registration of the future panels and encoders which come after it, that isn't the correct thing to do, we should go through the rest of the panels. Replace the 'return's with 'continue's. Signed-off-by: Archit Taneja <archit@ti.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* | drm: Perform ioctl command validation on the stored kernel valuesChris Wilson2013-04-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Userspace is free to pass in any command bits it feels like through the ioctl cmd, and for example trinity likes to fuzz those bits to create conflicting commands. So instead of relying upon userspace to pass along the correct IN/OUT flags for the ioctl, use the flags as expected by the kernel. This does have a side-effect that NULL pointers can not be substituted by userspace in place of a struct. This feature was not being used by any driver, but instead exposed all of the command handlers to a user triggerable OOPS. Reported-by: Tommi Rantala <tt.rantala@gmail.com> Link: http://lkml.kernel.org/r/CA+ydwtpuBvbwxbt-tdgPUvj1EU7itmCHo_2B3w13HkD5+jWKow@mail.gmail.com Signed-off-by: Tommi Rantala <tt.rantala@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm: use vma_pages() to replace (vm_end - vm_start) >> PAGE_SHIFTLibin2013-04-15
| | | | | | | | | | | | | | | | (*->vm_end - *->vm_start) >> PAGE_SHIFT operation is implemented as a inline funcion vma_pages() in linux/mm.h, so using it. Signed-off-by: Libin <huawei.libin@huawei.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm: Destroy property blobs at mode config cleanup timeLaurent Pinchart2013-04-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Property blob objects need to be destroyed when cleaning up to avoid memory leaks. Go through the list of all blobs in the drm_mode_config_cleanup() function and destroy them. The drm_mode_config_cleanup() function needs to be moved after the drm_property_destroy_blob() declaration. Move drm_mode_config_init() as well to keep the functions together. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | Merge tag 'drm-intel-next-2013-04-06' of ↵Dave Airlie2013-04-15
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~danvet/drm-intel into drm-next Daniel writes: Since I expect Linus to open the merge window in about a week I guess this is the last i915 feature pull for 3.10. Highlights: Updated testing tree for -next. Highlights: - Corner case fixes discovered with static analyzers (Damien). - More fixes to combat unclaimed register errors on Haswell (Paulo). - Some small fixes to the gpu turbo code (Rodrigo+Ben), Ben has more fixes for overclocking support pending. - More prep work for fastboot from Chris. - VT-switchless suspend/resume from Jesse. - The prep work of Egbert Eich's hpd irq storm handling. Hopefully we can squeeze in the actual storm handling code for 3.10 ... - More convenience helpers for Imre's sg iterator. Core parts acked by Andrew Morton. - A bit of backlight code cleanup from Jani. - Fixed ilk gpu reset (Jesse). - Reduced color range handling fixes for VLV (Ville). The big item here is though the introduction of pipe_config to properly pre-compute the desired modeset state before touching the hw. Together with some very basic support to read out the current config from the hw and compare the state with the sw tracking. This is all prep work for more reliable fastboot, atomic modesets and other cool features. Stuff converted to the new world includes: - Most simple pipe attributes (reduce color range, pixel multiplier). - Pipe bpp/dither handling. - Some convenience flags like ->has_pch_encoder to simplify the code flow. - (Almost) DP clock handling, had to be reverted since part of a prep patch was lost in rebasing ... Expect a lot of patches for this throughout 3.11, there's tons of work till we have all state properly tracked for fastbooting to woExpect a lot of patches for this throughout 3.11, there's tons of work till we have all state properly tracked for fastbooting to work. For 3.10 I have a bunch of fixes queued up and I plan to send them all out at the end of this week. I need to shuffle patches in my -next queue a bit so that we don't but feature-y stuff in there, too. The main thing I'd like to sneak in is Egbert's hpd irq storm handling, which should be pretty low-risk since all the infrastructure work has landed already. I also have the oops fix pending, but that only mustered review before the w/e and giving how hairy that part of our modeset code is, I want to give it some more testing before forwarding. Note: annarchy.fd.o seems to run out of disk space, so couldn't push the usual for-airlied branch. Tag should work though. Note 2: I've had to do a backmerge since conflicts grew too ugly, but the upstream -rc I've backmerged is already in your drm-next. * tag 'drm-intel-next-2013-04-06' of git://people.freedesktop.org/~danvet/drm-intel: (75 commits) drm/i915: info level for simulated gpu hang dmesg notice drm/i915: revert eDP bpp clamping code changes Revert "drm/i915: fix DP get_hw_state return value" drm/i915: Don't use the HDMI port color range bit on Valleyview drm/i915: Set PIPECONF color range bit on Valleyview drm/i915: extract i9xx_set_pipeconf drm/i915: Add no-lvds quirk for Fujitsu Esprimo Q900 drm/i915: create pipe_config->dpll for clock state drm/i915: hw readout support for ->has_pch_encoders drm/i915: add hw state readout/checking for pipe_config drm/i915: rip out superflous is_dp&is_cpu_edp tracking drm/i915: remove leaky eDP functions drm/i915: track dp target_clock in pipe_config drm/i915: move dp_m_n computation to dp_encoder->compute_config drm/i915: clear up the fdi/dp set_m_n confusion drm/i915: Fix sdvo connector get_hw_state function drm/i915: drop DPFLIPSTAT enables on VLV v3 drm/i915: add Punit read/write routines for VLV v2 drm/i915: panel power sequencing for VLV eDP v2 drm/i915/dp: fix up VLV DP handling v2 ...
| * | drm/i915: info level for simulated gpu hang dmesg noticeDaniel Vetter2013-04-06
| | | | | | | | | | | | | | | | | | | | | Otherwise running igt will fill your dmesg with hang notices and it's hard to judge from a quick look whether they're expected or not. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: revert eDP bpp clamping code changesDaniel Vetter2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The behaviour around handling the eDP bpp value from vbt has been slightly changed in commit 3600836585e3fdef0a1410d63fe5ce4015007aac Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Mar 27 00:44:59 2013 +0100 drm/i915: convert DP autodither code to new infrastructure The old behaviour was that we used the plane's bpp (usually 24bpp) for computing the dp link bw, but set up the pipe with the bpp value from vbt if available. This takes the vbt bpp override into account even for the dp link bw configuration. On Paulo's hsw machine this resulted in a slower link clock and a black screen - but the mode actually /should/ fit even with the lower clock. Until we've cleared up simply stay bug-for-bug compatible with the old code. While at it, also restore a debug message lost in: commit 4e53c2e010e531b4a014692199e978482d471c7e Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Mar 27 00:44:58 2013 +0100 drm/i915: precompute pipe bpp before touching the hw Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | Revert "drm/i915: fix DP get_hw_state return value"Daniel Vetter2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit deb18211a110c102d32b3e9ed866bd7d25e0f8d5. It completely breaks the logic, since when we fall through to the end of the function we actually _have_ figured out the correct pipe. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Don't use the HDMI port color range bit on ValleyviewVille Syrjälä2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VLV docs still list the the color range selection bit for the HDMI ports, but for DP ports it has been repurposed. I have no idea whether the HDMI color range selection bit still works on VLV, but since we now have to use the PIPECONF color range bit for DP, we might as well do the same for HDMI. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Set PIPECONF color range bit on ValleyviewVille Syrjälä2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VLV has the color range selection bit in the PIPECONF register. Configure it appropriately. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> [danvet: fixup rebase issues due to slightly different baseline.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: extract i9xx_set_pipeconfDaniel Vetter2013-04-05
| | | | | | | | | | | | | | | | | | Prep-patch to improve the bpc handling in a next patch. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Add no-lvds quirk for Fujitsu Esprimo Q900Christian Lamparter2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "Mobile Sandy Bridge CPUs" in the Fujitsu Esprimo Q900 mini desktop PCs are probably misleading the LVDS detection code in intel_lvds_supported. Nothing is connected to the LVDS ports in these systems. Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: create pipe_config->dpll for clock stateDaniel Vetter2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock computations and handling are highly encoder specific, both in the optimal clock selection and also in which clocks to use and when sharing of clocks is possible. So the best place to do this is somewhere in the encoders, with a generic fallback for those encoders without special needs. To facility this, add a pipe_config->clocks_set boolean. This patch here is only prep work, it simply sets the computed clock values in pipe_config->dpll, and uses that data in the hw clock setting functions. Haswell code isn't touched, simply because Haswell clocks work much different and need their own infrastructure (with probably a Haswell-specific config->ddi_clock substruct). Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: hw readout support for ->has_pch_encodersDaniel Vetter2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now we can ditch the checks in the Haswell disable code. v2: add support for Haswell Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: add hw state readout/checking for pipe_configDaniel Vetter2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to be able to read out the hw state code for a bunch of reasons: - Correctly disabling boot-up/resume state. - Pure paranoia. Since not all of the pipe configuration is e.g. relevant for fastboot (or at least we can allow some wiggle room in some parameters, like the clocks), we need to add a strict_checking parameter to intel_pipe_config_compare for fastboot. For now intel_pipe_config_compare should be fully paranoid and check everything that the hw state readout code supports. Which for this infrastructure code is nothing. I've gone a bit overboard with adding 3 get_pipe_config functions: The ilk version will differ with the next patch, so it's not too onerous. v2: Don't check the hw config if the pipe is off, since an enabled, but dpms off crtc will obviously have tons of difference with the hw state. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: rip out superflous is_dp&is_cpu_edp trackingDaniel Vetter2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | The only exception left is is_cpu_edp in the haswell modeset code. We need that to assign the cpu transcoder, but we might want to move that eventually into the encoder, too. \o/-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: remove leaky eDP functionsDaniel Vetter2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Jesse Barnes noticed in his review of my DP cleanup series that intel_edp_target_clock is now unused. Checking related code I've noticed that also intel_edp_link_config is long unused. Kill them both. Wrt leaky eDP functions used in the common crtc code, the only thing still left is intel_encoder_is_pch_edp. That one is just due to the massive confusion between eDP vs. DP and port A vs. port D. Crtc code should at most concern itself with the later, never with the former. But that's material for another patch series. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: track dp target_clock in pipe_configDaniel Vetter2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need it in the fdi m_n computation, which nicely kills almost all ugly special cases in there. It looks like we also need this to handle 12bpc hdmi correctly. Eventually it might be better to switch things around and put the target clock into adjusted_mode->clock and create a new pipe_config parameter for the port link clock. v2: Add a massive comment in the code to explain this mess. v3: s/dp_target_clock/pixel_target_clock in anticipation of the hdmi use-case. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: move dp_m_n computation to dp_encoder->compute_configDaniel Vetter2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need a flag to designate dp encoders and the dp link m_n parameters in the pipe config for that. And now that the pipe bpp computations have been moved up and stored in the pipe config, too, we can do this without losing our sanity. v2: Rebased on top of Takashi Iwai's fix to (again) fix the target clock handling for eDP. Luckily the new code is sane enough and just does the right thing! v3: Move ->has_dp_encoder to this patch (Jesse). Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: clear up the fdi/dp set_m_n confusionDaniel Vetter2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's a rather decent confusion going on around transcoder m_n values. So let's clarify: - All dp encoders need this, either on the pch transcoder if it's a pch port, or on the cpu transcoder/pipe if it's a cpu port. - fdi links need to have the right m_n values for the fdi link set in the cpu transcoder. To handle the pch vs transcoder stuff a bit better, extract transcoder set_m_n helpers. To make them simpler, set intel_crtc->cpu_transcoder als in ironlake_crtc_mode_set, so that gen5+ (where the cpu m_n registers are all at the same offset) can use it. Haswell modeset is decently confused about dp vs. edp vs. fdi. dp vs. edp works exactly the same as dp (since there's no pch dp any more), so use that as a check. And only set up the fdi m_n values if we really have a pch encoder present (which means we have a VGA encoder). On ilk+ we've called ironlake_set_m_n both for cpu_edp and for pch encoders. Now that dp_set_m_n handles all dp links (thanks to the pch encoder check), we can ditch the cpu_edp stuff from the fdi_set_m_n function. Since the dp_m_n values are not readily available, we need to carefully coax the edp values out of the encoder. Hence we can't (yet) kill this superflous complexity. v2: Rebase on top of the ivb fdi B/C check patch - we need to properly clear intel_crtc->fdi_lane, otherwise those checks will misfire. v3: Rebased on top of a s/IS_HASWELL/HAS_DDI/ patch from Paulo Zanoni. v4: Drop the addition of has_dp_encoder, it's in the wrong patch (Jesse). Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | Merge tag 'v3.9-rc5' into drm-intel-next-queuedDaniel Vetter2013-04-03
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backmerge Linux 3.9-rc5 since I want to merge a few dp clock cleanups for -next, but they will conflict all over the place with commit 9d1a455b0ca1c2c956b4d9ab212864a8695270f1 Author: Takashi Iwai <tiwai@suse.de> Date: Mon Mar 18 11:25:36 2013 +0100 drm/i915: Use the fixed pixel clock for eDP in intel_dp_set_m_n() from -fixes. Conflicts: drivers/gpu/drm/i915/intel_dp.c: Simply adjacent lines changed. drivers/gpu/drm/i915/intel_panel.c: A field rename in -next conflicts with a bugfix in -fixes. Take the version from -fixes and apply the rename. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Fix sdvo connector get_hw_state functionDaniel Vetter2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The active output is only the currently selected one, which does not imply that it's actually enabled. Since we don't use the sdvo encoder side dpms support, we need to check whether the chip-side sdvo port is enabled instead. v2: Fix up Bugzilla links. v3: Simplify logic a bit (Chris). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60138 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63031 Cc: Egbert Eich <eich@pdx.freedesktop.org> Cc: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Egbert Eich <eich@pdx.freedesktop.org> (v2) Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: drop DPFLIPSTAT enables on VLV v3Jesse Barnes2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't need this until we start using the wait event commands. v2: move to i915_irq.c (Jesse) drop unneeded sprite flip done enables (Ville) v3: drop the DPFLIPSTAT enables altogether (Ville) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: add Punit read/write routines for VLV v2Jesse Barnes2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Slightly different than other platforms. v2 [Jani]: Fix IOSF_BYTE_ENABLES_SHIFT shift. Use common routine. v3: drop turbo defines from this patch (Ville) use PCI_DEVFN(2,0) instead of open coding (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Jani Nikula <jani.nikula@intel.com> [danvet: Add checkpatch bikeshed about missing space.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: panel power sequencing for VLV eDP v2Jesse Barnes2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPS register offsets have changed in Valleyview. v2: don't clobber port select bits on VLV when fixing up PPS timings don't bother with G4x PPS regs (Jani) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915/dp: fix up VLV DP handling v2Jesse Barnes2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Needed to handle pre/post enable/disable paths on VLV and avoid a few fields that are marked reserved on VLV. v2: don't set color range or DP PLL fields (Jani) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: add sprite assertion function for VLVJesse Barnes2013-04-02
| | | | | | | | | | | | | | | | | | | | | Need to make sure sprites are disabled before shutting off a pipe. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: sprite support for ValleyView v4Jesse Barnes2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No constant alpha yet though, that needs a new ioctl and/or property to get/set. v2: use drm_plane_format_cpp (Ville) fix up vlv_disable_plane, remove IVB bits (Ville) remove error path rework (Ville) fix component order confusion (Ville) clean up platform init (Ville) use compute_offset_xtiled (Ville) v3: fix up more format confusion (Ville) update to new page offset function (Ville) v4: remove incorrect formats from framebuffer_init (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: fix DDI get_hw_state return valueJesse Barnes2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | If we couldn't find a pipe we shouldn't return true. This might be even better as a WARN though, since it should be impossible to have the port enabled without a pipe selected. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: fix DP get_hw_state return valueJesse Barnes2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | If we couldn't find a pipe we shouldn't return true. This might be even better as a WARN though, since it should be impossible to have the port enabled without a pipe selected. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Skip modifying PCH DREF if not changing clock sourcesChris Wilson2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modifying the clock sources (via the DREF control on the PCH) is a slow multi-stage process as we need to let the clocks stabilise between each stage. If we are not actually changing the clock sources, then we can return early. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jani Nikula <jani.nikula@intel.com> [danvet: Appease checkpatch by deleting a space after a ~] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: group backlight related stuff into a structJani Nikula2013-04-02
| | | | | | | | | | | | | | | | | | | | | No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: fix ILK GPU reset for renderJesse Barnes2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | Earlier code would leave both bits set, so any reset after the first would only reset media. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: fixup fb bpp computation in pipe_config_set_bppDaniel Vetter2013-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ville pointed out that my assumption that no unsupported pixel format can get past the pipe config computation stage to the platform update_plane callbacks is wrong. The reason is that this function still checks the old fb->depth value instead of the new pixel_format. While checking with all the other places that use this I've noticed that intel_framebuffer_init already has all the platform checks we need, so replace those checks with a WARN_ON. Since fb->depth isn't set for YUV pixel formats and since we already can't create an fb with an rgb layout not support on the running platform I /think/ this patch doesn't fix any bug. But it surely looks better! v2: BGR formats are also only gen4+, so add the corresponding WARN_ON, too (Ville). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: check fb->pixel_format instead of bits_per_pixelDaniel Vetter2013-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've mostly switched over to the new more flexible schema, but there's one check left in the modeset code. Motivated by a question from Ville whether there's really no way an unsupported pixel_format can escape into our platform update_plane callbacks. v2: Ville noticed that the fb->depth check is redudant when we already check fb->pixel_format. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: fix up _wait_for macroDaniel Vetter2013-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As Thomas Gleixner spotted, it's rather horrible racy: - We can miss almost a full tick, so need to compensate by 1 jiffy. - We need to re-check the condition when having timed-out, since a the last check could have been before the timeout expired. E.g. when we've been preempted or a long irq happened. Cc: Thomas Gleixner <tglx@linutronix.de> Reported-by: Jack Winter <jbh@alchemy.lu> Cc: Jack Winter <jbh@alchemy.lu> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: fold wait_for_atomic_us into wait_for_atomicDaniel Vetter2013-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit bcf9dcc1e6269fac674e41f25d007ff75f76e840 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Sun Jul 15 09:42:38 2012 +0100 drm/i915: Workaround hang with BSD and forcewake on SandyBridge and commit 0cc2764cc4a4bd73df55f8893c871778cf7ddd0f Author: Ben Widawsky <ben@bwidawsk.net> Date: Sat Sep 1 22:59:48 2012 -0700 drm/i915: use cpu_relax() in wait_for_atomic these two macros are essentially the same, so unify them. We keep the _us version since it's a nice documentation for smaller timeouts. v2: Fixup time unit conversion, _wait_for takes ms (Ville). Cc: Jack Winter <jbh@alchemy.lu> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: remove "inline" keyword from ironlake_disable_display_irqPaulo Zanoni2013-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - It's a static function - I just added a few more users to it - Its sister ironlake_enable_display_irq is not marked as inline - The compiler will still inline if it thinks it should do Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: clean up pipe bpp confusionDaniel Vetter2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - gen4 and earlier (save for g4x) only really have a 8bpc pipe, with the possibility to dither to 6bpc using the panel fitter - g4x has hdmi, but no 12 bpc pipe ... !? Clamp hdmi accordingly. - TV/SDVO out are the only connectors available on platforms with a pipe bpp != 8, add code to force the pipe to 8bpc unconditionally. <rant> The dither handling on gmch platforms is one giant disaster. I'm hoping somewhat that vlv enabling will fix this up, but given that the 6bpc handling for edp was simply added with another quick hack, I don't have high hopes ... </rant> v2: Neither vlv nor g4x have 12bpc pipes. Still set pipe_bpp to 12*3, but let the crtc code clamp things down to 10bpc on these platforms. v3: Fix a bpc vs. bpp mixup in the gen4 and earlier pipe_bpp limiter code. v4: Drop the hunk in intel_hdmi.c about g4x/vlv 12bpc, it was wrong. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: clean up plane bpp confusionDaniel Vetter2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - There is no 16bpc linear color format in our hw. gen4+ has a 16 bpc float layout, but we don't really support it. - 10bpc is a gen4+ feature, fix up the support for it. - Update_plane should never see a wrong fb bpp value, BUG in the corresponding cases. v2: Rebase on top of Ville's plane pixel layout changes. v3: Actually drop the old gen4 check for 10bpc planes, spotted by Ville Syrjälä. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: convert DP autodither code to new infrastructureDaniel Vetter2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The old code only handled either 6bpc or 8bpc. Since it's easy to do, reorganize the code to be a bit more generic so that it can also handle 10bpc and 12bpc. Note that we still start with 8bpc, so there's no functional change. Also, since we no don't need to compute the 6BPC flag in the mode_valid callback, we can consolidate things a bit. That requires though that the link bw computation is moved up in the compute_config callback. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: precompute pipe bpp before touching the hwDaniel Vetter2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The procedure has now 3 steps: 1. Compute the bpp that the plane will output, this is done in pipe_config_set_bpp and stored into pipe_config->pipe_bpp. Also, this function clamps the pipe_bpp to whatever limit the EDID of any connected output specifies. 2. Adjust the pipe_bpp in the encoder and crtc functions, according to whatever constraints there are. 3. Decide whether to use dither by comparing the stored plane bpp with computed pipe_bpp. There are a few slight functional changes in this patch: - LVDS connector are now also going through the EDID clamping. But in a 2nd change we now unconditionally force the lvds bpc value - this shouldn't matter in reality when the panel setup is consistent, but better safe than sorry. - HDMI now forces the pipe_bpp to the selected value - I think that's what we actually want, since otherwise at least the pixelclock computations are wrong (I'm not sure whether the port would accept e.g. 10 bpc when in 12bpc mode). Contrary to the old code, we pick the next higher bpc value, since otherwise there's no way to make use of the 12 bpc mode (since the next patch will remove the 12bpc plane format, it doesn't exist). Both of these changes are due to the removal of the pipe_bpp = min(display_bpp, plane_bpp); statement. Another slight change is the reworking of the dp bpc code: - For the mode_valid callback it's sufficient to only check whether the mode would fit at the lowest bpc. - The bandwidth computation code is a bit restructured: It now walks all available bpp values in an outer loop and the codeblock that computes derived values (once a good configuration is found) has been moved out of the for loop maze. This is prep work to allow us to successively fall back on bpc values, and also correctly support bpc values != 8 or 6. v2: Rebased on top of Paulo Zanoni's little refactoring to use more drm dp helper functions. v3: Rebased on top of Jani's eDP bpp fix and Ville's limited color range work. v4: Remove the INTEL_MODE_DP_FORCE_6BPC #define, no longer needed. v5: Remove intel_crtc->bpp, too, and fix up the 12bpc check in the hdmi code. Also fixup the bpp check in intel_dp.c, it'll get reworked in a later patch though again. v6: Fix spelling in a comment. v7: Debug output improvements for the bpp computation. v8: Fixup 6bpc lvds check - dual-link and 8bpc mode are different things! v9: Reinstate the fix to properly ignore the firmware edp bpp ... this was lost in a rebase. v10: Both g4x and vlv lack 12bpc pipes, so don't enforce that we have that. Still unsure whether this is the way to go, but at least 6bpc for a 8bpc hdmi output seems to work. v11: And g4x/vlv also lack 12bpc hdmi support, so only support high depth on DP. Adjust the code. v12: Rebased. v13: Split out the introduction of pipe_config->dither|pipe_bpp, as requested from Jesse Barnes. v14: Split out the special 6BPC handling for DP, as requested by Jesse Barnes. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: introduce pipe_config->dither|pipe_bppDaniel Vetter2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | We want to compute this earlier. To avoid a big complicated patch, this patch here just does the big search&replace and still calls the old functions at the same places. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: add pipe_config->limited_color_rangeDaniel Vetter2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a useful struct for this, let's use it. Some neat pointer-chasing required, but it's all there already. v2: Rebased on top of the added Haswell limited color range support. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: add pipe_config->has_pch_encoderDaniel Vetter2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is used way too often in the enable/disable paths. And will be even more useful in the future. Note that correct semantics of this change highly depend upon correct updating of intel_crtc->config: Like with all other modeset state, we need to call ->disable with the old config, but ->mode_set and ->enable with the new config. v2: Do not yet use the flag in the ->disable callbacks - atm we don't yet have support for the information stored in the pipe_config in the hw state readout code, so this will be wrong at boot-up/resume. v3: Rebased on top of the hdmi/dp ddi encoder merging. v4: Fixup stupid rebase error which lead to a NULL vfunc deref. v5: On haswell the VGA port is on the PCH! v6: s/IS_HASWELL/HAS_DDI/, spotted by Paulo Zanoni. Also add a missing parameter name in a function declaration. v7: Don't forget to git add ... Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 21:24:31 -0400