| Commit message (Collapse) | Author | Age |
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Standard timings don't let you say 1366. Both 1360 and 1368 have been
seen in the wild. So invent a CVT timing for it. CVT will round 1366 up
to 1368; we'll then manually underscan it.
Split this into two parts, since we need to do something sneaky between
them in the future.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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1.4 adds better pixel clock precision, explicit reduced blanking
awareness, and extended sync ranges. It's almost like a real spec.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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The generic block walk callback looks like overkill, but we'll need it
for other detailed block walks in the future.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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In 1.4, the first detailed mode is always the preferred mode. The bit
that used to mean that, now means "this mode is the physical size in
pixels".
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Also, document what the spec says to do.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This makes fetching the second EDID block on HDMI monitors actually
work. DDC can't transfer more than 128 bytes at a time. Also,
rearrange the code so the pure DDC bits are separate from block parse.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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* drm-ttm-pool:
drm/ttm: using kmalloc/kfree requires including slab.h
drm/ttm: include linux/seq_file.h for seq_printf
drm/ttm: Add sysfs interface to control pool allocator.
drm/ttm: Use set_pages_array_wc instead of set_memory_wc.
arch/x86: Add array variants for setting memory to wc caching.
drm/nouveau: Add ttm page pool debugfs file.
drm/radeon/kms: Add ttm page pool debugfs file.
drm/ttm: Add debugfs output entry to pool allocator.
drm/ttm: add pool wc/uc page allocator V3
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Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Fixes
drivers/gpu/drm/ttm/ttm_page_alloc.c: In function 'ttm_page_alloc_debugfs':
drivers/gpu/drm/ttm/ttm_page_alloc.c:829: error: implicit declaration of
function 'seq_printf'
Signed-off-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Sysfs interface allows user to configure pool allocator functionality and
change limits for the size of pool.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Using single call to set multiple pages to wc reduces number of expensive cache
flushes.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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ttm_page_pool file is hooked ttm_page_alloc_debugfs for pool
allocator state.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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ttm_page_pool file is hooked ttm_page_alloc_debugfs for pool
allocator state.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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ttm_page_alloc_debugfs can be registered to output the state
of pools.
Debugfs file will output number of pages freed from the pool,
number of pages in pool now and the lowes number of pages in
pool since previous shrink.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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On AGP system we might allocate/free routinely uncached or wc memory,
changing page from cached (wb) to uc or wc is very expensive and involves
a lot of flushing. To improve performance this allocator use a pool
of uc,wc pages.
Pools are protected with spinlocks to allow multiple threads to allocate pages
simultanously. Expensive operations are done outside of spinlock to maximize
concurrency.
Pools are linked lists of pages that were recently freed. mm shrink callback
allows kernel to claim back pages when they are required for something else.
Fixes:
* set_pages_array_wb handles highmem pages so we don't have to remove them
from pool.
* Add count parameter to ttm_put_pages to avoid looping in free code.
* Change looping from _safe to normal in pool fill error path.
* Initialize sum variable and make the loop prettier in get_num_unused_pages.
* Moved pages_freed reseting inside the loop in ttm_page_pool_free.
* Add warning comment about spinlock context in ttm_page_pool_free.
Based on Jerome Glisse's and Dave Airlie's pool allocator.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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into drm-core-next
* 'anholt/drm-intel-next' of /home/airlied/kernel/drm-next: (48 commits)
agp/intel-gtt: kill previous_size assignments
agp/intel-gtt: kill intel_i830_tlbflush
agp/intel: split out gmch/gtt probe, part 1
agp/intel: kill mutli_gmch_chip
agp/intel: uncoditionally reconfigure driver on resume
agp/intel: split out the GTT support
agp/intel: introduce intel-agp.h header file
drm/i915: Don't touch PORT_HOTPLUG_EN in intel_dp_detect()
drm/i915/pch: Use minimal number of FDI lanes (v2)
drm/i915: Add the support of memory self-refresh on Ironlake
drm/i915: Move Pineview CxSR and watermark code into update_wm hook.
drm/i915: Only save/restore FBC on the platform that supports FBC
drm/i915: Fix the incorrect argument for SDVO SET_TV_format command
drm/i915: Add support of SDVO on Ibexpeak PCH
drm/i915: Don't enable pipe/plane/VCO early (wait for DPMS on).
drm/i915: do not read uninitialized ->dev_private
Revert "drm/i915: Use a dmi quirk to skip a broken SDVO TV output."
drm/i915: implement multifunction SDVO device support
drm/i915: remove unused intel_pipe_get_connector()
drm/i915: remove connector object in old output structure
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PORT_HOTPLUG_EN has allready been setup in i915_driver_irq_postinstall(),
when intel_dp_detect() runs.
Delete the DP[BCD]_HOTPLUG_INT_EN defines, they are not referenced anymore.
I found this while searching for a fix for
https://bugzilla.redhat.com/show_bug.cgi?id=528312
Signed-off-by: Karsten Wiese <fzu@wemgehoertderstaat.de>
Signed-off-by: Eric Anholt <eric@anholt.net>
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This should be a small power savings. Tested on Lenovo T410 (Ironlake), LVDS
VGA and DisplayPort, up to 1920x1200R.
v2: Add Sandybridge support, fix obvious math error.
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Update the self-refresh watermark for display plane/cursor and enable
the memory self-refresh on Ironlake. The watermark is also updated for
the active display plane.
More than 1W idle power is saved on one Ironlake laptop after enabling
memory self-refresh.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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Previously, after setting up the Pineview CxSR state, i9xx_update_wm would
get called and overwrite our state.
BTW: We will disable the self-refresh and never enable it any more if we
can't find the appropriate the latency on pineview plaftorm. In such case
the update_wm callback will be NULL.
The bitmask macro is also defined to access the corresponding fifo
watermark register.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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Otherwise it will cause that S-video output becomes black/white when
switching to other TV format.
http://bugs.freedesktop.org/show_bug.cgi?id=23916
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Tested-by: Arnold <arnold.erbsloeh@web.de>
Tested-by: Bazin <bazin.cz@gmail.com>
Tested-by: Nigel <nigel_tuck@eircom.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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SDVO on Ibexpeak PCH with Ironlake is multiplexed with
HDMIB port, and only has SDVOB port.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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The existing code handling the DPMS ON event is much more careful to
ensure that these registers are enabled according to strict sequencing
requirements. Enabling these early in mode_set simply defeats that.
Signed-off-by: Carl Worth <cworth@cworth.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
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->dev_private at that point is NULL and is initialied only a few lines
later.
Signed-off-by: Luca Tettamanti <kronos.it@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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This reverts commit 6070a4a928f8c92b9fae7d6717ebbb05f425d6b2.
The quirk for this SDVO device on IBM specific board is just a hack
in old code which showed the broken multifunction SDVO support in
the driver. Multifunction SDVO patch provided the right fix for it.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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With new intel_encoder/intel_connector structure change, each supported
connector type on SDVO device will be created as a new 'intel_connector',
and all attached to one 'intel_encoder' for its SDVO port.
The SDVO encoder will handle SDVO protocol stuff, and each connector does
its own part of work now, like detection is only to check if current active
output is itself, etc.
Update since last submit:
- Fixed SDVO TV property creation failure by incorrect set target output call
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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Added by original eDP support patch, not used any more.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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As all display drivers have been converted, remove the left reference
for connector object in old structure.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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Also remove old UMS copied code for get_crtc.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Probably only matters for format-converting dongles, but might as well
get it right all the time.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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DP on Cougarpoint has new training pattern definitions, and
new transcoder DP control register is used to determine the mapping
for transcoder and DP digital output. And eDP for Sandybridge has
new voltage and pre-emphasis level definitions.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Fix transcoder select bit for HDMI on CPT.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Fix the transcoder select bit for LVDS on CPT.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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To make CRT force detect reliable on Cougarpoint, we need to
disable DAC before force detect, and restore back when trigger
is completed.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Cougarpoint is the new PCH for Sandybridge CPU. This one resolves the
chipset change for display pipeline compared to previous Ibexpeak PCH.
Sandybridge/Cougarpoint has different FDI training parameters, so this also
makes seperate FDI training functions for IBX and CPT. Other change includes
new transcoder DPLL select function to set which DPLL for transcoder to pick
up.
And with another new transcoder C introduced in Cougarpoint, each connector
has new transcoder select bits. This one adds that change to light up VGA.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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PCH is the new name for south bridge from Ironlake/Sandybridge,
which contains most of the display outputs except eDP. This one
adds a probe function to detect current PCH type, and method to
detect Cougarpoint PCH.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Integrated TV is deprecated in new chips from Ironlake.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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