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* drm/tegra: dc: No longer disable planes at CRTC disableThierry Reding2015-01-27
| | | | | | | The DRM core should take care of disabling all unneeded planes, so there is no need to do this explicitly. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Move tegra_drm_mode_funcs to the coreThierry Reding2015-01-27
| | | | | | | This structure will be extended using non-framebuffer related callbacks in subsequent patches, so it should move to a more central location. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc: Wait for idle when disabledThierry Reding2015-01-27
| | | | | | | | When disabling the display controller, stop it and wait for it to become idle. Doing so ensures that no further accesses to the framebuffer occur and the buffers can be safely unmapped or freed. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Stop CRTC at CRTC disable timeThierry Reding2015-01-27
| | | | | | | | | | | | | Previously output drivers would all stop the display controller in their disable path. However with the transition to atomic modesetting the display controller needs to be kept running until all planes have been disabled so that software can properly determine (using VBLANK counts) when it is safe to remove the framebuffers associated with the planes. Moving this code into the display controller's disable path also gets rid of the duplication of this into all output drivers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Use tegra_commit_dc() in output driversThierry Reding2015-01-27
| | | | | | | All output drivers have open-coded variants of this function, so export it to remove some code duplication. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: gem: oops in error handlingDan Carpenter2015-01-27
| | | | | | | kfree(ERR_PTR(-ENOMEM)) will not work very well. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc: Fix bad irqsave/restore in tegra_dc_finish_page_flip()Dan Carpenter2015-01-27
| | | | | | | | | | We can't save two values to the IRQ flags at the same time so the IRQs are not enabled at the end. This kind of bug is easy to miss in testing if the function is normally called with IRQs disabled so we wouldn't enable IRQs anyway. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi: Adjust D-PHY timingDavid Ung2015-01-27
| | | | | | | | | Compliance testing shows that HS Trail is off by -12%. Increase the HS Trail time to make this test pass. Signed-off-by: David Ung <davidu@nvidia.com> [treding@nvidia.com: update specification references, add comment] Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi: Reset across ->exit()/->init()Thierry Reding2015-01-27
| | | | | | | This allows a DRM driver unload/reload cycle to completely reset the DSI controller and may help in situations where it's broken. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi: Soft-reset controller on ->disableThierry Reding2015-01-27
| | | | | | | This reset is necessary to properly clean up the internal state of the controller. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi: Registers are 32-bitThierry Reding2015-01-27
| | | | | | | | Use a sized unsigned 32-bit data type (u32) to store register contents. The DSI registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: hdmi: Registers are 32-bitThierry Reding2015-01-27
| | | | | | | | Use a sized unsigned 32-bit data type (u32) to store register contents. The HDMI registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc: Return planar flag for non-YUV modesThierry Reding2015-01-27
| | | | | | | This prevents the compiler from warning about using a variable that is possibly uninitialized. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc: Describe register copiesThierry Reding2015-01-27
| | | | | | | | | | | | | | | Most of the display controller's registers are double-buffered, a few of them are triple-buffered. The ASSEMBLY shadow copy is latched intto the ACTIVE copy for double-buffered registers. For triple-buffered registers the ASSEMBLY copy is first latched into the ARM copy. Latching into the ACTIVE copy happens immediately if the controller is inactive. Otherwise the latching happens on the next frame boundary. The latching of the ASSEMBLY into the ARM copy happens immediately. Latching is controlled by a set of *_ACT_REQ and *_UPDATE bits in the DC_CMD_STATE_CONTROL register. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc: Initialize border colorThierry Reding2015-01-27
| | | | | | | | | Tegra114 and earlier support specifying the color of the border (i.e. the active area of the screen that is not covered by any of the overlay windows). By default this is set to a light blue, so set it to black to comply with the requirements set by atomic modesetting. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Check for NULL pointer instead of IS_ERR()Dan Carpenter2015-01-27
| | | | | | | | iommu_domain_alloc() returns NULL on error, it never returns error pointers. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: plane: Use proper possible_crtcs maskThierry Reding2015-01-27
| | | | | | | | The possible_crtcs mask needs to be a mask of CRTC indices. There is no guarantee that the DRM indices match the hardware pipe number, so the mask must be computed from the CRTC index. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Remove redundant zeroing out of memoryThierry Reding2015-01-27
| | | | | | | | The DRM core now zeroes out the memory associated with CRTC, encoder and connector objects upon cleanup, so there's no need to explicitly do that in drivers anymore. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: gem: Use iommu_map_sg()Thierry Reding2015-01-27
| | | | | | | The iommu_map_sg() function is now available in the IOMMU API, so drop the open-coded variant. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Provide a proper struct bus_typeThierry Reding2015-01-27
| | | | | | | | | | | | | | | | | | | | | Previously the struct bus_type exported by the host1x infrastructure was only a very basic skeleton. Turn that implementation into a more full- fledged bus to support proper probe ordering and power management. Note that the bus infrastructure needs to be available before any of the drivers can be registered. This is automatically ensured if all drivers are built as loadable modules (via symbol dependencies). If all drivers are built-in there are no such guarantees and the link order determines the initcall ordering. Adjust drivers/gpu/Makefile to make sure that the host1x bus infrastructure is initialized prior to any of its users (only drm/tegra currently). v2: Fix building host1x and tegra-drm as modules Reported-by: Dave Airlie <airlied@gmail.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'topic/core-stuff-2014-12-19' of ↵Dave Airlie2015-01-08
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm-intel into drm-next Misc drm patches with mostly polish patches from Thierry, with a bit of generic mode validation from Ville and a few other oddball things. * tag 'topic/core-stuff-2014-12-19' of git://anongit.freedesktop.org/drm-intel: (25 commits) drm: Include drm_crtc_helper.h in DocBook drm: Make drm_crtc_helper.h standalone includible drm: Move IRQ related fields to proper section drm: Remove stale comment drm: Do basic sanity checks for user modes drm: Perform basic sanity checks on probed modes drm: Reorganize probed mode validation drm/doc: Remove duplicate "by" drm/info: Remove unused code drm/cache: Use wbinvd helpers drm/plane-helper: Test for plane disable earlier drm/doc: Document drm_add_modes_noedid() usage drm: bit of spell-check / editorializing. drm: Prefer sizeof(type) over sizeof type drm: Remove useless else block drm: Remove unneeded braces for single statement blocks drm: Do not assign in if condition drm: Prefer kmalloc_array() over kmalloc() with multiply drm: Prefer kcalloc() over kzalloc() with multiply drm: Miscellaneous checkpatch whitespace cleanups ...
| * drm/tegra: Remove dummy ->load_lut() implementationThierry Reding2014-12-10
| | | | | | | | | | | | | | | | The ->load_lut() callback is optional, therefore a dummy implementation is not needed. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/tegra: dc: Select root window for event dispatchSean Paul2014-12-17
| | | | | | | | | | | | | | | | | | | | | | | | | | In finish pageflip, the driver was not selecting the root window when dispatching events. This exposed a race where a plane update would change the window selection and cause tegra_dc_finish_page_flip to check the wrong base address. This patch also protects access to the window selection register as well as the registers affected by it. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | drm/tegra: gem: Use the proper size for GEM objectsThierry Reding2014-12-17
| | | | | | | | | | | | | | | | | | | | | | If the requested buffer size wasn't a multiple of the page size, the IOMMU code would round down the size to the next multiple of the page size, thereby causing translation errors. To fix this we no longer pass around the requested size but reuse the computed size of the GEM object. This is already rounded to the next page boundary, so mapping that size works out fine. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | drm/tegra: gem: Flush buffer objects upon allocationThierry Reding2014-12-17
| | | | | | | | | | | | | | | | Buffers obtained via shmem may still have associated cachelines. If they aren't properly flushed they may cause framebuffer corruption if the cache gets flushed after the application has drawn to it. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | drm/tegra: dc: Fix a potential race on page-flip completionThierry Reding2014-12-17
| | | | | | | | | | | | | | | | Page-flip completion could race with page-flip submission, so extend the critical section to include all accesses to page-flip related data. Reported-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | drm/tegra: dc: Consistently use the same pipeThierry Reding2014-12-17
| | | | | | | | | | | | | | | | | | | | | | | | | | The hardware pipe numbers don't always match the DRM CRTC indices. This can happen for example if the first display controller defers probe, causing it to be registered with DRM after the second display controller. When that happens the hardware pipe numbers and DRM CRTC indices become different. Make sure that the CRTC index is always used when accessing per-CRTC VBLANK data. This can be ensured by using the drm_crtc_vblank_*() API, which will do the right thing automatically given a struct drm_crtc *. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | Merge tag 'v3.18-rc7' into drm-nextDave Airlie2014-12-01
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | This fixes a bunch of conflicts prior to merging i915 tree. Linux 3.18-rc7 Conflicts: drivers/gpu/drm/exynos/exynos_drm_drv.c drivers/gpu/drm/i915/i915_drv.c drivers/gpu/drm/i915/intel_pm.c drivers/gpu/drm/tegra/dc.c
| * drm/tegra: dc: Add missing call to drm_vblank_on()Thierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When the CRTC is enabled, make sure the VBLANK machinery is enabled. Failure to do so will cause drm_vblank_get() to not enable the VBLANK on the CRTC and VBLANK-synchronized page-flips won't work. While at it, get rid of the legacy drm_vblank_pre_modeset() and drm_vblank_post_modeset() calls that are replaced by drm_vblank_on() and drm_vblank_off(). Reported-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | Merge tag 'drm/tegra/for-3.19-rc1' of ↵Dave Airlie2014-11-14
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~tagr/linux into drm-next drm/tegra: Changes for v3.19-rc1 The highlights in this pull request are: * IOMMU support: The Tegra DRM driver can now deal with discontiguous buffers if an IOMMU exists in the system. That means it can allocate using drm_gem_get_pages() and will map them into IOVA space via the IOMMU API. Similarly, non-contiguous PRIME buffers can be imported from a different driver, which allows better integration with gk20a (nouveau) and less hacks. * Universal planes: This is precursory work for atomic modesetting and will allow hardware cursor support to be implemented on pre-Tegra114 where RGB cursors were not supported. * DSI ganged-mode support: The DSI controller can now gang up with a second DSI controller to drive high resolution DSI panels. Besides those bigger changes there is a slew of fixes, cleanups, plugged memory leaks and so on. * tag 'drm/tegra/for-3.19-rc1' of git://people.freedesktop.org/~tagr/linux: (44 commits) drm/tegra: gem: Check before freeing CMA memory drm/tegra: fb: Add error codes to error messages drm/tegra: fb: Properly release GEM objects on failure drm/tegra: Detach panel when a connector is removed drm/tegra: Plug memory leak drm/tegra: gem: Use more consistent data types drm/tegra: fb: Do not destroy framebuffer drm/tegra: gem: dumb: pitch and size are outputs drm/tegra: Enable the hotplug interrupt only when necessary drm/tegra: dc: Universal plane support drm/tegra: dc: Registers are 32 bits wide drm/tegra: dc: Factor out DC, window and cursor commit drm/tegra: Add IOMMU support drm/tegra: Fix error handling cleanup drm/tegra: gem: Use dma_mmap_writecombine() drm/tegra: gem: Remove redundant drm_gem_free_mmap_offset() drm/tegra: gem: Cleanup tegra_bo_create_with_handle() drm/tegra: gem: Extract tegra_bo_alloc_object() drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlier drm/tegra: dsi: Replace 1000000 by USEC_PER_SEC ...
| * | drm/tegra: gem: Check before freeing CMA memoryThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dma_free_writecombine() must not be called on a buffer that couldn't be allocated. Check for a valid virtual address before attempting to free the memory to avoid a crash. Reported-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: fb: Add error codes to error messagesThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | This helps in determining what errors happened at specifics points in the initialization sequence. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: fb: Properly release GEM objects on failureThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | When fbdev initialization fails, make sure to unreference the GEM objects properly. Note that we can't do this in the general error unwinding path because ownership of the GEM object references is transferred to the framebuffer upon creation. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: Detach panel when a connector is removedThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | When the DRM device is torn down and the connector is removed, make sure to detach the panel to make sure there are no dangling pointers. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: Plug memory leakThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | Free the DRM device-private memory upon driver unload to make sure the memory doesn't leak. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: gem: Use more consistent data typesThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | Use size_t consistently for sizes and u32/u64 instead of uint32_t and uint64_t. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: fb: Do not destroy framebufferThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Drop a reference instead of directly calling the framebuffer .destroy() callback at fbdev free time. This is necessary to make sure the object isn't destroyed if anyone else still has a reference. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: gem: dumb: pitch and size are outputsThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When creating a dumb buffer object using the DRM_IOCTL_MODE_CREATE_DUMB IOCTL, only the width, height, bpp and flags parameters are inputs. The caller is not guaranteed to zero out or set handle, pitch and size, so the driver must not treat these values as possible inputs. Fixes a bug where running the Weston compositor on Tegra DRM would cause an attempt to allocate a 3 GiB framebuffer to be allocated. Fixes: de2ba664c30f ("gpu: host1x: drm: Add memory manager and fb") Cc: stable@vger.kernel.org Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: Enable the hotplug interrupt only when necessaryThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hotplug handling needs access to the DRM device, which only appears at ->init() time. Disable interrupts up until that time. Similarly, when an output is removed, disable the hotplug interrupt again because the DRM device (and with it the hotplug infrastructure) is going away. Also make sure to only access the DRM device if it's available. Given the above change for the hotplug interrupt this should really never happen, but the extra check doesn't hurt either. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dc: Universal plane supportThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | This allows the primary plane and cursor to be exposed as regular DRM/KMS planes, which is a prerequisite for atomic modesetting and gives userspace more flexibility over controlling them. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dc: Registers are 32 bits wideThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | Using an unsigned long type will cause these variables to become 64-bit on 64-bit SoCs. In practice this should always work, but there's no need for carrying around the additional 32 bits. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dc: Factor out DC, window and cursor commitThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | The sequence to commit changes to the DC, window or cursor configuration is repetitive and can be extracted into separate functions for ease of use. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: Add IOMMU supportThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | When an IOMMU device is available on the platform bus, allocate an IOMMU domain and attach the display controllers to it. The display controllers can then scan out non-contiguous buffers by mapping them through the IOMMU. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: Fix error handling cleanupThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DRM driver's ->load() implementation didn't do a good job (no job at all really) cleaning up on failure. Fix that by undoing any prior setup when an error occurs. This requires a bit of rework to make it possible to clean up fbdev midway. This was tested by injecting errors at various points during the initialization sequence and verifying that error cleanup didn't crash and no memory leaked (using kmemleak). Reported-by: Stéphane Marchesin <marcheu@chromium.org> Reported-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: gem: Use dma_mmap_writecombine()Thierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | Use the existing API rather than open-coding equivalent functionality in the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: gem: Remove redundant drm_gem_free_mmap_offset()Thierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | The drm_gem_object_release() function already performs this cleanup, so there is no reason to do it explicitly. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: gem: Cleanup tegra_bo_create_with_handle()Thierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | There is only a single location where the function needs to do cleanup. Skip the error unwinding path and call the cleanup function directly instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: gem: Extract tegra_bo_alloc_object()Thierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | | | | This function implements the common buffer object allocation used for both allocation and import paths. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlierSean Paul2014-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure the DSI PHY_TIMING and BTA_TIMING registers are initialized when the clocks are set up as opposed to when the output is enabled. This makes sure that the PHY timings are properly set up when the panel is prepared and that DCS commands sent at that time use the appropriate timings. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Replace 1000000 by USEC_PER_SECThierry Reding2014-11-13
| | | | | | | | | | | | | | | | | | Using the symbolic constant instantly provides a lot more context. Signed-off-by: Thierry Reding <treding@nvidia.com>
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