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* drm/tegra: sor - Fix copy/paste errorStéphane Marchesin2014-06-09
| | | | | | | | The comment above mentions link A/B but this isn't what the code does, so let's fix that. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Remove pixel clock roundingStéphane Marchesin2014-06-09
| | | | | | | | | | The code currently rounds up the clock to the next MHZ, which is rounding up a 69.5MHz clock to 70MHz on my machine. This in turn prevents the display from syncing. Removing this rounding fixes eDP for me. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Make debugfs setup consistentThierry Reding2014-06-06
| | | | | | | Other output drivers set up debugfs slightly differently. Bring the SOR driver in line with those for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Recursively remove debugfs treeThierry Reding2014-06-06
| | | | | | | | Removing only the root directory will fail when there are still files in it. Instead of manually removing all files, remove the whole directory recursively. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dp - Mark the connector as hotplug capableThierry Reding2014-06-05
| | | | | | | Doing so allows the hotplug events generated by the connector to be properly handled by the DRM poll helpers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dp - Implement hotplug detection in work queueThierry Reding2014-06-05
| | | | | | | | Calling the drm_helper_hpd_irq_event() helper can sleep, so instead of invoking it directly from the interrupt handler, schedule a work queue and run it from there. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Add hardware cursor supportThierry Reding2014-06-05
| | | | | | | | Enable hardware cursor support on Tegra124. Earlier generations support the hardware cursor to some degree as well, but not in a way that can be generically exposed. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Remove host1x drm_bus implementationThierry Reding2014-06-05
| | | | | | | The DRM core can now cope with drivers that don't have an associated struct drm_bus, so the host1x implementation is no longer useful. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: gem - Make tegra_bo_import() staticThierry Reding2014-06-05
| | | | | | | The function is never used outside of the source file and therefore can be locally scoped. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: hdmi - Add Tegra124 supportThierry Reding2014-06-05
| | | | | | | | Tegra124 is mostly backwards-compatible with Tegra114. However, Tegra124 supports a few more features (e.g. interlacing, ...). Introduce a new compatible string and TMDS tables to cope with these differences. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Protect CRC debugfs against enable stateThierry Reding2014-06-05
| | | | | | | | Accessing the CRC debugfs file will hang the system if the SOR is not enabled, so make sure that it is stays enabled until the CRC has been read. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Do not needlessly recompute pclkThierry Reding2014-06-05
| | | | | | | | | In some cases the pixel clock used to not be correct, which is why it had to be recomputed. It turns out that the reason why it wasn't correct is that it was used wrongly. If used correctly there's not need for the recomputation. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc - Compute shift clock divider in output driversThierry Reding2014-06-05
| | | | | | | | The shift clock divider is highly dependent on the type of output, so push computation of it down into the output drivers. The old code used to work merely by accident. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc - Move around shift clock programmingThierry Reding2014-06-05
| | | | | | | Program the shift clock divider in tegra_crtc_setup_clk() since that's where the divider is computed, so passing it around can be avoided. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Reset controller on driver unloadThierry Reding2014-06-05
| | | | | | | | Assert the DSI controller's reset when the driver is unloaded to reduce power consumption and to put the controller into a known state for subsequent driver reloads. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Fix typo when disabling controllerThierry Reding2014-06-05
| | | | | | | When disabling the DSI controller, the code wasn't really doing what it was supposed to. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Add enable guardThierry Reding2014-06-05
| | | | | | | | To prevent the enable or disable operations to potentially be run multiple times, add guards to return early when the output is already in the targetted state. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Initialize proper packet sequencesThierry Reding2014-06-05
| | | | | | | | | The packet sequencer needs to be programmed depending on the video mode of the attached peripheral. Add support for non-burst video modes with sync events (as opposed to sync pulses) and select either sequence depending on the video mode. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Implement VDD supply supportThierry Reding2014-06-05
| | | | | | | | | The DSI controllers are powered by a (typically 1.2V) regulator. Usually this is always on, so there was no need to support enabling or disabling it thus far. But in order not to consume any power when DSI is inactive, give the driver a chance to enable or disable the supply as needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Remove unneeded codeThierry Reding2014-06-05
| | | | | | | | A bunch of registers are initialized to 0 upon during driver probe. It turns out that none of these are actually needed, so they can simply be dropped. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Use internal pixel formatThierry Reding2014-06-05
| | | | | | | | The pixel format enumeration values used by the Tegra DSI controller don't match those defined by the DSI framework. Make sure to convert them to the internal format before writing it to the register. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: hdmi - Fix disable sequenceThierry Reding2014-06-05
| | | | | | | | | | | For some reason when the PW*_ENABLE and PM*_ENABLE fields are cleared during disable, the HDMI output stops working properly. Resetting and initializing doesn't help. Comment out those accesses for now until it has been determined what to do about them. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: hdmi - Disable LVDS modeThierry Reding2014-06-05
| | | | | | | | Disable LVDS mode according to register documentation. It seems like this has no effect on the operation of HDMI, but it's probably a good idea to do this anyway. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: hdmi - Use proper power-up sequenceThierry Reding2014-06-05
| | | | | | | This reflects the power-up sequence as described in the documentation, but it doesn't seem to be strictly necessary to get HDMI to work. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: hdmi - Clean up clock usageThierry Reding2014-06-05
| | | | | | | Clocks are never enabled or disabled in atomic context, so we can use the clk_prepare_enable() and clk_disable_unprepare() helpers instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: hdmi - Reverse regulator enable orderingThierry Reding2014-06-05
| | | | | | | Schematics indicate that the AVDD_HDMI_PLL supply should be enabled prior to the AVDD_HDMI supply. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: hdmi - Remove duplicate codeThierry Reding2014-06-05
| | | | | | | The generic Tegra output code already sets up the clocks properly, so there's no need to do it again when the HDMI output is enabled. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: hdmi - Add connector supply supportThierry Reding2014-06-05
| | | | | | | | | | | | | | | | | | | | | | | Revert commit 18ebc0f404d5 "drm/tegra: hdmi: Enable VDD earlier for hotplug/DDC" and instead add a new supply for the +5V pin on the HDMI connector. The vdd-supply property refers to the regulator that supplies the AVDD_HDMI input on Tegra, rather than the +5V HDMI connector pin. This was never a problem before, because all boards had that pin hooked up to a regulator that was always on. Starting with Dalmore and continuing with Venice2, the +5V pin is controllable via a GPIO. For reasons unknown, the GPIO ended up as the controlling GPIO of the AVDD_HDMI supply in the Dalmore and Venice2 DTS files. But that's not correct. Instead, a separate supply must be introduced so that the +5V pin can be controlled separately from the supplies that feed the HDMI block within Tegra. A new hdmi-supply property is introduced that takes the place of the vdd-supply and vdd-supply is only enabled when HDMI is enabled rather than all the time. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc - Use proper H/V ref-to-sync valuesThierry Reding2014-06-05
| | | | | | For HDMI compliance both of these values need to be set to 1. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc - Do not touch power control registerThierry Reding2014-06-05
| | | | | | | | Setting the bits in this register is dependent on the output type driven by the display controller. All output drivers already set these properly so there is no need to do it here again. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc - Reshuffle code to get rid of prototypesThierry Reding2014-06-05
| | | | | | | | The tegra_dc_format() and tegra_dc_setup_window() functions are only used internally by the display controller driver. Move them upwards in order to make them static and get rid of the function prototypes. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc - Rename INVERT_V to V_DIRECTIONThierry Reding2014-06-05
| | | | | | | V_DIRECTION is the name of the field in the documentation, so use that for consistency. Also add the H_DIRECTION field for completeness. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Add CRC debugfs supportThierry Reding2014-06-05
| | | | | | | | The SOR allows the computation of a 32 bit CRC of the content that it transmits. This functionality is exposed via debugfs and is useful to verify proper operation of the SOR. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc - Add YUYV supportThierry Reding2014-06-05
| | | | | | | | | | | | YUYV is UYVY with swapped bytes. Luckily the Tegra DC hardware can swap bytes during scan-out, so supporting YUYV is simply a matter of writing the correct value to the byteswap register. This patch modifies tegra_dc_format() to return the byte swap parameter via an output parameter in addition to returning the pixel format. Many other formats can potentially be supported in a similar way. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Cleanup header fileThierry Reding2014-06-05
| | | | | | | Remove extern keyword from function prototypes since it isn't needed and drop an unnecessary forward declaration. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm: add drm_fb_helper_restore_fbdev_mode_unlocked()Rob Clark2014-06-04
| | | | | | | | | All drm_fb_helper_restore_fbdev_mode() call sites, save one, do the same locking. Simplify this into drm_fb_helper_restore_fbdev_mode_unlocked(). Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/dp: add a hw mutex around the transfer functions. (v2)Dave Airlie2014-06-04
| | | | | | | | | This should avoid races between connector probing and HPD irqs in the future, currently mode_config.mutex blocks this possibility. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
* Merge branch 'drm-init-cleanup' of git://people.freedesktop.org/~danvet/drm ↵Dave Airlie2014-04-30
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next Next pull request, this time more of the drm de-midlayering work. The big thing is that his patch series here removes everything from drm_bus except the set_busid callback. Thierry has a few more patches on top of this to make that one optional to. With that we can ditch all the non-pci drm_bus implementations, which Thierry has already done for the fake tegra host1x drm_bus. Reviewed by Thierry, Laurent and David and now also survived some testing on my intel boxes to make sure the irq fumble is fixed correctly ;-) The last minute rebase was just to add the r-b tags from Thierry for the 2 patches I've redone. * 'drm-init-cleanup' of git://people.freedesktop.org/~danvet/drm: drm/<drivers>: don't set driver->dev_priv_size to 0 drm: Remove dev->kdriver drm: remove drm_bus->get_name drm: rip out dev->devname drm: inline drm_pci_set_unique drm: remove bus->get_irq implementations drm: pass the irq explicitly to drm_irq_install drm/irq: Look up the pci irq directly in the drm_control ioctl drm/irq: track the irq installed in drm_irq_install in dev->irq drm: rename dev->count_lock to dev->buf_lock drm: Rip out totally bogus vga_switcheroo->can_switch locking drm: kill drm_bus->bus_type drm: remove drm_dev_to_irq from drivers drm/irq: remove cargo-culted locking from irq_install/uninstall drm/irq: drm_control is a legacy ioctl, so pci devices only drm/pci: fold in irq_by_busid support drm/irq: simplify irq checks in drm_wait_vblank
| * drm: rip out dev->devnameDaniel Vetter2014-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was only ever used to pretty-print the irq driver name. And on kms systems due to set_version bonghits we never set up the prettier name, ever. Which make this a bit pointless. Also, we can always dig out the driver-instance/irq relationship through other means, so this isn't that useful. So just rip it out to simplify the set_version/set_busid insanity a bit. Also delete the temporary busname from drm_pci_set_busid, it's now unused. v2: Rebase on top of the new host1x drm_bus for tegra. Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm: kill drm_bus->bus_typeDaniel Vetter2014-04-22
| | | | | | | | | | | | | | | | | | | | | | | | Completely unused. Hooray, midlayer mistakes that didn't cause work to undo! v2: Rebase on top of the recent tegra changes which added a host1x drm bus. Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | Merge tag 'drm/tegra/for-3.15-rc3' of ↵Dave Airlie2014-04-27
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Fixes for v3.15-rc3 A single fix for some framebuffer reference counting fallout caused by the primary plane helpers introduced in 3.15-rc1. * tag 'drm/tegra/for-3.15-rc3' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: restrict plane loops to legacy planes
| * drm/tegra: restrict plane loops to legacy planesDaniel Vetter2014-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Matt Ropers primary plane series a set of prep patches like commit af2b653bfb4ef40931b4d101ca842ce0c5da57ef Author: Matt Roper <matthew.d.roper@intel.com> Date: Tue Apr 1 15:22:32 2014 -0700 drm/i915: Restrict plane loops to only operate on overlay planes (v2) ensured that all exisiting users of the mode_config->plane_list wouldn't change behaviour. Unfortunately tegra seems to have fallen through the cracks. Fix it. This regression was introduced in commit e13161af80c185ecd8dc4641d0f5df58f9e3e0af Author: Matt Roper <matthew.d.roper@intel.com> Date: Tue Apr 1 15:22:38 2014 -0700 drm: Add drm_crtc_init_with_planes() (v2) The result was that we've unref'ed the fb for the primary plane twice, leading to a use-after free bug. This is because the drm core will already set crtc->primary->fb to NULL and do the unref for us, and the crtc disable hook is called by the drm crtc helpers for exactly this case. Aside: Now that the fbdev helpers clean up planes there's no longer a need to do this in drivers. So this could probably be nuked entirely in linux-next. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | drm/tegra: dp: Support address-only I2C-over-AUX transactionsThierry Reding2014-04-08
|/ | | | | | | | Certain types of I2C-over-AUX transactions require that only the address is transferred. Detect this by looking at the AUX message's size and set the address-only bit appropriately. Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'drm/tegra/for-3.15-rc1' of ↵Dave Airlie2014-04-05
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v3.15-rc1 Implement eDP support for Tegra124 and support the PRIME vmap()/vunmap() operations. A symbol that is required for upcoming V4L2 support is now exported by the host1x driver. Relicense drivers under the GPL v2 for consistency. One exception is the public header file, which is relicensed under MIT to abide by the common rule. * tag 'drm/tegra/for-3.15-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: Use standard GPL v2 license text drm/tegra: Relicense under GPL v2 drm/tegra: Relicense public header under MIT drm/tegra: Add eDP support gpu: host1x: export host1x_syncpt_incr_max() function drm/tegra: prime: Add vmap support
| * drm/tegra: Use standard GPL v2 license textThierry Reding2014-04-04
| | | | | | | | | | | | | | Use the more canonical and concise variant of the GPL v2 license text. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: Relicense under GPL v2Thierry Reding2014-04-04
| | | | | | | | | | | | | | | | The majority of the code in this driver is licensed under the GPL v2, so relicense the rest under GPL v2 as well for consistency. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: Add eDP supportThierry Reding2014-04-04
| | | | | | | | | | | | | | Add support for eDP functionality found on Tegra124 and later SoCs. Only fast link training is currently supported. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: prime: Add vmap supportThierry Reding2014-04-04
| | | | | | | | | | | | | | This is trivial to support since all GEM objects are mapped into kernel space anyway. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | drm: Replace crtc fb with primary plane fb (v3)Matt Roper2014-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that CRTC's have a primary plane, there's no need to track the framebuffer in the CRTC. Replace all references to the CRTC fb with the primary plane's fb. This patch was generated by the Coccinelle semantic patching tool using the following rules: @@ struct drm_crtc C; @@ - (C).fb + C.primary->fb @@ struct drm_crtc *C; @@ - (C)->fb + C->primary->fb v3: Generate patch via coccinelle. Actual removal of crtc->fb has been moved to a subsequent patch. v2: Fixup several lingering crtc->fb instances that were missed in the first patch iteration. [Rob Clark] Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Rob Clark <robdclark@gmail.com>
* | Merge tag 'v3.14-rc7' into drm-nextDave Airlie2014-03-18
|\ \ | | | | | | | | | | | | | | | Linux 3.14-rc7 Backmerge to help out Intel guys.
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-14 09:23:55 -0400