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path: root/drivers/gpu/drm/msm
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* drm/msm/mdp5: fix incorrect parameter for msm_framebuffer_iova()Stephane Viau2015-05-21
| | | | | | | | | The index of ->planes[] array (3rd parameter) cannot be equal to MAX_PLANE. This looks like a typo that is now fixed. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Acked-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/msm: fix locking inconsistencies in gpu->destroy()Rob Clark2015-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In error paths, this was being called without struct_mutex held. Leading to panics like: msm 1a00000.qcom,mdss_mdp: No memory protection without IOMMU Kernel panic - not syncing: BUG! CPU: 0 PID: 1409 Comm: cat Not tainted 4.0.0-dirty #4 Hardware name: Qualcomm Technologies, Inc. APQ 8016 SBC (DT) Call trace: [<ffffffc000089c78>] dump_backtrace+0x0/0x118 [<ffffffc000089da0>] show_stack+0x10/0x20 [<ffffffc0006686d4>] dump_stack+0x84/0xc4 [<ffffffc0006678b4>] panic+0xd0/0x210 [<ffffffc0003e1ce4>] drm_gem_object_free+0x5c/0x60 [<ffffffc000402870>] adreno_gpu_cleanup+0x60/0x80 [<ffffffc0004035a0>] a3xx_destroy+0x20/0x70 [<ffffffc0004036f4>] a3xx_gpu_init+0x84/0x108 [<ffffffc0004018b8>] adreno_load_gpu+0x58/0x190 [<ffffffc000419dac>] msm_open+0x74/0x88 [<ffffffc0003e0a48>] drm_open+0x168/0x400 [<ffffffc0003e7210>] drm_stub_open+0xa8/0x118 [<ffffffc0001a0e84>] chrdev_open+0x94/0x198 [<ffffffc000199f88>] do_dentry_open+0x208/0x310 [<ffffffc00019a4c4>] vfs_open+0x44/0x50 [<ffffffc0001aa26c>] do_last.isra.14+0x2c4/0xc10 [<ffffffc0001aac38>] path_openat+0x80/0x5e8 [<ffffffc0001ac354>] do_filp_open+0x2c/0x98 [<ffffffc00019b60c>] do_sys_open+0x13c/0x228 [<ffffffc00019b72c>] SyS_openat+0xc/0x18 CPU1: stopping But there isn't any particularly good reason to hold struct_mutex for teardown, so just standardize on calling it without the mutex held and use the _unlocked() versions for GEM obj unref'ing Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Simplify the code to get the number of read byteHai Li2015-05-14
| | | | | | | | | | During cmd rx, only new versions of H/W provide register to read back the real number of byte returned by panel. For the old versions, reading this register will not get the right number. In fact, we only need to assume the returned data is the same size as we expected, because later we will check the data type to detect error. Signed-off-by: Hai Li <hali@codeaurora.org>
* drm/msm: Attach assigned encoder to eDP and DSI connectorsHai Li2015-05-14
| | | | | | | | | drm_mode_connector_attach_encoder() function call is missing during eDP and DSI connector initialization. As a result, no encoder is returned by DRM_IOCTL_MODE_GETCONNECTOR system call. This change is to fix this issue. Signed-off-by: Hai Li <hali@codeaurora.org>
* drm/msm: setup vram after component_bind_all()Rob Clark2015-05-14
| | | | | | | | First of all, we don't want -EPROBE_DEFER when trying to bind children to cause us to forget to free our vram. And second we don't want vram allocation fail to trigger _unbind_all() before _bind_all(). Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: use pr_err_ratelimitedRob Clark2015-05-14
| | | | | | | When things go badly we can get a lot of these error irqs. Let's not DoS the user. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: fix unbalanced DRM framebuffer init/destroyStephane Viau2015-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | | When msm_framebuffer_init() fails before calling drm_framebuffer_init(), drm_framebuffer_cleanup() [called in msm_framebuffer_destroy()] is still being called even though drm_framebuffer_init() was not called for that buffer. Thus a NULL pointer derefencing: [ 247.529691] Unable to handle kernel NULL pointer dereference at virtual address 0000027c ... [ 247.563996] PC is at __mutex_lock_slowpath+0x94/0x3a8 ... [ 247.823025] [<c07c3c78>] (__mutex_lock_slowpath) from [<c07c3fac>] (mutex_lock+0x20/0x3c) [ 247.831186] [<c07c3fac>] (mutex_lock) from [<c0347cf0>] (drm_framebuffer_cleanup+0x18/0x38) [ 247.839520] [<c0347cf0>] (drm_framebuffer_cleanup) from [<c036d138>] (msm_framebuffer_destroy+0x48/0x100) [ 247.849066] [<c036d138>] (msm_framebuffer_destroy) from [<c036d580>] (msm_framebuffer_init+0x1e8/0x228) [ 247.858439] [<c036d580>] (msm_framebuffer_init) from [<c036d630>] (msm_framebuffer_create+0x70/0x134) [ 247.867642] [<c036d630>] (msm_framebuffer_create) from [<c03493ec>] (internal_framebuffer_create+0x67c/0x7b4) [ 247.877537] [<c03493ec>] (internal_framebuffer_create) from [<c034ce34>] (drm_mode_addfb2+0x20/0x98) [ 247.886650] [<c034ce34>] (drm_mode_addfb2) from [<c034071c>] (drm_ioctl+0x240/0x420) [ 247.894378] [<c034071c>] (drm_ioctl) from [<c011df7c>] (do_vfs_ioctl+0x4e4/0x5a4) ... Signed-off-by: Stephane Viau <sviau@codeaurora.org> [plus initialize msm_fb to NULL to -Rob] Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Fix iteration on INTF config arrayStephane Viau2015-05-14
| | | | | | | | | | | | | | | | | | | | The current iteration in get_dsi_id_from_intf() is wrong: instead of iterating until hw_cfg->intf.count, we need to iterate until MDP5_INTF_NUM_MAX here. Let's take the example of msm8x16: hw_cfg->intf.count = 1 intfs[0] = INTF_Disabled intfs[1] = INTF_DSI If we stop iterating once i reaches hw_cfg->intf.count (== 1), we will miss the test for intfs[1]. Actually, this hw_cfg->intf.count entry is quite confusing and is not (or *should not be*) used anywhere else; let's remove it. Signed-off-by: Stephane Viau <sviau@codeaurora.org>
* drm/msm/dsi: Fixup missing *break* statement during cmd rxHai Li2015-05-14
| | | | Signed-off-by: Hai Li <hali@codeaurora.org>
* drm/msm/dp: fix error return codeJulia Lawall2015-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Return a negative error code on failure. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ identifier ret; expression e1,e2; @@ ( if (\(ret < 0\|ret != 0\)) { ... return ret; } | ret = 0 ) ... when != ret = e1 when != &ret *if(...) { ... when != ret = e2 when forall return ret; } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
* drm: msm: Fix build when legacy fbdev support isn't setArchit Taneja2015-05-14
| | | | | | | | | The DRM_KMS_FB_HELPER config is selected only when DRM_MSM_FBDEV config is selected. The driver accesses drm_fb_helper_* functions even when legacy fbdev support is disabled in msm. Wrap around these functions with #ifdef checks to prevent build break. Signed-off-by: Archit Taneja <architt@codeaurora.org>
* drm/msm/dsi: Fix a couple more 64-bit build warningsStephane Viau2015-05-14
| | | | | | | Avoid such errors at compilation time: format '%d' expects argument of type 'int', but argument 3 has type 'size_t' Signed-off-by: Stephane Viau <sviau@codeaurora.org>
* drm/msm: Fix a couple of 64-bit build warningsThierry Reding2015-05-14
| | | | | | | | | | Avoid casts from pointers to fixed-size integers to prevent the compiler from warning. Print virtual memory addresses using %p instead. Also turn a couple of %d/%x specifiers into %zu/%zd/%zx to avoid further warnings due to mismatched format strings. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Rob Clark <robdclark@gmail.com>
* Merge Linus master into drm-nextDave Airlie2015-04-19
|\ | | | | | | | | | | | | | | | | The merge is clean, but the arm build fails afterwards, due to API changes in the regulator tree. I've included the patch into the merge to fix the build. Signed-off-by: Dave Airlie <airlied@redhat.com>
| *-. Merge remote-tracking branches 'regulator/topic/mode', ↵Mark Brown2015-04-10
| |\ \ | | | | | | | | | | | | 'regulator/topic/notifier', 'regulator/topic/palmas', 'regulator/topic/qcom' and 'regulator/topic/stw481x' into regulator-next
| | * | regulator: fixes for regulator_set_optimum_mode name changeStephen Rothwell2015-03-10
| | |/ | | | | | | | | | | | | Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | drm/msm/mdp5: Enable DSI connector in msm drm driverHai Li2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds the support in mdp5 kms driver for single and dual DSI. Dual DSI case depends on the framework API and sequence change to support dual data path. v1: Initial change v2: Address Rob Clark's comment - Separate command mode encoder to a new file mdp5_cmd_encoder.c - Rebase to not depend on msm_drm_sub_dev change Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm: Initial add DSI connector supportHai Li2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds the DSI connector support in msm drm driver. v1: Initial change v2: - Address comments from Archit + minor clean-ups - Rebase to not depend on msm_drm_sub_dev change [Rob's comment] v3: Fix issues when initialization is failed Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm: Add split display interfaceHai Li2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | This change is to add an interface to MDP for connector devices setting split display information. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Move *_modeset_init out of construct_encoder functionHai Li2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is to make the content in construct_encoder reflect its name. Also, DSI connector may be connected to video mode or command mode encoder, so that 2 different encoders need to be constructed for DSI. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Remove CTL flush dummy bitsStephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | This TODO can now be removed and replaced by the previous patch "drm/msm/mdp5: Update headers (add CTL flush bits)" Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Update headers (add CTL flush bits)Stephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some upcoming targets have more bits to set in CTL_FLUSH registers. Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Add hardware configuration for msm8x16Stephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds the hw configuration for msm8x16 chipsets in mdp5_cfg module. Note that only one external display interface is present in this configuration (DSI) but has not been enabled yet. It will be enabled once drm/msm driver supports DSI connectors. v2: add CTL flush register's hardware mask [pointed by Archit] Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Get SMP client list from mdp5_cfgStephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SMP blocks are configured for specific client IDs (ports). These client IDs can be different from one chip to another for a given pipe. e.g.: DMA0 pipe fetch Y component is connected to: - port #10 for MDP5 v1.3 - port #4 for MDP5 v1.6 In order to be compatible for upcoming versions of MDP5, the client ID list is passed through the MDP5 config module rather than using a list of hard-coded enum values. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Update headers (remove enum mdp5_client_id)Stephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | This patch contains the generated header file of the following change "drm/msm/mdp5: Get SMP client list from mdp5_cfg". Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Separate MDP5 domain from MDSS domainStephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MDP block is actually contained inside the MDSS block. For some chipsets, the base address of the MDP registers is different from the current (assumed) 0x100 offset. Like CTL and LM blocks, this changes introduce a dynamic offset for the MDP instance, which can be found out at runtime, once the MDSS HW version is read. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Update headers (introduce MDP5 domain)Stephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | This change contains the generated header file for the following change "drm/msm/mdp5: Separate MDP5 domain from MDSS domain". Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/dsi: Update generated DSI header fileHai Li2015-04-01
| | | | | | | | | | | | | | | | | | | | | Prepare for initial DSI implementation Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Fix PIPE source image size settingsHai Li2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | The width and height in SSPP_SRC_IMG_SIZE register should be the size of the entire source framebuffer, not the fetch size. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Update generated mdp5 header file with DSI supportHai Li2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | This change adds the registers in mdp5 ping pong blocks and split display control registers. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Add pingpong entry to mdp5 config tableHai Li2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | Pingpong register base addresses are different across platforms. This change adds this information to config table and initialize the values for 8x74 and 8084. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Make the intf connection in config moduleStephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up until now, we assume that eDP is tight to intf_0 and HDMI to intf_3. This information shall actually come from the mdp5_cfg module since it can change from one chip to another. v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit] v3: add sanity check before writing in INTF_TIMING_ENGINE_EN registers Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Add START signal to kick off certain pipelinesStephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some interfaces (WB, DSI Command Mode) need to be kicked off through a START Signal. This signal needs to be sent at the right time and requests in some cases to keep track of the pipeline status (eg: whether pipeline registers are flushed AND output WB buffers are ready, in case of WB interface). Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Enhance operation mode for pipeline configurationStephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DSI and WB interfaces need a more complex pipeline configuration than the current mdp5_ctl_set_intf(). For example, memory output connections need to be selected for WB. Interface mode (Video vs. Command modes) also need to be configured for DSI. This change takes care of configuring the whole pipeline as far as operation mode goes. DSI and WB interfaces will be added later. v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit] Signed-off-by: Stephane Viau <sviau@codeaurora.org> [Remove temp bisectability hack -Rob] Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: Update generated header filesStephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare for pipeline operation mode configuration, in particular for DSI and WB modes. Signed-off-by: Stephane Viau <sviau@codeaurora.org> [Throw in a #define temporarily to keep things bisectable -Rob] Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/mdp5: only flush on a CRTC ->atomic_flush()Stephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MDP5 hardware has some limitation and requires to avoid flushing registers more than once between two Vblanks. This change removes all FLUSH operations (except for HW cursor) beside the one coming from a CRTC's ->atomic_flush(). This avoid this type of behavior (eg: CRTC + 1 plane overlay): [drm:mdp5_crtc_vblank_irq] vblank [drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0 [drm:mdp5_ctl_commit] flush (20040) CTL + LM0 [drm:mdp5_crtc_vblank_irq] blank [drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0 [drm:mdp5_crtc_vblank_irq] blank and replaces it by: [drm:mdp5_crtc_vblank_irq] vblank [drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0 [drm:mdp5_crtc_vblank_irq] blank [drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0 [drm:mdp5_crtc_vblank_irq] blank Only *one* FLUSH is called between Vblanks interrupts. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm/hdmi: add 74.176MHz and 154.0MHz pix clksRob Clark2015-04-01
| | | | | | | | | | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm: add support for "stolen" memRob Clark2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to use the VRAM carveout (if specified in dtb) for fbdev scanout buffer. This allows drm/msm to take over a bootloader splash- screen, and avoids corruption on screen that results if the kernel uses memory that is still being scanned out for itself. Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | drm/msm: split out vram initializationRob Clark2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | We'll want to extend this a bit to handle also a reserved-memory ("stolen") region, so that drm/msm can take-over bootloader splash screen. First split it out into it's own fxn to reduce noise in the following patch. Signed-off-by: Rob Clark <robdclark@gmail.com>
* | | Merge tag 'v4.0-rc3' into drm-nextDave Airlie2015-03-09
|\| | | | | | | | | | | | | | | | | | | | | | | | | | Linux 4.0-rc3 backmerge to fix two i915 conflicts, and get some mainline bug fixes needed for my testing box Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/intel_display.c
| * | drm/msm: kexec fixesRob Clark2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In kexec environment, we are more likely to encounter irq's already enabled from previous environment. At which point we find that writes to disable/clear pending irq's are slightly less than useless without first enabling clocks. TODO: full blown state read-in so kexec'd kernel can inherit the mode already setup. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * | drm/msm/mdp5: fix cursor blendingRob Clark2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | Seems like we just want BLEND_EN and not BLEND_TRANSP_EN (setting the latter results in black pixels in the cursor image treated as transparent). Signed-off-by: Rob Clark <robdclark@gmail.com>
| * | drm/msm/mdp5: fix cursor ROIRob Clark2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | If cursor is set near the edge of the screen, it is not valid to use the new cursor width/height as the ROI dimensions. Split out the ROI calc and use it both cursor_set and cursor_move. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * | drm/msm/atomic: Don't leak atomic commit object when commit failsLaurent Pinchart2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | If the atomic commit fails due to completion wait interruption the atomic commit object is not freed and is thus leaked. Free it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * | drm/msm/mdp5: Avoid flushing registers when CRTC is disabledStephane Viau2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a CRTC is disabled, no CTL is allocated to it (CRTC->ctl == NULL); in that case we should not try to FLUSH registers and do nothing instead. This can happen when we try to move a cursor but the CRTC's CTL (CONTROL) has not been allocated yet (inactive CRTC). It can also happens when we .atomic_check()/.atomic_flush() on a disabled CRTC. A CTL needs to be kept as long as the CRTC is alive. Releasing it after the last VBlank is safer than in .atomic_flush(). Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * | drm/msm: update generated headers (add 6th lm.base entry)Stephane Viau2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | Some target have up to 6 layer mixers (LM). Let the header file access the last LM's base address. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * | drm/msm/mdp5: fixup "drm/msm: fix fallout of atomic dpms changes"Stephane Viau2015-03-04
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0b776d457b94 ("drm/msm: fix fallout of atomic dpms changes") has a typo in both mdp5_encoder_helper_funcs and mdp5_crtc_helper_funcs definitions: .dpms entry should be replaced by .disable and .enable Also fixed a typo in mdp5_encoder_enable(). Note that these typos are only present for MDP5. MDP4 is fine. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | drm: Pass in new and old plane state to prepare_fb and cleanup_fbTvrtko Ursulin2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use cases like rotation require these hooks to have some context so they know how to prepare and cleanup the frame buffer correctly. For i915 specifically, object backing pages need to be mapped differently for different rotation modes and the driver needs to know which mapping to instantiate and which to tear down when transitioning between them. v2: Made passed in states const. (Daniel Vetter) [airlied: add mdp5 and atmel fixups] Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: dri-devel@lists.freedesktop.org Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/atomic-helper: Rename commmit_post/pre_planesDaniel Vetter2015-02-23
|/ | | | | | | | | | | | | | | | | | These names only make sense because of backwards compatability with the order used by the crtc helper library. There's not really any real requirement in the ordering here. So rename them to something more descriptive and update the kerneldoc a bit. Motivated in a discussion with Laurent about how to restore plane state for dpms for drivers with runtime pm. v2: Squash in fixup from Stephen Rothwell to fix a conflict with tegra. Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
* drm/msm: add moduleparam to disable fbdevRob Clark2015-02-01
| | | | | | | Useful to avoid recompiling to disable fbdev. Useful because otherwise the first modeset happens under console_lock (ie. debugging sadness). Signed-off-by: Rob Clark <robdclark@gmail.com>
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