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* | drm/i915: Reduce CHV DDL multiplier to 16/8Ville Syrjälä2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently we must yet halve the DDL drain latency from what we're using currently. This little nugget is not in any spec, but came down through the grapevine. This makes the displays a bit more stable. Not quite fully stable but at least they don't fall over immediately on driver load. v2: Update high_precision in valleyview_update_sprite_wm() too (Jesse) Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Disable the mmio.debug WARN after it firesChris Wilson2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we have a single unclaimed register, we will have lots. A WARN for each one makes the machine unusable and does not aid debugging. Convert the i915.mmio_debug option to a counter for how many WARNs to fire before shutting up. Even when i915.mmio_debug was disabled it would continue to shout an *ERROR* for every interrupt, without any information at all for debugging. The massive verbiage was added in commit 5978118c39c2f72fd8b39ef9c086723542384809 Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Wed Jul 16 17:49:29 2014 -0300 drm/i915: reorganize the unclaimed register detection code v2: Automatically enable invalid mmio reporting for the *next* invalid access if mmio_debug is disabled by default. This should give us clearer debug information without polluting the logs too much. v3: Compile fixes, rebase. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: Update modparam text per the thread.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: fix simple_return.cocci warningskbuild test robot2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | drivers/gpu/drm/i915/intel_ringbuffer.c:435:1-4: WARNING: end returns can be simpified Simplify a trivial if-return sequence. Possibly combine with a preceding function call. Generated by: scripts/coccinelle/misc/simple_return.cocci CC: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Do both mt and gen6 style forcewake reset on ivb probeMika Kuoppala2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 05a2fb157e44 ("drm/i915: Consolidate forcewake code") failed to take into account that we have used to reset both the gen6 style and the multithreaded style forcewake registers. This is due to fact that ivb can use either, depending on how the bios has set up the machine. Mimic the old semantics before we have determined the correct variety and reset both before the ecobus probe. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Huang Ying <ying.huang@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Remove ironlake rc6 supportJohn Harrison2015-03-17
| | | | | | | | | | | | | | | | | | | | | | Apparently, this has never worked reliably and is currently disabled. Also, the gains are not particularly impressive. Thus rather than try to keep unused code from decaying and having to update it for other driver changes, it was decided to simply remove it. For: VIZ-5115 Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Don't clobber plane state on internal disablesMatt Roper2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to disable all sprite planes when disabling the CRTC. We had been using the top-level atomic 'disable' entrypoint to accomplish this, which was wrong. Not only can this lead to various locking issues, it also modifies the actual plane state, making it impossible to restore the plane properly later. For example, a DPMS off followed by a DPMS on will result in any sprite planes in use not being restored properly. The proper solution here is to call directly into our 'commit plane' hook with a copy of the plane's current state that has 'visible' set to false. Committing this dummy state will turn off the plane, but will not touch the actual plane->state pointer, allowing us to properly restore the plane state later. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Setup all page directories for gen8Mika Kuoppala2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the requested size is less than what the full range of pdps can address, we end up setting pdps for only the requested area. The logical context however needs all pdp entries to be valid. Prior to commit 06fda602dbca ("drm/i915: Create page table allocators") we have been writing pdp entries with dma address of zero instead of valid pdps. This is supposedly bad even if those pdps are not addressed. As commit 06fda602dbca ("drm/i915: Create page table allocators") introduced more dynamic structure for pdps, we ended up oopsing when we populated the lrc context. Analyzing this oops revealed the fact that we have not been writing valid pdps with bsw, as it is doing the ppgtt init with 2GB limit in some cases. We should do the right thing and setup the non addressable part pdps/pde/pte to scratch page through the minimal structure by having just pdp with pde entries pointing to same page with pte entries pointing to scratch page. But instead of going through that trouble, setup all the pdps through individual pd pages and pt entries, even for non addressable parts. And let the clear range point them to scratch page. This way we populate the lrc with valid pdps and wait for dynamic page allocation work to land, and do the heavy lifting for truncating page table tree according to usage. The regression of oopsing in init was introduced by commit 06fda602dbca ("drm/i915: Create page table allocators") v2: Clear the range for the unused part also (Ville) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89350 Cc: Michel Thierry <michel.thierry@intel.com> Cc: Ben Widawsky <benjamin.widawsky@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Valtteri Rantala <valtteri.rantala@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915/skl: Program PLL for edp1.4 intermediate frequenciesSonika Jindal2015-03-17
| | | | | | | | | | | | | | | | | | v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros (Ville) Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915/skl: Add support for edp 1.4 intermediate frequenciesSonika Jindal2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eDp 1.4 supports custom frequencies. Skylake supports following intermediate frequencies : 3.24 GHz, 2.16 GHz and 4.32 GHz along with usual LBR, HBR and HBR2 frequencies. Read sink supported frequencies and get common frequencies from sink and source and use these for link training. v2: Rebased, removed calculation of min_clock since for edp it is taken as max_clock (as per comment). v3: Keeping single array for link rates (Satheesh) v4: Setting LINK_BW_SET to 0 when setting LINK_RATE_SET (Satheesh) v5: Some minor nits (Ville) v6: Keeping separate arrays for source and sink rates (Ville) v7: Remove redundant setting of DP_LINK_BW_SET to 0 (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915/skl: Read sink supported rates from edp panelSonika Jindal2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: Using DP_SUPPORTED_LINK_RATES macro for supported_rates array (Satheesh). v3: Reading dpcd's supported link rates tables based upon edp version in the same patch. v4: Move version check under is_edp (Satheesh) v5: Using le16 for rates, some naming, and removing nested if block (Ville) v6: Correctly using DP_MAX_SUPPORTED_RATES and removing DP_SUPPORTED_LINK_RATES (Ville) v7: Incorrectly removed DP_SUPPORTED_LINK_RATES in v6, re-adding it v8: Checking return value of intel_dp_dpcd_read_wake() (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: add frontbuffer tracking to FBCPaulo Zanoni2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kill the blt/render tracking we currently have and use the frontbuffer tracking infrastructure. Don't enable things by default yet. v2: (Rodrigo) Fix small conflict on rebase and typo at subject. v3: (Paulo) Rebase on RENDER_CS change. v4: (Paulo) Rebase. v5: (Paulo) Simplify: flushes don't have origin (Daniel). Also rebase due to patch order changes. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Fixing mutex deadlock window at eDP DRRSRamalingam C2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In invalidate and flush functions of eDP DRRS, if deferred downclock work starts execution at a time window between acquiring the drrs mutex and cancellation of the deferred work (intel_edp_drrs_downclock_work), then deferred work will find drrs mutex locked and wait for the same. Meanwhile the function that acquired mutex drrs invalidate/flush will wait for the completion of the deferred work before releasing the mutex. Thats a deadlock. To avoid such deadlock scenario, this change cancels the deferred work before acquiring the mutex at invalidate and flush functions. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Add debugfs entry for DRRSVandana Kannan2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding a debugfs entry to determine if DRRS is supported or not V2: [By Ram]: Following details about the active crtc will be filled in seq-file of the debugfs 1. Encoder output type 2. DRRS Support on this CRTC 3. DRRS current state 4. Current Vrefresh Format is as follows: CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR, Vrefresh: 60 CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR, Vrefresh: 40 CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless V3: [By Ram]: Readability is improved. Another error case is covered [Daniel] V4: [By Ram]: Current status of the Idleness DRRS along with the Front buffer bits are added to the debugfs. [Rodrigo] V5: [By Ram]: Rephrased to make it easy to understand. And format is modified. [Rodrigo] V6: [By Ram]: Modeset mutex are acquired for each crtc along with renaming the Idleness detection states [Daniel] Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> [danvet: dump full busy_frontbuffer_bits and remove the dubios computed logical state of DRRS - debugfs is about what is fact, developers should reach their own conclusion when debugging issues.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Add I915_PARAM_REVISIONNeil Roberts2015-03-17
| | | | | | | | | | | | | | | | | | | | Adds a parameter which can be used with DRM_I915_GETPARAM to query the GPU revision. The intention is to use this in Mesa to implement the WaDisableSIMD16On3SrcInstr workaround on Skylake but only for revision 2. Signed-off-by: Neil Roberts <neil@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Improve staged config loggingAnder Conselvan de Oliveira2015-03-17
| | | | | | | | | | | | | | | | | | When logging that full mode switch is necessary, log which connector, encoder or crtc has caused it, so it is easier to figure out what is goind on by just looking at the log. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Add a for_each_intel_connector macroAnder Conselvan de Oliveira2015-03-17
| | | | | | | | | | | | | | | | We have similar macros for crtcs and encoders, and the pattern happens often enough to justify the macro. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Set crtc backpointer when duplicating crtc stateAnder Conselvan de Oliveira2015-03-17
| | | | | | | | | | | | | | | | In the path were there is no state to duplicate, the allocated crtc state wouldn't have the crtc backpointer initialized. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Reduce CHV DPLL min vco frequency to 4.8 GHzVille Syrjälä2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current minimum vco frequency leaves us with a gap in our supported frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a pixel clock of 241.5 MHz, which is just withing that gap. Reduce the allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz, and thus allow such displays to work. 4.8 GHz is actually the documented (at least in some docs) limit of the PLL, and we just picked 4.86 GHz originally because that was the lowest value produced by the PLL spreadsheet, which obviously didn't consider 2560x1440 displays. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: also do frontbuffer tracking on pwritesPaulo Zanoni2015-03-17
| | | | | | | | | | | | | | | | | | | | We need this for FBC, and possibly for PSR too. v2: Don't only flush: invalidate too (Daniel). Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: pass which operation triggered the frontbuffer trackingPaulo Zanoni2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to port FBC to the frontbuffer tracking infrastructure, but for that we need to know what caused the object invalidation so we can react accordingly: CPU mmaps need manual, GTT mmaps and flips don't need handling and ring rendering needs nukes. v2: - s/ORIGIN_RENDER/ORIGIN_CS/ (Daniel, Rodrigo) - Fix copy/pasted wrong documentation - Rebase v3: - Rebase v4: - Don't pass the operation to flushes (Daniel). Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | Revert "drm/i915: Switch planes from transitional helpers to full atomic ↵Daniel Vetter2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | helpers" This reverts commit 3f678c96abb43a977d2ea41aefccdc49e8a3e896. We've been a bit too optimistic with this one here :( The trouble is that internally we're still using these plane update/disable hooks. Which was totally ok pre-atomic since the drm core did all the book-keeping updating and these just mostly updated hw state. But with atomic there's lots more going on, and it causes heaps of trouble with the load detect code. This one specifically cause a deadlock since both the load detect code and the nested plane atomic helper functions tried to grab the same locks. It only blows up because of the evil tricks though we play with the implicit ww acquire context. Applying this revert unearths the NULL deref on already freed framebuffer objects reported as a regression in 4.0 by various people. Fixing this will be fairly invasive, hence revert even for the 4.1-next queue. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Paul Bolle <pebolle@tiscali.nl> Acked-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
* | drm/i915/skl: Only use the 800mV+2bB HDMI translation entryDamien Lespiau2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This translation entry was updated after electrical validation by the hw team. The other entries are removed from existence as they aren't validated and because the sole use of a certain type of level shifter for SKL products is anticipated. v2: Remove all the other entries and force the use of the 800mv+2dB config (Sonika) Suggested-by: Sonika Jindal <sonika.jindal@intel.com> Cc: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Make for_each_sprite() take dev_priv as argumentDamien Lespiau2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | Implicit usage of local variables in macros isn't exactly the greatest thing in the world, especially when that variable is the drm device and we want to move towards a broader use of the i915 device structure. Let's make for_each_sprite() take dev_priv as its first argument then. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Chris Wilson <chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Make for_each_plane() take dev_priv as argumentDamien Lespiau2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | Implicit usage of local variables in macros isn't exactly the greatest thing in the world, especially when that variable is the drm device and we want to move towards a broader use of the i915 device structure. Let's make for_each_plane() take dev_priv as its first argument then. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Chris Wilson <chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Remove irq-related FIXME in reset codeDaniel Vetter2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the two-step reset counter increments which braket the actual reset code and the subsequent wake-up we're guaranteeing that all the lockless waiters _will_ be woken up. And since we unconditionally bail out of waits with -EAGAIN (or -EIO) in that case there is not risk of lost interrupt enabling bits when the lockless wait code races against a gpu reset. Let's remove this FIXME as resolved then. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Fix trivial typos in comments and warning messageYannick Guerrini2015-03-17
| | | | | | | | | | | | | | | | | | Change 'mutliple' to 'multiple' Change 'mutlipler' to 'multiplier' Change 'Haswel' to 'Haswell' Signed-off-by: Yannick Guerrini <yguerrini@tomshardware.fr> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Use plane->state->fb in watermark code (v2)Matt Roper2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | plane->fb is a legacy pointer that not always be up-to-date (or updated early enough). Make sure the watermark code uses plane->state->fb so that we're always doing our calculations based on the correct framebuffers. This patch was generated by Coccinelle with the following semantic patch: @@ struct drm_plane *P; @@ - P->fb + P->state->fb v2: Rebase Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Kill intel_crtc->cursor_{width, height} (v2)Matt Roper2015-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cursor size fields in intel_crtc just duplicate the data from cursor->state.crtc_{w,h} so we don't need them any more. Worse, their use in the watermark code actually introduces a subtle bug since they don't get updated to mirror the state values until the plane commit stage, which is *after* we've already used them to calculate new watermark values. This happens because we had to move watermark updates slightly earlier (outside vblank evasion) in commit commit 32b7eeec4d1e861230b09d437e95d76c86ff4a68 Author: Matt Roper <matthew.d.roper@intel.com> Date: Wed Dec 24 07:59:06 2014 -0800 drm/i915: Refactor work that can sleep out of commit (v7) Dropping the intel_crtc fields and just using the state values (which are properly updated by the time watermark updates happen) should solve the problem. Aside from the actual removal of the struct fields (which are formatted in a way that I couldn't figure out how to match in Coccinelle), the rest of this patch was generated via the following semantic patch: // Drop assignment @@ struct intel_crtc *C; struct drm_plane_state S; @@ ( - C->cursor_width = S.crtc_w; | - C->cursor_height = S.crtc_h; ) // Replace usage @@ struct intel_crtc *C; expression E; @@ ( - C->cursor_width + C->base.cursor->state->crtc_w | - C->cursor_height + C->base.cursor->state->crtc_h | - to_intel_crtc(E)->cursor_width + E->cursor->state->crtc_w | - to_intel_crtc(E)->cursor_height + E->cursor->state->crtc_h ) v2: Rebase Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Joe Konno <joe.konno@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89346 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Rotation property is now handled in DRM coreTvrtko Ursulin2015-03-10
| | | | | | | | | | | | | | | | | | | | So no need to have code which never gets called in the driver. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: dri-devel@lists.freedesktop.org Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Fix struct_mutex deadlock due to merge fumbleVille Syrjälä2015-03-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit a8c6ecb3be7029881f7c95e5e201a629094a4e1a Merge: 8dd0eb35 9eccca0 Author: Dave Airlie <airlied@redhat.com> Date: Mon Mar 9 19:58:30 2015 +1000 Merge tag 'v4.0-rc3' into drm-next managed to pick the wrong code to resolve the conflict and left us with a mutex_lock(struct_mutex) without the mutex_unlock(struct_mutex) leading to a deadlock. Fix the problem by recovering the correct code which doesn't need the lock. Cc: Dave Airlie <airlied@redhat.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | Merge tag 'v4.0-rc3' into drm-nextDave Airlie2015-03-09
|\| | | | | | | | | | | | | | | | | Linux 4.0-rc3 backmerge to fix two i915 conflicts, and get some mainline bug fixes needed for my testing box Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/intel_display.c
| * Merge tag 'drm-intel-fixes-2015-03-05' of ↵Dave Airlie2015-03-06
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm-intel into drm-fixes two fixes, both cc'd stable. * tag 'drm-intel-fixes-2015-03-05' of git://anongit.freedesktop.org/drm-intel: drm/i915: gen4: work around hang during hibernation drm/i915: Check for driver readyness before handling an underrun interrupt
| | * drm/i915: gen4: work around hang during hibernationImre Deak2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bjørn reported that his machine hang during hibernation and eventually bisected the problem to the following commit: commit da2bc1b9db3351addd293e5b82757efe1f77ed1d Author: Imre Deak <imre.deak@intel.com> Date: Thu Oct 23 19:23:26 2014 +0300 drm/i915: add poweroff_late handler The problem seems to be that after the kernel puts the device into D3 the BIOS still tries to access it, or otherwise assumes that it's in D0. This is clearly bogus, since ACPI mandates that devices are put into D3 by the OSPM if they are not wake-up sources. In the future we want to unify more of the driver's runtime and system suspend paths, for example by skipping all the system suspend/hibernation hooks if the device is runtime suspended already. Accordingly for all other platforms the goal is still to properly power down the device during hibernation. v2: - Another GEN4 Lenovo laptop had the same issue, while platforms from other vendors (including mobile and desktop, GEN4 and non-GEN4) seem to work fine. Based on this apply the workaround on all GEN4 Lenovo platforms. - add code comment about failing platforms (Ville) Reference: http://lists.freedesktop.org/archives/intel-gfx/2015-February/060633.html Reported-and-bisected-by: Bjørn Mork <bjorn@mork.no> Cc: stable@vger.kernel.org # v3.19 Signed-off-by: Imre Deak <imre.deak@intel.com> Acked-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| | * drm/i915: Check for driver readyness before handling an underrun interruptChris Wilson2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we takeover from the BIOS and install our interrupt handler, the BIOS may have left us a few surprises in the form of spontaneous interrupts. (This is especially likely on hardware like 965gm where display fifo underruns are continuous and the GMCH cannot filter that interrupt souce.) As we enable our IRQ early so that we can use it during hardware probing, our interrupt handler must be prepared to handle a few sources prior to being fully configured. As such, we need to add a simple is-ready check prior to dereferencing our KMS state for reporting underruns. Reported-by: Rob Clark <rclark@redhat.com> Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1193972 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: stable@vger.kernel.org [Jani: dropped the extra !] Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| * | Merge tag 'v4.0-rc2' into drm-fixesDave Airlie2015-03-06
| |\| | | | | | | | | | | | | | | | | | | Linux 4.0-rc2 Merging this manually as the i915 change is in it, and intel fixes are on top of this
| | * drm/i915: Fix modeset state confusion in the load detect codeDaniel Vetter2015-03-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a tricky story of the new atomic state handling and the legacy code fighting over each another. The bug at hand is an underrun of the framebuffer reference with subsequent hilarity caused by the load detect code. Which is peculiar since the the exact same code works fine as the implementation of the legacy setcrtc ioctl. Let's look at the ingredients: - Currently our code is a crazy mix of legacy modeset interfaces to set the parameters and half-baked atomic state tracking underneath. While this transition is going we're using the transitional plane helpers to update the atomic side (drm_plane_helper_disable/update and friends), i.e. plane->state->fb. Since the state structure owns the fb those functions take care of that themselves. The legacy state (specifically crtc->primary->fb) is still managed by the old code (and mostly by the drm core), with the fb reference counting done by callers (core drm for the ioctl or the i915 load detect code). The relevant commit is commit ea2c67bb4affa84080c616920f3899f123786e56 Author: Matt Roper <matthew.d.roper@intel.com> Date: Tue Dec 23 10:41:52 2014 -0800 drm/i915: Move to atomic plane helpers (v9) - drm_plane_helper_disable has special code to handle multiple calls in a row - it checks plane->crtc == NULL and bails out. This is to match the proper atomic implementation which needs the crtc to get at the implied locking context atomic updates always need. See commit acf24a395c5a9290189b080383564437101d411c Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Tue Jul 29 15:33:05 2014 +0200 drm/plane-helper: transitional atomic plane helpers - The universal plane code split out the implicit primary plane from the CRTC into it's own full-blown drm_plane object. As part of that the setcrtc ioctl (which updated both the crtc mode and primary plane) learned to set crtc->primary->crtc on modeset to make sure the plane->crtc assignments statate up to date in commit e13161af80c185ecd8dc4641d0f5df58f9e3e0af Author: Matt Roper <matthew.d.roper@intel.com> Date: Tue Apr 1 15:22:38 2014 -0700 drm: Add drm_crtc_init_with_planes() (v2) Unfortunately we've forgotten to update the load detect code. Which wasn't a problem since the load detect modeset is temporary and always undone before we drop the locks. - Finally there is a organically grown history (i.e. don't ask) around who sets the legacy plane->fb for the various driver entry points. Originally updating that was the drivers duty, but for almost all places we've moved that (plus updating the refcounts) into the core. Again the exception is the load detect code. Taking all together the following happens: - The load detect code doesn't set crtc->primary->crtc. This is only really an issue on crtcs never before used or when userspace explicitly disabled the primary plane. - The plane helper glue code short-circuits because of that and leaves a non-NULL fb behind in plane->state->fb and plane->fb. The state fb isn't a real problem (it's properly refcounted on its own), it's just the canary. - Load detect code drops the reference for that fb, but doesn't set plane->fb = NULL. This is ok since it's still living in that old world where drivers had to clear the pointer but the core/callers handled the refcounting. - On the next modeset the drm core notices plane->fb and takes care of refcounting it properly by doing another unref. This drops the refcount to zero, leaving state->plane now pointing at freed memory. - intel_plane_duplicate_state still assume it owns a reference to that very state->fb and bad things start to happen. Fix this all by applying the same duct-tape as for the legacy setcrtc ioctl code and set crtc->primary->crtc properly. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Paul Bolle <pebolle@tiscali.nl> Cc: Rob Clark <robdclark@gmail.com> Cc: Paulo Zanoni <przanoni@gmail.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Matt Roper <matthew.d.roper@intel.com> Reported-and-tested-by: Linus Torvalds <torvalds@linux-foundation.org> Reported-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | drm/mm: Support 4 GiB and larger rangesThierry Reding2015-03-04
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation is limited by the number of addresses that fit into an unsigned long. This causes problems on 32-bit Tegra where unsigned long is 32-bit but drm_mm is used to manage an IOVA space of 4 GiB. Given the 32-bit limitation, the range is limited to 4 GiB - 1 (or 4 GiB - 4 KiB for page granularity). This commit changes the start and size of the range to be an unsigned 64-bit integer, thus allowing much larger ranges to be supported. [airlied: fix i915 warnings and coloring callback] Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Dave Airlie <airlied@redhat.com> fixupo
| * drm/i915: Fix frontbuffer false positve.Rodrigo Vivi2015-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This return 0 without setting atomic bits on fb == crtc->cursor->fb where causing frontbuffer false positives. According to Daniel: The original regression seems to have been introduced in the original check/commit split: commit 757f9a3e5b8a812af0c213099a5b31cb423f4d3c Author: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Date: Wed Sep 24 14:20:24 2014 -0300 drm/i915: move check of intel_crtc_cursor_set_obj() out Which already cause other trouble, resulting in the check getting moved in commit e391ea882b1a04fb3f559287ac694652a3cd9da9 Author: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Date: Wed Sep 24 14:20:25 2014 -0300 drm/i915: Fix not checking cursor and object sizes The frontbuffer tracking itself only was broken when we shifted it into the check/commit logic with: commit 32b7eeec4d1e861230b09d437e95d76c86ff4a68 Author: Matt Roper <matthew.d.roper@intel.com> Date: Wed Dec 24 07:59:06 2014 -0800 drm/i915: Refactor work that can sleep out of commit (v7) v2: When putting more debug prints I notice the solution was simpler than I thought. AMS design is solid, just this return was wrong. Sorry for the noise. v3: Remove the entire chunck that would probably be removed by gcc anyway. (by Daniel) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| * drm/i915: Align initial plane backing objects correctlyDaniel Vetter2015-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some bios really like to joke and start the planes at an offset ... hooray! Align start and end to fix this. v2: Fixup calculation of size, spotted by Chris Wilson. v3: Fix serious fumble I've just spotted. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86883 Cc: stable@vger.kernel.org Cc: Johannes W <jargon@molb.org> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@linux.intel.com> Reported-and-tested-by: Johannes W <jargon@molb.org> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> [Jani: split WARN_ONs, rebase on v4.0-rc1] Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| * drm/i915: avoid processing spurious/shared interrupts in low-power statesImre Deak2015-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Atm, it's possible that the interrupt handler is called when the device is in D3 or some other low-power state. It can be due to another device that is still in D0 state and shares the interrupt line with i915, or on some platforms there could be spurious interrupts even without sharing the interrupt line. The latter case was reported by Klaus Ethgen using a Lenovo x61p machine (gen 4). He noticed this issue via a system suspend/resume hang and bisected it to the following commit: commit e11aa362308f5de467ce355a2a2471321b15a35c Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Wed Jun 18 09:52:55 2014 -0700 drm/i915: use runtime irq suspend/resume in freeze/thaw This is a problem, since in low-power states IIR will always read 0xffffffff resulting in an endless IRQ servicing loop. Fix this by handling interrupts only when the driver explicitly enables them and so it's guaranteed that the interrupt registers return a valid value. Note that this issue existed even before the above commit, since during runtime suspend/resume we never unregistered the handler. v2: - clarify the purpose of smp_mb() vs. synchronize_irq() in the code comment (Chris) v3: - no need for an explicit smp_mb(), we can assume that synchronize_irq() and the mmio read/writes in the install hooks provide for this (Daniel) - remove code comment as the remaining synchronize_irq() is self explanatory (Daniel) v4: - drm_irq_uninstall() implies synchronize_irq(), so no need to call it explicitly (Daniel) Reference: https://lkml.org/lkml/2015/2/11/205 Reported-and-bisected-by: Klaus Ethgen <Klaus@Ethgen.ch> Cc: stable@vger.kernel.org Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| * drm/i915: Check obj->vma_list under the struct_mutexChris Wilson2015-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we walk the list of vma, or even for protecting against concurrent framebuffer creation, we must hold the struct_mutex or else a second thread can corrupt the list as we walk it. Fixes regression from commit d7f46fc4e7323887494db13f063a8e59861fefb0 Author: Ben Widawsky <benjamin.widawsky@intel.com> Date: Fri Dec 6 14:10:55 2013 -0800 drm/i915: Make pin count per VMA References: https://bugs.freedesktop.org/show_bug.cgi?id=89085 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: stable@vger.kernel.org Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| * drm/i915: Fix a use after free, and unbalanced refcountingNick Hoath2015-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When converting from implicitly tracked execlist queue items to ref counted requests, not all frees of requests were replaced with unrefs, and extraneous refs/unrefs of contexts were added. Correct the unbalanced refcount & replace the frees. Remove a noisy warning when hitting the request creation path. drm_i915_gem_request and intel_context are both kref reference counted structures. Upon allocation, drm_i915_gem_request's ref count should be bumped using kref_init. When a context is assigned to the request, the context's reference count should be bumped using i915_gem_context_reference. i915_gem_request_reference will reduce the context reference count when the request is freed. Problem introduced in commit 6d3d8274bc45de4babb62d64562d92af984dd238 Author: Nick Hoath <nicholas.hoath@intel.com> AuthorDate: Thu Jan 15 13:10:39 2015 +0000 drm/i915: Subsume intel_ctx_submit_request in to drm_i915_gem_request v2: Added comments explaining how the ctx pointer and the request object should be ref-counted. Removed noisy warning. v3: Cleaned up the language used in the commit & the header description (Thanks David Gordon) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88652 Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> Reviewed-by: Thomas Daniel <thomas.daniel@intel.com> Reviewed-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| * drm/i915: Dell Chromebook 11 has PWM backlightJani Nikula2015-02-23
| | | | | | | | | | | | | | | | | | | | Add quirk for Dell Chromebook 11 backlight. Reported-and-tested-by: Owen Garland <garland.owen@gmail.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=93451 Acked-by: Damien Lespiau <damien.lespiau@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| * drm/i915/skl: handle all pixel formats in skylake_update_primary_plane()Jani Nikula2015-02-23
| | | | | | | | | | | | | | | | | | skylake_update_primary_plane() did not handle all pixel formats returned by skl_format_to_fourcc(). Handle alpha similar to skl_update_plane(). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89052 Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| * drm/i915/bdw: PCI IDs ending in 0xb are ULT.Rodrigo Vivi2015-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | When reviewing patch that fixes VGA on BDW Halo Jani noticed that we also had other ULT IDs that weren't listed there. So this follow-up patch add these pci-ids as halo and fix comments on i915_pciids.h Cc: Jani Nikula <jani.nikula@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
* | Merge tag 'drm-intel-next-2015-02-27' of ↵Dave Airlie2015-03-09
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm-intel into drm-next - Y tiling support for scanout from Tvrtko&Damien - Remove more UMS support - some small prep patches for OLR removal from John Harrison - first few patches for dynamic pagetable allocation from Ben Widawsky, rebased by tons of other people - DRRS support patches (Sonika&Vandana) - fbc patches from Paulo - make sure our vblank callbacks aren't called when the pipes are off - various patches all over * tag 'drm-intel-next-2015-02-27' of git://anongit.freedesktop.org/drm-intel: (61 commits) drm/i915: Update DRIVER_DATE to 20150227 drm/i915: Clarify obj->map_and_fenceable drm/i915/skl: Allow Y (and Yf) frame buffer creation drm/i915/skl: Update watermarks for Y tiling drm/i915/skl: Updated watermark programming drm/i915/skl: Adjust get_plane_config() to support Yb/Yf tiling drm/i915/skl: Teach pin_and_fence_fb_obj() about Y tiling constraints drm/i915/skl: Adjust intel_fb_align_height() for Yb/Yf tiling drm/i915/skl: Allow scanning out Y and Yf fbs drm/i915/skl: Add new displayable tiling formats drm/i915: Remove DRIVER_MODESET checks from modeset code drm/i915: Remove regfile code&data for UMS suspend/resume drm/i915: Remove DRIVER_MODESET checks from gem code drm/i915: Remove DRIVER_MODESET checks in the gpu reset code drm/i915: Remove DRIVER_MODESET checks from suspend/resume code drm/i915: Remove DRIVER_MODESET checks in load/unload/close code drm/i915: fix a printk format drm/i915: Add media rc6 residency file to sysfs drm/i915: Add missing description to parameter in alloc_pt_range drm/i915: Removed the read of RP_STATE_CAP from sysfs/debugfs functions ...
| * | drm/i915: Update DRIVER_DATE to 20150227Daniel Vetter2015-02-27
| | | | | | | | | | | | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Clarify obj->map_and_fenceableChris Wilson2015-02-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For an object right on the boundary of mappable space, as the fenceable size is stricly greater than the actual size, its fence region may extend out of mappable space. Note that only pnv/g33 has fence_size > obj.size and an unmappable range in the gtt, and there alignment constraints prevent bad things from happening. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Clarify why this shouldn't change anything as per the discussion on intel-gfx.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915/skl: Allow Y (and Yf) frame buffer creationTvrtko Ursulin2015-02-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By this patch all underlying bits have been implemented and this patch actually enables the feature. v2: Validate passed in fb modifiers to reject garbage. (Daniel Vetter) v3: Rearrange validation checks per code review comments. (Daniel Vetter) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> (v1) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915/skl: Update watermarks for Y tilingTvrtko Ursulin2015-02-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Display watermarks need different programming for different tiling modes. Set the relevant flag so this happens during the plane commit and add relevant data into a structure made available to the watermark computation code. v2: Pass in tiling info to sprite plane updates as well. v3: Rebased for plane handling changes. v4: Handle fb == NULL when plane is disabled. v5: Refactored for addfb2 interface. v6: Refactored for fb modifier changes. v7: Updated for atomic commit by only updating watermarks when tiling changes. v8: BSpec watermark calculation updates. v9: Restrict scope of y_tile_minimum variable. (Damien Lespiau) v10: Get fb from plane state otherwise we are working on old state. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Acked-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Acked-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> (v9) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-11 15:31:16 -0400