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* | drm/i915: Remove redundant bit shifting from intel_gmbus_set_speedAdam Jackson2011-10-20
| | | | | | | | | | | | Signed-off-by: Adam Jackson <ajax@redhat.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Rename intel_sdvo_hdmi_sink_detectAdam Jackson2011-10-20
| | | | | | | | | | | | | | | | This is general TMDS detect, not HDMI specifically. Signed-off-by: Adam Jackson <ajax@redhat.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Fix multifunction SDVO detectionAdam Jackson2011-10-20
| | | | | | | | | | | | | | | | | | I can't think of any sensible reason to limit this to a mask of 0x0f, ie, SDVO_OUTPUT_{TMDS,RGB,CVBS,SVID}0. Signed-off-by: Adam Jackson <ajax@redhat.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Remove "i2c_speed" nonsense from child device tableAdam Jackson2011-10-20
| | | | | | | | | | | | | | | | | | | | I have no evidence for this byte being used this way, and lots of counterexamples. Restore the struct to its empirical definition and patch up gmbus setup to match. Signed-off-by: Adam Jackson <ajax@redhat.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* | Merge branch 'fix-pch-refclk' into fooKeith Packard2011-10-20
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| * | drm/i915: Initialize PCH refclks at modeset init timeKeith Packard2011-09-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reference clock configuration must be done before any mode setting can occur as all outputs must be disabled to change anything. Initialize the clocks after turning everything off during the initialization process. Also, re-initialize the refclk at resume time. Signed-off-by: Keith Packard <keithp@keithp.com>
| * | drm/i915: All PCH refclks are 120MHzKeith Packard2011-09-28
| | | | | | | | | | | | | | | | | | | | | | | | I can't find any reference clocks which run at 96MHz as seems to be indicated from the comments in this code. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | drm/i915: Use CK505 as non-SSC source where availableKeith Packard2011-09-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When trying to use SSC on Ibex Peak without CK505, any non-SSC outputs (like VGA or TV) get broken. So, do not use SSC on Ibex Peak unless there is a CK505 available (as specified by the VBT). On Cougar Point, all clocking is internal, so SSC can always be used, and there will never be a CK505 available. This eliminates VGA shimmer on some Ironlake machines which have a CK505 clock source. References: https://bugzilla.kernel.org/show_bug.cgi?id=21742 References: https://bugs.freedesktop.org/show_bug.cgi?id=38750 Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | drm/i915: Fix PCH SSC reference clock settingsKeith Packard2011-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCH refclk settings are global, so we need to look at all of the encoders, not just the current encoder when deciding how to configure it. Also, handle systems with more than one panel (any combination of PCH/non-PCH eDP and LVDS). Disable SSC clocks when no panels are connected. Signed-off-by: Keith Packard <keithp@keithp.com>
| * | drm/i915: Allow SSC parameter to override VBT valueKeith Packard2011-09-27
| | | | | | | | | | | | | | | | | | | | | Allow SSC to be enabled even when the BIOS disables it for testing SSC paths. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | drm/i915: Document a few more BDB_GENERAL_FEATURES bits from PCH BIOSKeith Packard2011-09-27
| | | | | | | | | | | | | | | | | | | | | This includes whether an eDP panel is present, and whether that should use SSC (and at what frequency) Signed-off-by: Keith Packard <keithp@keithp.com>
| * | drv/i915: Pull display_clock_mode out of VBT tableKeith Packard2011-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | This tells the driver whether a CK505 clock source is available on pre-PCH hardware. If so, it should be used as the non-SSC source, leaving the internal clock for use as the SSC source. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Chris Wison <chris@chris-wilson.co.uk>
| * | drm/i915: Use DRM_DEBUG_KMS for all messages in intel_bios.cKeith Packard2011-09-27
| | | | | | | | | | | | | | | | | | | | | | | | These are all KMS related anyways, so don't hide them under other debug levels. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | drm/i915: broken copyright encoding in intel_bios.cKeith Packard2011-09-27
| | | | | | | | | | | | Signed-off-by: Keith Packard <keithp@keithp.com>
* | | Merge branch 'edp-training-fixes' into drm-intel-nextKeith Packard2011-10-20
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/gpu/drm/i915/intel_dp.c Just whitespace change conflicts
| * | | drm/i915: No need to wait for eDP power off delay if panel is onKeith Packard2011-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If the panel is powered up, there's no need to delay for the 'off' interval when turning the panel on. Signed-off-by: Keith Packard <keithp@keithp.com>
| * | | drm/i915: Restrict ILK-specific eDP power hack to ILKKeith Packard2011-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This eliminates a fairly long delay when power sequencing newer hardware Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | | drm/i915: Disable eDP VDD in a delayed work proc instead of synchronouslyKeith Packard2011-10-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no good reason to turn off the eDP force VDD bit synchronously while probing devices; that just sticks a huge delay into all mode setting paths. Instead, queue a delayed work proc to disable the VDD force bit and then remember when that fires to ensure that the appropriate delay is respected before trying to turn it back on. Signed-off-by: Keith Packard <keithp@keithp.com>
| * | | drm/i915: Create helper functions to determine eDP power stateKeith Packard2011-10-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to check eDP VDD force and panel on in several places, so create some simple helper functions to avoid duplicating code. Signed-off-by: Keith Packard <keithp@keithp.com>
| * | | drm/i915: edp_panel_on does not need to return a boolKeith Packard2011-10-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The return value was unused, so just stop doing that. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | | drm/i915: Move eDP panel fixed mode from dev_priv to intel_dpKeith Packard2011-10-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This value doesn't come directly from the VBT, and so is rather specific to the particular DP output. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | | drm/i915: Correct eDP panel power sequencing delay computationsKeith Packard2011-10-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Store the panel power sequencing delays in the dp private structure, rather than the global device structure. Who knows, maybe we'll get more than one eDP device in the future. From the eDP spec, we need the following numbers: T1 + T3 Power on to Aux Channel operation (panel_power_up_delay) This marks how long it takes the panel to boot up and get ready to receive aux channel communications. T8 Video signal to backlight on (backlight_on_delay) Once a valid video signal is being sent to the device, it can take a while before the panel is actuall showing useful data. This delay allows the panel to get something reasonable up before the backlight is turned on. T9 Backlight off to video off (backlight_off_delay) Turning the backlight off can take a moment, so this delay makes sure there is still valid video data on the screen. T10 Video off to power off (panel_power_down_delay) Presumably this delay allows the panel to perform an orderly shutdown of the display. T11 + T12 Power off to power on (panel_power_cycle_delay) So, once you turn the panel off, you have to wait a while before you can turn it back on. This delay is usually the longest in the entire sequence. Neither the VBIOS source code nor the hardware documentation has a clear mapping between the delay values they provide and those required by the eDP spec. The VBIOS code actually uses two different labels for the delay values in the five words of the relevant VBT table. **** MORE LATER *** Look at both the current hardware register settings and the VBT specified panel power sequencing timings. Use the maximum of the two delays, to make sure things work reliably. If there is no VBT data, then those values will be initialized to zero, so we'll just use the values as programmed in the hardware. Note that the BIOS just fetches delays from the VBT table to place in the hardware registers, so we should get the same values from both places, except for rounding. VBT doesn't provide any values for T1 or T2, so we'll always just use the hardware value for that. The panel power up delay is thus T1 + T2 + T3, which should be sufficient in all cases. The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy for T11, which isn't available anywhere. For the backlight delays, the eDP spec says T6 + T8 is the delay from the end of link training to backlight on and T9 is the delay from backlight off until video off. The hardware provides a 'backlight on' delay, which I'm taking to be T6 + T8 while the VBT provides something called 'T7', which I'm assuming is s On the macbook air I'm testing with, this yields a power-up delay of over 200ms and a power-down delay of over 600ms. It all works now, but we're frobbing these power controls several times during mode setting, making the whole process take an awfully long time. Signed-off-by: Keith Packard <keithp@keithp.com>
| * | | drm/i915: Ensure eDP powered up during DP_SET_POWER operation in dp_prepareKeith Packard2011-10-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Any call to intel_dp_sink_dpms must ensure that the panel has power so that the DP_SET_POWER operation will be correctly received. The only one missing this was in intel_dp_prepare. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | | drm/i915: Enable eDP panel power during I2C initialization sequenceKeith Packard2011-10-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DP i2c initialization code does a couple of i2c transactions, which means that an eDP panel must be powered up. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | | drm/i915: Wrap DP EDID fetch functions to enable eDP panel powerKeith Packard2011-10-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Talking to the eDP DDC channel requires that the panel be powered up. Wrap both the EDID and modes fetch code with calls to turn the vdd power on and back off. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | | drm/i915: Delay DP i2c initialization until panel power timings are computedKeith Packard2011-10-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On eDP, DDC requires panel power, but turning that on uses the panel power sequencing timing values fetch from the DPCD data. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | | drm/i915: Ensure panel is on during DPMS offKeith Packard2011-10-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the panel is already off, we'll need to turn VDD on to execute the (useless) DPMS off code. Yes, it would be better to just not do any of this, but correctness, and *then* performance. Signed-off-by: Keith Packard <keithp@keithp.com>
| * | | drm/i915: Turn force VDD back off when panel running in intel_dp_dpmsKeith Packard2011-09-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VDD force bit is turned on before touching the panel, but if it was enabled, there was no call to turn it back off. Add a call. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | | drm/i915: Check for eDP inside edp panel on/off funcsKeith Packard2011-09-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleans up code dealing with eDP a bit. Remove redundant checks in callers Signed-off-by: Keith Packard <keithp@keithp.com>
| * | | drm/i915: Unlock PCH_PP_CONTROL alwaysKeith Packard2011-09-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid any question about locked registers by just writing the unlock pattern with every write to the register. Signed-off-by: Keith Packard <keithp@keithp.com>
| * | | drm/i915: Check eDP power when doing aux channel communicationsKeith Packard2011-09-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Verify that the eDP VDD is on, either with the panel being on or with the VDD force-on bit being set. This demonstrates that in many instances, VDD is not on when needed, which leads to failed EDID communications. Signed-off-by: Keith Packard <keithp@keithp.com>
| * | | drm/i915: Only use VBT panel mode on eDP if no EDID is foundKeith Packard2011-09-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're going to assume that EDID is more reliable than the VBT tables for eDP panels, which is notably true on MacBook machines where the VBT contains completely bogus data. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | | drm/i915: Shut down PCH interrupts during irq_uninstallKeith Packard2011-09-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This masks out all interrupts and ack's any pending ones at IRQ uninstall time to make sure we don't receive any unexpected interrupts later on. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | | drm/i915: Enable digital port hotplug on PCH systemsKeith Packard2011-09-30
| |/ / | | | | | | | | | | | | | | | | | | | | | We were relying on the BIOS to set these bits, which doesn't always happen. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | | Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard2011-09-28
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| * | drm/i915: FBC off for ironlake and older, otherwise on by defaultKeith Packard2011-09-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the default FBC behaviour chipset specific, allowing us to turn it on by default for Ironlake and older where it has been seen to cause trouble with screen updates. Signed-off-by: Keith Packard <keithp@keithp.com> Tested-by: Francis Moreau <francis.moro@gmail.com>
| * | drm/i915: Enable SDVO hotplug interrupts for HDMI and DVISimon Farnsworth2011-09-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I was seeing a nasty 5 frame glitch every 10 seconds, caused by the poll for connection on DVI attached by SDVO. As my SDVO DVI supports hotplug detect interrupts, the fix is to enable them, and hook them in to the various bits of driver infrastructure so that they work reliably. Note that this is only tested on single-function DVI-D SDVOs, on two platforms (965GME and 945GSE), and has not been checked against a specification document. With lots of help from Adam Jackson <ajax@redhat.com> on IRC. Signed-off-by: Simon Farnsworth <simon.farnsworth@onelan.co.uk> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
| * | drm/i915: Enable dither whenever display bpc < frame buffer bpcKeith Packard2011-09-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to enable dithering on any pipe where the frame buffer has more color resolution than the output device. The previous code was incorrectly clamping the frame buffer bpc to the display bpc, effectively disabling dithering all of the time as the computed frame buffer bpc would never be larger than the display bpc. Signed-off-by: Keith Packard <keithp@keithp.com> Reported-by: Oliver Hartkopp <socketcan@hartkopp.net> Tested-by: Oliver Hartkopp <socketcan@hartkopp.net>
* | | drm/i915: Dumb down the semaphore logicBen Widawsky2011-09-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While I think the previous code is correct, it was hard to follow and hard to debug. Since we already have a ring abstraction, might as well use it to handle the semaphore updates and compares. I don't expect this code to make semaphores better or worse, but you never know... v2: Remove magic per Keith's suggestions. Ran Daniel's gem_ring_sync_loop test on this. v3: Ignored one of Keith's suggestions. v4: Removed some bloat per Daniel's recommendation. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Keith Packard <keithp@keithp.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
* | | drm/i915: pass ELD to HDMI/DP audio driverWu Fengguang2011-09-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ELD support for Intel Eaglelake, IbexPeak/Ironlake, SandyBridge/CougarPoint and IvyBridge/PantherPoint chips. ELD (EDID-Like Data) describes to the HDMI/DP audio driver the audio capabilities of the plugged monitor. It's built and passed to audio driver in 2 steps: (1) at get_modes time, parse EDID and save ELD to drm_connector.eld[] (2) at mode_set time, write drm_connector.eld[] to the Transcoder's hw ELD buffer and set the ELD_valid bit to inform HDMI/DP audio driver This patch is tested OK on G45/HDMI, IbexPeak/HDMI and IvyBridge/HDMI+DP. Test scheme: plug in the HDMI/DP monitor, and run cat /proc/asound/card0/eld* to check if the monitor name, HDMI/DP type, etc. show up correctly. Minor imperfection: the GEN5_AUD_CNTL_ST/DIP_Port_Select field always reads 0 (reserved). Without knowing the port number, I worked it around by setting the ELD_valid bit for ALL the three ports. It's tested to not be a problem, because the audio driver will find invalid ELD data and hence rightfully abort, even when it sees the ELD_valid indicator. Thanks to Zhenyu and Pierre-Louis for a lot of valuable help and testing. CC: Zhao Yakui <yakui.zhao@intel.com> CC: Wang Zhenyu <zhenyu.z.wang@intel.com> CC: Jeremy Bush <contractfrombelow@gmail.com> CC: Christopher White <c.white@pulseforce.com> CC: Pierre-Louis Bossart <pierre-louis.bossart@intel.com> CC: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Wu Fengguang <fengguang.wu@intel.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* | | drm/i915: Enable dither whenever display bpc < frame buffer bpcKeith Packard2011-09-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to enable dithering on any pipe where the frame buffer has more color resolution than the output device. The previous code was incorrectly clamping the frame buffer bpc to the display bpc, effectively disabling dithering all of the time as the computed frame buffer bpc would never be larger than the display bpc. Signed-off-by: Keith Packard <keithp@keithp.com> Reported-by: Oliver Hartkopp <socketcan@hartkopp.net> Tested-by: Oliver Hartkopp <socketcan@hartkopp.net>
* | | Merge branch 'drm-intel-next' of git://people.freedesktop.org/~keithp/linux ↵Dave Airlie2011-09-20
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | into drm-next * 'drm-intel-next' of git://people.freedesktop.org/~keithp/linux: Drivers: i915: Fix all space related issues.
| * | | Drivers: i915: Fix all space related issues.Akshay Joshi2011-09-19
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Various issues involved with the space character were generating warnings in the checkpatch.pl file. This patch removes most of those warnings. Signed-off-by: Akshay Joshi <me@akshayjoshi.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* / / drm/i915: use common functions for mmap offset creationRob Clark2011-08-30
|/ / | | | | | | | | Signed-off-by: Rob Clark <rob@ti.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/i915: Fix wrong initializer for "locked" variable in assert_panel_unlockedThomas Jarosch2011-08-25
| | | | | | | | | | | | | | | | | | | | Otherwise it just contains random memory. Issue detected by cppcheck. Signed-off-by: Thomas Jarosch <thomas.jarosch@intra2net.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* | i915: do not setup intel_backlight twiceKamal Mostafa2011-08-22
|/ | | | | | | | | | | | | The commit "Not all systems expose a firmware or platform mechanism for changing the backlight intensity on i915, so add native driver support" adds calls to intel_panel_setup_backlight() from intel_{lvds,dp}_init so do not call it again from intel_setup_outputs(). BugLink: http://bugs.launchpad.net/bugs/831542 Signed-off-by: Kamal Mostafa <kamal@canonical.com> ACKed-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* Merge branch 'for-linus' of ↵Linus Torvalds2011-08-20
|\ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/drm-intel * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/drm-intel: drm/i915: set GFX_MODE to pre-Ivybridge default value even on Ivybridge
| * drm/i915: set GFX_MODE to pre-Ivybridge default value even on IvybridgeJesse Barnes2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to Ivybridge, the GFX_MODE would default to 0x800, meaning that MI_FLUSH would flush the TLBs in addition to the rest of the caches indicated in the MI_FLUSH command. However starting with Ivybridge, the register defaults to 0x2800 out of reset, meaning that to invalidate the TLB we need to use PIPE_CONTROL. Since we're not doing that yet, go back to the old default so things work. v2: don't forget to actually *clear* the new bit Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | drm/i915: Cannot set clock gating under UMSKeith Packard2011-08-15
| | | | | | | | | | | | | | | | The clock gating functions are only assigned under KMS, so don't try to call them under UMS. Signed-off-by: Keith Packard <keithp@keithp.com> Tested-by: Justin P. Mattock <justinmattock@gmail.com>
* | drm/i915: Can't do accurate vblank timestamps with UMSKeith Packard2011-08-15
| | | | | | | | | | | | | | | | Disable this feature when KMS is not running by setting the driver->get_vblank_timestamp function pointer to NULL. Signed-off-by: Keith Packard <keithp@keithp.com> Tested-by: Justin P. Mattock <justinmattock@gmail.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-09 07:55:38 -0400