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path: root/drivers/gpu/drm/i915/intel_ringbuffer.c
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* drm/i915/ringbuffer: Use the HEAD auto-reporting mechanismChris Wilson2010-11-08
| | | | | | | | | | | | | | My Sandybridge only reports 0 for the ring buffer registers, causing it to hang as soon as we exhaust the available ring. As a workaround, take advantage of our huge ring buffers and use the auto-reporting mechanism to update the status page with the HEAD location every 64 KiB. Cherry-picked from 6aa56062eaba67adfb247cded244fd877329588d. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31404 Tested-by: Zhao Jian <jian.j.zhao@intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: SNB BLT workaroundChris Wilson2010-11-02
| | | | | | | | | | | | | | | | | On some stepping of SNB cpu, the first command to be parsed in BLT command streamer should be MI_BATCHBUFFER_START otherwise the GPU may hang. (cherry picked from commit 8d19215be8254f4f75e9c5a0d28345947b0382db) Conflicts: drivers/gpu/drm/i915/intel_ringbuffer.c drivers/gpu/drm/i915/intel_ringbuffer.h Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Move gpu_write_list to per-ringChris Wilson2010-10-24
| | | | | | | | | | ... to prevent flush processing of an idle (or even absent) ring. This fixes a regression during suspend from 87acb0a5. Reported-and-tested-by: Alexey Fisher <bug-track@fisher-privat.net> Tested-by: Peter Clifton <pcjc2@cam.ac.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/ringbuffer: Write the value passed in to the tail registerChris Wilson2010-10-22
| | | | | | | | This should fix the error along the reset path were we tried to clear the tail register by setting it to 0, but were in fact setting it to the current value and complaining when it did not reset to 0. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: IS_IRONLAKE is synonymous with gen == 5Chris Wilson2010-10-21
| | | | | | | So remove the redundant bit in the capabilities block and s/IS_IRONLAKE/IS_GEN5/. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Enable SandyBridge blitter ringChris Wilson2010-10-21
| | | | | | | | Based on an original patch by Zhenyu Wang, this initializes the BLT ring for SandyBridge and enables support for user execbuffers. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/ringbuffer: Remove broken intel_fill_struct()Chris Wilson2010-10-21
| | | | | | | | ... before someone tries to use it. The code both calls intel_ring_begin/advance() and open-codes the bookkeeping performed by those two functions. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/ringbuffer: Fix emit batch buffer regression from 8187a2bChris Wilson2010-10-21
| | | | | | | In commit 8187a2b, the number of dwords used in the ringbuffer for executing the batch buffer was erroneously changed from 2 to 4. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Sleep whilst waiting for the ringChris Wilson2010-10-19
| | | | | | | | | If userspace is submitting so many long running batches that the ring becomes full, throttle by sleeping for a 1ms before checking for free space. Simply yielding was causing excessive scheduler overhead whilst making no progress. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/debug: Convert i915_verify_active() to scan all listsChris Wilson2010-09-30
| | | | | | ... and check more regularly. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: kill ring->setup_status_pageDaniel Vetter2010-09-25
| | | | | | | | It's the same code, essentially, so kill all copies safe one unified version. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: kill ring->get_active_headDaniel Vetter2010-09-25
| | | | | | | | | | | All functions are extremely similar, so fold them into one generic implementation. This function isn't used anyway, because there's not yet a bsd ring error state dumper. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: kill per-ring macrosDaniel Vetter2010-09-25
| | | | | | | | | | Two macros that use a base address for HWS_PGA were missing, add them. Also switch the remaining users of *_ACTHD to the ring-base one. Kill the other ring-specific macros because they're now unused. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [ickle: And silence checkpatch whilst in the vicinity] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: fix ACTHD for gen <= 3Daniel Vetter2010-09-25
| | | | | | | | | | | | | This was mixed up in the following patch: commit a6c45cf013a57e32ddae43dd4ac911eb4a3919fd Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Fri Sep 17 00:32:17 2010 +0100 drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965g Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Only hold a process-local lock whilst throttling.Chris Wilson2010-09-24
| | | | | | | | | Avoid cause latencies in other clients by not taking the global struct mutex and moving the per-client request manipulation a local per-client mutex. For example, this allows a compositor to schedule a page-flip (through X) whilst an OpenGL application is monopolising the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/ringbuffer: whitespace cleanupChris Wilson2010-09-21
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: drop alignment ringbuffer parameterDaniel Vetter2010-09-21
| | | | | | | Always PAGE_SIZE and only complicates the code. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: don't explicitly initialize ringbuffer members to zeroDaniel Vetter2010-09-21
| | | | | | | The compiler happily does that for us. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: use new macros to access the ring ctl registerDaniel Vetter2010-09-21
| | | | | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: use new macros to access the ring head registerDaniel Vetter2010-09-21
| | | | | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: use new macros to access the ring start registerDaniel Vetter2010-09-21
| | | | | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: use new macros to access the ring tail registerDaniel Vetter2010-09-21
| | | | | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: add relative ring register macrosDaniel Vetter2010-09-21
| | | | | | | | | | | | Documentation explicitly mentions that the ring registers are designed to have the same offsets relative to a base registers. Use this to fight the code beaurocratic in intel_ringbuffer.c. No code changes in this patch, just the new definitions. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/ringbuffer: Mark the initialisation structs as constant.Chris Wilson2010-09-21
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: add a new BSD ring buffer for SandybridgeXiang, Haihao2010-09-21
| | | | | | | | This ring buffer is used for video decoding/encoding on Sandybridge. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/ringbuffer: Implement advance using set_tailChris Wilson2010-09-21
| | | | | | | As noted by Zhenyu, we can now simply replace the existing advance hook by calling the new set_tail function pointer directly. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: add set_tail hook in struct intel_ring_bufferXiang, Haihao2010-09-21
| | | | | | | | | | This is prepared for video codec ring buffer on Sandybridge. It is needed to read/write more than one register to move the tail pointer of the video codec ring on Sandybridge. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: do not export the instances of struct intel_ring_bufferXiang, Haihao2010-09-21
| | | | | | | | | Introduce intel_init_render_ring_buffer(), intel_init_bsd_ring_buffer for ring initialization. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Only emit a flush request on the active ring.Chris Wilson2010-09-21
| | | | | | | | When flushing the GPU domains,we emit a flush on *both* rings, even though they share a unified cache. Only emit the flush on the currently active ring. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965gChris Wilson2010-09-21
| | | | | | | Avoid confusion between i965g meaning broadwater and the gen4+ chipset families. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Remove unused intel_ringbuffer->ring_flagChris Wilson2010-09-14
| | | | | | This can always be re-added should somebody find a use... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: move flushing list processing to i915_retire_commandsDaniel Vetter2010-09-08
| | | | | | | | | | | | | | | ... instead of threading flush_domains through the execbuf code to i915_add_request. With this change 2 small cleanups are possible (likewise the majority of the patch): - The flush_domains parameter of i915_add_request is always 0. Drop it and the corresponding logic. - Ditto for the seqno param of i915_gem_process_flushing_list. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Enable MI_FLUSH on SandybridgeZhenyu Wang2010-09-07
| | | | | | | | | MI_FLUSH is being deprecated, but still available on Sandybridge. Make sure it's enabled as userspace still uses MI_FLUSH. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915 invalidate indirect state pointers at end of ring execZou Nan hai2010-08-09
| | | | | | | | This is required by the spec, and without this some 3D programs will hang after resume from RC6 we enable that. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915/ringbuffer: Set ring->gem_buffer = NULL on init unwindChris Wilson2010-08-09
| | | | | | | | | The cleanup path for early abort failed to nullify the gem_buffer. The likely consequence of this is zero, since a failure here should mean aborting the module load. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Use a common seqno for all rings.Chris Wilson2010-08-09
| | | | | | | | This will be used by the eviction logic to maintain fairness between the rings. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Inline ringbuffer_emit()Chris Wilson2010-08-09
| | | | | | | | As the function has been reduced to a store plus increment, the body is now smaller than the call so inline it. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Move ringbuffer accounting to begin/advance.Chris Wilson2010-08-09
| | | | | | | | | | | | | As we check that the ringbuffer will not wrap upon emission, we do not need to check that incrementing the tail wrapped every time. However, we do upon advancing just in case the tail is now pointing at the very end of the ring. Likewise we can account for the space used during emission in begin() and avoid decrementing it for every emit. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Unroll wrapping of the ringbuffer.Chris Wilson2010-08-09
| | | | | | | The tail is quadword aligned, so we can add two MI_NOOP as a time. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Account for space on the ring buffer consumed whilst wrapping.Chris Wilson2010-07-01
| | | | | | | | If we fill the tail of the physical ring buffer with NOOP when wrapping, we need to account for the reduction in available space. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer.Zou Nan hai2010-06-14
| | | | | | | | | The ring_begin API was taking a number of bytes, while all of our other begin/end macros take number of dwords. Change the API over to dwords to prevent future bugs. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix PIPE_CONTROL command on SandybridgeZhenyu Wang2010-05-28
| | | | | | | | | | | | | | | Sandybridge(Gen6) has new format for PIPE_CONTROL command, the flush and post-op control are in dword 1 now. This changes command length field for difference between Ironlake and Sandybridge. I tried to test this with noop request and issue PIPE_CONTROL command for each sequence and track notify interrupts, which seems work fine. Hopefully we don't need workaround like on Ironlake for Sandybridge. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: implement BSD ring buffer V2Zou Nan hai2010-05-26
| | | | | | | | | | | The BSD (bit stream decoder) ring is used for accessing the BSD engine which decodes video bitstream for H.264 and VC1 on G45+. It is asynchronous with the render ring and has access to separate parts of the GPU from it, though the render cache is coherent between the two. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: introduce intel_ring_buffer structure (V2)Zou Nan hai2010-05-26
| | | | | | | | | | | Introduces a more complete intel_ring_buffer structure with callbacks for setup and management of a particular ringbuffer, and converts the render ring buffer consumers to use it. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com> [anholt: Fixed up whitespace fail and rebased against prep patches] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Rename dev_priv->ring to dev_priv->render_ring.Eric Anholt2010-05-26
| | | | | | With the advent of the BSD ring, be clear about which ring this is. The docs are pretty consistent with calling this the Render engine at this point.
* drm/i915: Move ringbuffer-related code to intel_ringbuffer.c.Eric Anholt2010-05-26
This is preparation for supporting multiple ringbuffers on Ironlake. The non-copy-and-paste changes are: - de-staticing functions - I915_GEM_GPU_DOMAINS moving to i915_drv.h to be used by both files. - i915_gem_add_request had only half its implementation copy-and-pasted out of the middle of it.
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