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path: root/drivers/gpu/drm/i915/intel_pm.c
Commit message (Expand)AuthorAge
* drm/i915: sanitize RPS resetting during GPU resetImre Deak2014-12-15
* drm/i915/bdw: Fix the write setting up the WIZ hashing modeDamien Lespiau2014-12-10
* drm/i915: remove the IRQs enabled WARN from intel_disable_gt_powersaveImre Deak2014-11-20
* drm/i915: vlv: increase timeout when setting idle GPU freqImre Deak2014-11-20
* drm/i915: Update ring freq for full gpu freq rangeTom O'Rourke2014-11-20
* drm/i915: change initial rps frequency for gen8Tom O'Rourke2014-11-20
* drm/i915: Keep min freq above floor on HSW/BDWTom O'Rourke2014-11-20
* drm/i915: Use efficient frequency for HSW/BDWTom O'Rourke2014-11-20
* Merge tag 'drm-intel-fixes-2014-11-19' into drm-intel-next-queuedDaniel Vetter2014-11-19
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| * drm/i915: drop WaSetupGtModeTdRowDispatch:snbDaniel Vetter2014-11-17
* | drm/i915: disable rps irqs earlier during suspend/unloadImre Deak2014-11-19
* | drm/i915: sanitize rps irq disablingImre Deak2014-11-19
* | drm/i915: sanitize rps irq enablingImre Deak2014-11-19
* | drm/i915: move rps irq disable one level upImre Deak2014-11-19
* | drm/i915: Extend pcode mailbox interfaceTom O'Rourke2014-11-19
* | drm/i915: Change CHV SKU400 GPU freq divider to 10Ville Syrjälä2014-11-17
* | drm/i915: Add missing newline to 'DDR speed' debug messagesVille Syrjälä2014-11-17
* | drm/i915: Refactor vlv/chv GPU frequency divider setupVille Syrjälä2014-11-17
* | drm/i915: Improve PCBR debug informationVille Syrjälä2014-11-17
* | drm/i915: Warn if GPLL isn't used on vlv/chvVille Syrjälä2014-11-17
* | drm/i915: Add a name for the Punit GPLLENABLE bitVille Syrjälä2014-11-17
* | drm/i915: Silence valleyview_set_rps()Ville Syrjälä2014-11-17
* | drm/i915: Let's hope future platforms will use the same WM code as SKLDamien Lespiau2014-11-14
* | drm/i915: Clear PCODE_DATA1 on SNB+Damien Lespiau2014-11-14
* | drm/i915: Read the CCK fuse register from CCKVille Syrjälä2014-11-14
* | drm/i915: move rps irq enable/disable to i915_irq.cImre Deak2014-11-14
* | drm/i915: unify gen6/gen8 rps irq enable/disableImre Deak2014-11-14
* | drm/i915: unify gen6/gen8 pm irq helpersImre Deak2014-11-14
* | drm/i915/chv: Remove pre-production workaroundsArun Siluvery2014-11-14
* | drm/i915/skl: Enable Gen9 RC6Zhe Wang2014-11-07
* | drm/i915/skl: Log the order in which we flush the pipes in the WM codeDamien Lespiau2014-11-07
* | drm/i915/skl: Flush the WM configurationDamien Lespiau2014-11-07
* | drm/i915/skl: Stage the pipe DDB allocationDamien Lespiau2014-11-07
* | drm/i915/skl: Reduce the indentation level in skl_write_wm_values()Damien Lespiau2014-11-07
* | drm/i915/skl: Correctly align skl_compute_plane_wm() argumentsDamien Lespiau2014-11-07
* | drm/i915/skl: Rework when the transition WMs are computedDamien Lespiau2014-11-07
* | drm/i915/skl: Move all the WM compute functions in one placeDamien Lespiau2014-11-07
* | drm/i915/skl: Make res_blocks/lines intermediate values 32 bitsDamien Lespiau2014-11-07
* | drm/i915/skl: Use a more descriptive parameter name in skl_compute_plane_wm()Damien Lespiau2014-11-07
* | drm/i915/skl: Make 'end' of the DDB allocation entry exclusiveDamien Lespiau2014-11-07
* | drm/i915/skl: Check the DDB state at modesetDamien Lespiau2014-11-07
* | drm/i915/skl: Read back the DDB allocation hw stateDamien Lespiau2014-11-07
* | drm/i915/skl: Store the new WM state at the very end of the updateDamien Lespiau2014-11-07
* | drm/i915/gen9: Disable WM if corresponding latency is 0Vandana Kannan2014-11-07
* | drm/i915/gen9: Add 2us read latency to WM levelVandana Kannan2014-11-07
* | drm/i915/skl: Read the pipe WM HW statePradeep Bhat2014-11-07
* | drm/i915/skl: Program the DDB allocationDamien Lespiau2014-11-07
* | drm/i915/skl: Allocate DDB portions for display planesDamien Lespiau2014-11-07
* | drm/i915/skl: SKL Watermark ComputationPradeep Bhat2014-11-07
* | drm/i915/skl: Definition of SKL WM param structs for pipe/planePradeep Bhat2014-11-07
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