litmus-rt.git - The LITMUS^RT kernel.

	Commit message (Expand)	Author	Age
*	drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/	Daniel Vetter	2014-10-03
*	drm/i915: Extract intel_runtime_pm.c	Daniel Vetter	2014-10-01
*	Merge branch 'topic/skl-stage1' into drm-intel-next-queued	Daniel Vetter	2014-09-30
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\| *	drm/i915/skl: Move gen9 pm initialization into its own branch	Damien Lespiau	2014-09-24
\| *	drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:skl	Damien Lespiau	2014-09-24
\| *	drm/i915/skl: Implement Wa4x4STCOptimizationDisable:skl	Damien Lespiau	2014-09-24
\| *	drm/i915/skl: Implement WaDisableSDEUnitClockGating:skl	Damien Lespiau	2014-09-24
\| *	drm/i915/skl: Restore pipe B/C interrupts	Satheeshakrishna M	2014-09-24
\| *	drm/i915/skl: Provide a placeholder for init_clock_gating()	Damien Lespiau	2014-09-24
* \|	drm/i915: Minimize the huge amount of unecessary fbc sw cache clean.	Rodrigo Vivi	2014-09-29
* \|	drm/i915: add SW tracking to FBC enabling	Paulo Zanoni	2014-09-23
* \|	drm/i915: extract intel_init_fbc()	Paulo Zanoni	2014-09-23
* \|	drm/i915: Avoid reading fbc registers in vain when fbc was never enabled.	Rodrigo Vivi	2014-09-19
* \|	drm/i915: Only flush fbc on sw when fbc is enabled.	Rodrigo Vivi	2014-09-19
* \|	drm/i915: Limit the watermark to at least 8 entries on gen2/3	Ville Syrjälä	2014-09-19
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*	drm/i915: Reset power sequencer pipe tracking when disp2d is off	Ville Syrjälä	2014-09-04
*	drm/i915: Rename global latency_ns variable	Chris Wilson	2014-09-03
*	drm/i915: Disable trickle feed for gen2/3	Ville Syrjälä	2014-09-03
*	drm/i915: Fix gen2 planes B and C max watermark value	Ville Syrjälä	2014-09-03
*	drm/i915: Init some CHV workarounds via LRIs in ring->init_context()	Ville Syrjälä	2014-09-03
*	drm/i915: Warn about odd rps values on CHV	Ville Syrjälä	2014-09-03
*	drm/i915/bdw: BDW Software Turbo	Daisy Sun	2014-09-03
*	drm/i915: Populate mem_freq in init_gt_powerwave()	Ville Syrjälä	2014-09-03
*	drm/i915/bdw: Apply workarounds in render ring init function	Arun Siluvery	2014-09-03
*	drm/i915: FBC flush nuke for BDW	Rodrigo Vivi	2014-09-03
*	drm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gating	Paulo Zanoni	2014-09-03
*	drm/i915: call lpt_init_clock_gating on BDW too	Paulo Zanoni	2014-09-03
*	drm/i915: Bring UP Power Wells before disabling RC6.	Deepak S	2014-09-03
*	drm/i915: Use dev_priv as first argument of for_each_pipe()	Damien Lespiau	2014-09-03
*	drm/i915: Add 180 degree primary plane rotation support	Sonika Jindal	2014-09-03
*	Merge tag 'drm-intel-next-2014-09-01' of git://anongit.freedesktop.org/drm-in...	Dave Airlie	2014-09-02
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\| *	drm/i915: Remove set but unused 'gt_perf_status'	Damien Lespiau	2014-08-11
* \|	Merge tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-in...	Dave Airlie	2014-08-25
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\| *	drm/i915: Add sprite watermark programming for VLV and CHV	Gajanan Bhat	2014-08-08
\| *	drm/i915: Round-up clock and limit drain latency	Gajanan Bhat	2014-08-08
\| *	drm/i915: Generalize drain latency computation	Gajanan Bhat	2014-08-08
\| *	drm/i915: Polish the chv cmnlane resrt macros	Ville Syrjälä	2014-08-08
\| *	drm/i915: Hack to tie both common lanes together on chv	Ville Syrjälä	2014-08-08
\| *	drm/i915: Add cherryview_update_wm()	Ville Syrjälä	2014-08-08
\| *	drm/i915: Update DDL only for current CRTC	Gajanan Bhat	2014-08-08
\| *	drm/i915: Parametrize VLV_DDL registers	Ville Syrjälä	2014-08-08
\| *	drm/i915: Fill out the FWx watermark register defines	Ville Syrjälä	2014-08-08
\| *	drm/i915: Introduce FBC False Color for debug purposes.	Rodrigo Vivi	2014-08-08
\| *	drm/i915: Split a few long debug prints	Ville Syrjälä	2014-08-08
\| *	drm/i915: Add chv port D TX wells	Ville Syrjälä	2014-08-08
\| *	drm/i915: Add chv port B and C TX wells	Ville Syrjälä	2014-08-08
\| *	drm/i915: Add per-pipe power wells for chv	Ville Syrjälä	2014-08-08
\| *	drm/i915: Add disp2d power well for chv	Ville Syrjälä	2014-08-08
\| *	drm/i915: Add chv cmnlane power wells	Ville Syrjälä	2014-08-08
\| *	drm/i915: Add chv_power_wells[]	Ville Syrjälä	2014-08-08