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path: root/drivers/gpu/drm/i915/intel_display.c
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* drm/i915: kill warning in intel_find_pll_g4x_dpJesse Barnes2009-10-23
| | | | | | | Initialize clock.vco to silence gcc. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: update watermarks before enabling PLLsJesse Barnes2009-10-23
| | | | | | | | | | When coming back from DPMS or turning on a display, make sure we have the watermarks set up before turning on the display plane, otherwise we may get underruns. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Dirk Hohndel <hohndel@infradead.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: add FIFO watermark support for G4xJesse Barnes2009-10-23
| | | | | | | | | Turns out G4x needs to have sensible watermarks set, especially for self-refresh enabled modes. Add support for it. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Dirk Hohndel <hohndel@infradead.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: fix panel fitting filter coefficient select for IronlakeZhenyu Wang2009-10-19
| | | | | | | | | | | Must set filter selection as hardcoded coefficients for medium 3x3 filtering, which matches vbios setting for Ironlake. This fixes display corrupt issue on HP arrandale with new vbios. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: fix to setup display reference clock control on IronlakeZhenyu Wang2009-10-19
| | | | | | | | | | | | | | For new stepping of PCH, the display reference clock is fully under driver's control. This one trys to setup all needed reference clock for different outputs. Older stepping of PCH chipset should be ignoring this. This fixes output failure issue on newer PCH which requires driver to take control of reference clock enabling. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Install a fence register for fbc on g4xChris Wilson2009-10-15
| | | | | | | | | | | | | | To enable framebuffer compression on a g4x, we not only need the buffer to tiled (X only), we also need to hold a fence register for the buffer. Currently we only install a fence register for pre-i965s when setting up the scanout buffer. Rather than adding some convoluted logic to g4x_enable_fbc() to acquire a fence register, and perhaps to g4x_disable_fbc() to release it again, we can extend the acquisition during setup to all chipsets. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix FDI M/N setting according with correct color depthZhenyu Wang2009-10-13
| | | | | | | | | | | | | | FDI M/N calculation hasn't taken the current pipe color depth into account, but always set as 24bpp. This one checks current pipe color depth setting, and change FDI M/N calculation a little to use bits_per_pixel first, then convert to bytes_per_pixel later. This fixes display corrupt issue on Arrandle LVDS with 1600x900 panel in 18bpp dual-channel mode. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: disable powersave feature for Ironlake currentlyZhenyu Wang2009-10-13
| | | | | | | | | | | Until we figure out the right setting for powersave features on Ironlake, disable it for now. Also disable watermark update, which has new registers for it on Ironlake too. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [anholt: Resolved against the Pineview FBC changes] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Set the LVDS_BORDER when using LVDS scaling modeZhao Yakui2009-10-13
| | | | | | | | | | | | | | | | | | According to the spec the LVDS_BORDER_ENABLE bit decides whether the border data should be included in the active display and data sent to the panel. Border should be used when in VGA centered (un-scaled) mode or when scaling a 4:3 source image to a wide screen panel (typical 16:9). So when the LVDS scaling is used, decide whether the LVDS_BORDER should be enabled or not according to the current scaling mode. At the same time fix the typo error in LVDS center scaling mode. https://bugs.freedesktop.org/show_bug.cgi?id=23789 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> tested-by: Zhao Jian <jian.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* Merge branch 'drm-intel-next' of ↵Linus Torvalds2009-10-09
|\ | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: Initialize HDMI outputs as HDMI connectors, not DVI. drm/i915: Multiply the refresh by 1000 in TV mode validatiion drm/i915: Enable irq to trace batch buffer completion. drm/i915: batch submit seqno off-by-one. drm/i915: Record device minor rather than pointer in TRACE_EVENT drm/i915: Don't call intel_update_fbc from intel_crtc_cursor_set
| * drm/i915: Don't call intel_update_fbc from intel_crtc_cursor_setBrian Rogers2009-09-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 74dff282 exposed this unnecessary call by causing a change in the failure path on i965 where framebuffer compression will be turned on and off on every cursor update. If you don't have the xf86-video-intel fix to avoid the blinking cursor effect, this is very slow. Symptoms were a far more noticeable cursor blink with every cursor image change combined with severe slowdown for animated cursors. Signed-off-by: Brian Rogers <brian@xyzw.org> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* | Merge branch 'drm-next' of ../drm-next into drm-linusDave Airlie2009-10-08
|\ \ | |/ |/| | | | | | | | | | | | | conflict in radeon since new init path merged with vga arb code. Conflicts: drivers/gpu/drm/radeon/radeon.h drivers/gpu/drm/radeon/radeon_asic.h drivers/gpu/drm/radeon/radeon_device.c
| * drm/fb: add more correct 8/16/24/32 bpp fb support.Dave Airlie2009-10-05
| | | | | | | | | | | | | | | | | | | | | | | | | | The previous patches had some unwanted side effects, I've fixed the lack of 32bpp working, and fixed up 16bpp so it should also work. this also adds the interface to allow the driver to set a preferred console depth so for example low memory rn50 can set it to 8bpp. It also catches 24bpp on cards that can't do it and forces 32bpp. Tested on r100/r600/i945. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/fb: add setcmap and fix 8-bit support.Dave Airlie2009-10-04
| | | | | | | | | | | | | | | | This adds support for the setcmap api and fixes the 8bpp support at least on radeon hardware. It adds a new load_lut hook which can be called once the color map is setup. Signed-off-by: Dave Airlie <airlied@redhat.com>
* | Merge branch 'drm-intel-next' of ↵Linus Torvalds2009-09-24
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (57 commits) drm/i915: Handle ERESTARTSYS during page fault drm/i915: Warn before mmaping a purgeable buffer. drm/i915: Track purged state. drm/i915: Remove eviction debug spam drm/i915: Immediately discard any backing storage for uneeded objects drm/i915: Do not mis-classify clean objects as purgeable drm/i915: Whitespace correction for madv drm/i915: BUG_ON page refleak during unbind drm/i915: Search harder for a reusable object drm/i915: Clean up evict from list. drm/i915: Add tracepoints drm/i915: framebuffer compression for GM45+ drm/i915: split display functions by chip type drm/i915: Skip the sanity checks if the current relocation is valid drm/i915: Check that the relocation points to within the target drm/i915: correct FBC update when pipe base update occurs drm/i915: blacklist Acer AspireOne lid status ACPI: make ACPI button funcs no-ops if not built in drm/i915: prevent FIFO calculation overflows on 32 bits with high dotclocks drm/i915: intel_display.c handle latency variable efficiently ... Fix up trivial conflicts in drivers/gpu/drm/i915/{i915_dma.c|i915_drv.h}
| * | drm/i915: framebuffer compression for GM45+Jesse Barnes2009-09-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for framebuffer compression on GM45 and above. Removes some unnecessary I915_HAS_FBC checks as well (this is now part of the FBC display function). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: split display functions by chip typeJesse Barnes2009-09-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch splits out several of the display functions into a separate display function table to avoid tons of chipset specific if..else if..else if blocks all over. There are more opportunities for this (some noted in the structure defintition); so more cleanup patches will follow. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: correct FBC update when pipe base update occursJesse Barnes2009-09-17
| | | | | | | | | | | | | | | | | | | | | | | | We usually don't have an SAREA, and we always want to update the FBC status anyway, so move the update up above the various master/sarea checks. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: prevent FIFO calculation overflows on 32 bits with high dotclocksJesse Barnes2009-09-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A very high dotclock (e.g. 229500kHz as reported by Anton) can cause the entries_required variable to overflow, potentially leading to a FIFO watermark value that's too low to support the given mode. Split the division across the calculation to avoid this. Cc: stable@kernel.org Reported-by: Anton Khirnov <wyskas@gmail.com> Tested-by: Anton Khirnov <wyskas@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: intel_display.c handle latency variable efficientlyJaswinder Singh Rajput2009-09-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By handling latency variable efficiently we also get rid of this warning : CC [M] drivers/gpu/drm/i915/intel_display.o drivers/gpu/drm/i915/intel_display.c: In function ‘igd_enable_cxsr’: drivers/gpu/drm/i915/intel_display.c:1918: warning: ‘latency’ may be used uninitialized in this function Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: fix startup hang on some non-mobile platformsJesse Barnes2009-09-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to a bogus FBC support check and failing to check for FBC support in the right places, mode setting on non-mobile platforms could fail and hang in the FBC disable routine. Fix it up. This fix highlights the need for cleanups in this area (function pointers and better feature support checks). Patches for that to follow. Tested-by: Kenny Graunke <kenny@whitecape.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: Fix LVDS panel fitting on ArrandaleZhenyu Wang2009-09-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arrandale has new window based method for panel fitting. This one enables full screen aspect scaling on LVDS. It fixes standard mode display failure on LVDS for Arrandale. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: Fix typo for wrong LVDS clock setting on IGDNGZhenyu Wang2009-09-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New register for PCH LVDS on IGDNG should be used. This is a copy-n-paste typo. This fixes possible dual channel LVDS panel failure on IGDNG. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: framebuffer compression for pre-GM45Jesse Barnes2009-09-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds framebuffer compression (good for about ~0.5W power savings in the best case) support for pre-GM45 chips. GM45+ have a new, more flexible FBC scheme that will be added in a separate patch. FBC can't always be enabled: the compressed buffer must be physically contiguous and reside in stolen space. So if you have a large display and a small amount of stolen memory, you may not be able to take advantage of FBC. In some cases, a BIOS setting controls how much stolen space is available. Increasing this to 8 or 16M can help. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: force mode set at lid open timeJesse Barnes2009-09-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some laptop platforms will disable pipes and/or planes at lid close time and not restore them when the lid is opened again. So catch the lid event, and if the lid was opened, force a mode restore. Fixes fdo bug #21230. Acked-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Write zero to DPLL_MD Reg for non-SDVO outputZhao Yakui2009-09-10
| |/ | | | | | | | | | | | | | | | | | | | | | | | | When the output device is LVDS, maybe the pixel clock of adjusted_mode will be less than that in mode. In such case it will set the incorrect multipler factor in DPLL_MD register. So the dpll_md_reg will be reset when the output type is non-SDVO https://bugs.freedesktop.org/show_bug.cgi?id=22761 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewd-by: Eric Anholt <eric@anholt.net> Signed-off-by: Eric Anholt <eric@anholt.net>
* / drm/vgaarb: add VGA arbitration support to the drm and kms.Dave Airlie2009-09-21
|/ | | | | | | | | | | | | VGA arb requires DRM support for non-kms drivers, to turn on/off irqs when disabling the mem/io regions. VGA arb requires KMS support for GPUs where we can turn off VGA decoding. Currently we know how to do this for intel and radeon kms drivers, which allows them to be removed from the arbiter. This patch comes from Fedora rawhide kernel. Signed-off-by: Dave Airlie <airlied@redhat.com>
* Merge intel drm-intel-next branchDave Airlie2009-09-07
|\ | | | | | | | | | | | | | | | | Merge remote branch 'anholt/drm-intel-next' of ../anholt-2.6 into drm-next Conflicts: drivers/gpu/drm/i915/intel_display.c drivers/gpu/drm/i915/intel_drv.h drivers/gpu/drm/i915/intel_sdvo.c
| * drm/i915: Put the idle reclocking work on our private workqueue as well.Eric Anholt2009-09-06
| | | | | | | | | | | | Fixes (again) whole-system lockups due to GPU lockups. Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: do dynamic clock freq control only in kernel modesettingZhenyu Wang2009-09-04
| | | | | | | | | | Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: fix tiling on IGDNGZhenyu Wang2009-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | It seems that on IGDNG the same swizzling setup always applys. And front buffer tiling needs to set address swizzle in display arb control too. Fix plane tricle feed setting in v1 which should be disable bit, and always setup address swizzle to let hardware care for buffer tiling in all cases. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: modeset: always set intel_crtc->dpms_mode by moving the assignment up.Daniel Vetter2009-09-04
| | | | | | | | | | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: remove open-coded drm_mode_object_findDaniel Vetter2009-09-04
| | | | | | | | | | | | | | | | And clean up a small whitespace goof-up in the same function, while I was looking at it. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Make the downclocking debug code be under DRM_DEBUG not DRM_ERROR.Eric Anholt2009-09-04
| | | | | | | | | | Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * drm/i915: add dynamic clock frequency controlJesse Barnes2009-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several sources of unnecessary power consumption on Intel graphics systems. The first is the LVDS clock. TFTs don't suffer from persistence issues like CRTs, and so we can reduce the LVDS refresh rate when the screen is idle. It will be automatically upclocked when userspace triggers graphical activity. Beyond that, we can enable memory self refresh. This allows the memory to go into a lower power state when the graphics are idle. Finally, we can drop some clocks on the gpu itself. All of these things can be reenabled between frames when GPU activity is triggered, and so there should be no user visible graphical changes. Signed-off-by: Jesse Barnes <jesse.barnes@intel.com> Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: increase default latency constant (v2 w/comment)Jesse Barnes2009-09-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some i915/i945 platforms have a fairly high memory latency in certain situations, so increase our constant a bit to avoid FIFO underruns. The effect should be positive on other platforms as well; we'll have a bit more insurance against a busy memory subsystem due to the extra FIFO entries. Fixes fdo bug #23368. Needed for 2.6.31. Tested-by: Sven Arvidsson <sa@whiz.se> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Set crtc/clone mask in different output devicesMa Ling2009-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Bspec each encoder has different sharing pipe property, i.e. Integrated or SDVO TV both will occupy one pipe exclusively, and sdvo-non-tv and crt are allowed to share one. The patch moves sharing judgment into differnet output functions, and sets the right clone bit. This fixes both HDMI outputs choosing the same pipe. https://bugs.freedesktop.org/show_bug.cgi?id=22247 Signed-off-by: Ma Ling <ling.ma@intel.com> Reviewed-by : Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Always use SDVO_B detect bit for SDVO output detection.Ma Ling2009-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After the following commit is shipped, the SDVO C detection will depend on the SDVO_C/DP detion bit. commit 13520b051e8888dd3af9bda639d83e7df76613d1 Author: Kristian Høgsberg <krh@redhat.com> Date: Fri Mar 13 15:42:14 2009 -0400 drm/i915: Read the right SDVO register when detecting SVDO/HDMI. According to the spec we should continue to detect the SDVO_B/C based on the SDVO_B detection bit. The new detection bit on G4X platform is for the HDMI_C detection rather than SDVO_C detection. https://bugs.freedesktop.org/show_bug.cgi?id=20639 Signed-off-by: Ma Ling <ling.ma@intel.com> Acked-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Check if BIOS enabled dual-channel LVDS on 8xx, not only on 9xxBruno Prémont2009-08-24
| | | | | | | | | | | | | | | | | | | | Commit 0c2e39525b3b53a97a0202c5f35058147e53977e is not sufficient to get fd.o bug #20115 fixed. In addition intel_find_best_PLL() must not only rely on BIOS settings for i9xx chips but also for i8xx, so drop the IS_I9XX() check. Signed-off-by: Bruno Prémont <bonbons@linux-vserver.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Set the multiplier for SDVO on G33 platformSean Young2009-08-24
| | | | | | | | | | | | | | | | | | http://bugs.freedesktop.org/show_bug.cgi?id=21417 Signed-off-by: Sean Young <sean@mess.org> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com> Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/kms: move driver specific fb common code to helper functions (v2)Dave Airlie2009-08-30
|/ | | | | | | | | | | | | | | | | | | | | | | Initially I always meant this code to be shared, but things ran away from me before I got to it. This refactors the i915 and radeon kms fbdev interaction layers out into generic helpers + driver specific pieces. It moves all the panic/sysrq enhancements to the core file, and stores a linked list of kernel fbs. This could possibly be improved to only store the fb which has fbcon on it for panics etc. radeon retains some specific codes used for a big endian workaround. changes: fix oops in v1 fix freeing path for crtc_info Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/i915: Add support for dual-channel LVDS on 8xx.ling.ma@intel.com2009-07-30
| | | | | | | This corresponds to a fix to UMS back in 2007. Fixes fd.o bug #20115. Signed-off-by: Ma Ling <ling.ma@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: fix 845G FIFO size & burst lengthJesse Barnes2009-07-29
| | | | | | | | | | | | | | | | | | | I had one report of flicker due to FIFO underruns on 845G. Scott was kind enough to test a few patches and report success with this one. Looks like 845G measures FIFO size slightly differently than other chips, and we were also clobbering the FIFO burst length. Fixing both of those issues gives him a healthy machine again. Note that we still only adjust plane A's watermark in the 830/845 case. If someone is willing to test we could support a bigger variety of dual-head 830/845 configurations with a bit more code. Fixes fdo bug #19304 (again). Reported-by: Scott Hansen <scottandchrystie@comcast.net> Tested-by: Scott Hansen <scottandchrystie@comcast.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Add eDP support on IGDNG mobile chipZhenyu Wang2009-07-29
| | | | | | | | | | | | | This adds embedded DisplayPort support on next mobile chip which aims to replace origin LVDS port. VBT's driver feature block has been used to determine the type of current internal panel for eDP or LVDS. Currently no panel fitting support for eDP and backlight control would be added in future. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: enable DisplayPort support on IGDNGZhenyu Wang2009-07-29
| | | | | Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: fix issue in display pipe setup on IGDNGZhenyu Wang2009-07-29
| | | | | | | | | | | During pipe DPMS off, instead of busy waiting pipe off, insert delays during wait and don't loop after enough tries which matches spec requirement. Also try to match DPMS on path by disable FDI TX PLL in DPMS off. Disable PF by writing PF_WIN_SZ which really trigger the update. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: disable VGA plane reliablyZhenyu Wang2009-07-29
| | | | | | | | | This does VGA disable like DDX driver. SR01 bit 5 should be set before VGA plane disable through control register, otherwise we might get random crash and lockups. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: correct self-refresh calculation in "everything off" caseJesse Barnes2009-07-16
| | | | | | | | | | | If no planes are enabled, the self-refresh calculation may end up doing a divide by zero. This patch should prevent that by making sure at least one of the CRTCs had a valid hdisplay value. Reported-by: Eric Anholt <eric@anholt.net> Tested-by: Eric Anholt <eric@anholt.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: handle FIFO oversubsription correctlyJesse Barnes2009-07-16
| | | | | | | | | | | | | If you're pushing a plane hard (i.e. you need most or all of the FIFO entries just to cover your frame refresh latency), the watermark level may end up being negative. So fix up the signed vs. unsigned math in the calculation function to handle this correctly, giving all available FIFO entries to such a configuration. Reported-by: Eric Anholt <eric@anholt.net> Tested-by: Eric Anholt <eric@anholt.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: FIFO watermark calculation fixesJesse Barnes2009-07-14
| | | | | | | | | | | | | | | | | | | | | I discovered several bugs in the FIFO code that was recently applied. Some of them fell into the "how did this ever work" category, since in some cases we were using the wrong FIFO size values, and the calculations ended up being way off. This patch fixes all the bugs I found, and works well on my GM45, 915GM and 855GM test machines; but as usual with these sorts of patches broader testing is definitely requested (in particular this patch affects 830, 845 and 865 for which I don't have test hardware). Overall, the patch clarifies the watermark calculation function by adding some comments and debug info, and making the variable names a bit clearer. The "get FIFO size" portion of the code has also been corrected, so we should be able to properly detect the FIFO allocations for each pipe, for use in the watermark calculation. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
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