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path: root/drivers/gpu/drm/i915/intel_display.c
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* drm/i915: split out PCH refclk update codeJesse Barnes2011-08-09
| | | | | | | | | We ought to be calling this from our DPMS routines as well as global state may change and we need to enable/disable clocks. So split out the code in preparation for further changes. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: Remove unused 'reg' argument to dp_pipe_enabledKeith Packard2011-08-08
| | | | | | | Just an extra parameter which isn't actually needed. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* drm/i915: Fix PCH port pipe select in CPT disable pathsKeith Packard2011-08-08
| | | | | | | | | | | | | | | CPT pipe select is different from previous generations (using two bits instead of one). All of the paths from intel_disable_pch_ports were not making this distinction. Mode setting with pipe A turned off would then also force all outputs on pipe B to get turned off as the disable code would mistakenly decide that all of these outputs were on pipe A and turn them off. This is an extension of the CPT DP disable fix (why didn't I fix this then?) Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* drm/i915: don't use uninitialized EDID bpc values when picking pipe bppJesse Barnes2011-08-01
| | | | | | | | | | | The EDID parser will zero out the bpc value, and the driver needs to handle that case. In our picker, we'll just ignore 0 values as far as bpp picking goes. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=39323. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard2011-07-29
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| * drm/i915: apply phase pointer override on SNB+ tooJesse Barnes2011-07-29
| | | | | | | | | | | | | | | | | | | | | | These bits moved around on SNB and above. v2: again with the git send-email fail v3: add macros for getting per-pipe override & enable bits v4: enable phase sync pointer on SNB and IVB configs as well Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
| * drm/i915: Add quirk to disable SSC on Sony Vaio Y2Michel Alexandre Salim2011-07-29
| | | | | | | | | | | | | | | | | | | | | | | | Using the new quirk added to support disabling SSC on Lenovo U160 (#36656, commit 435793dfb8aec7b2e19f72d5bce8a22fd0b57839), also register the Vaio as a special case and disable SSC for it. This patch fixes #34437 on fdo bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34437 Signed-off-by: Michel Alexandre Salim <salimma@fedoraproject.org> Signed-off-by: Keith Packard <keithp@keithp.com>
| * drm/i915: provide more error output when mode sets failJesse Barnes2011-07-29
| | | | | | | | | | | | | | | | | | | | If a mode set fails we may get a message from drm_crtc_helper if we're lucky, but it won't tell us anything about *why* we failed to set a mode. So add a few DRM_ERRORs for the cases that shouldn't happen so we can debug things more easily. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
| * drm/i915: fix CB tuning check for ILK+Jesse Barnes2011-07-28
| | | | | | | | | | | | | | | | | | | | | | | | CB tuning is needed to handle potential process variations that might cause clock jitter for certain PLL settings. However, we were setting it incorrectly since we were using the wrong M value as a check (M1 when we needed to use the whole M value). Fix it up, making my HDMI attached display a little prettier (used to have occasional dots crawl across the display). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* | Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard2011-07-28
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| * drm/i915: Flush other plane register writesKeith Packard2011-07-28
| | | | | | | | | | | | | | | | | | | | | | | | | | Writes to the plane control register are buffered in the chip until a write to the DSPADDR (pre-965) or DSPSURF (post-965) register occurs. This patch adds flushes in: intel_enable_plane gen6_init_clock_gating ivybridge_init_clock_gating Signed-off-by: Keith Packard <keithp@keithp.com>
| * drm/i915: flush plane control changes on ILK+ as wellJesse Barnes2011-07-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After writing to the plane control reg we need to write to the surface reg to trigger the double buffered register latch. On previous chipsets, writing to DSPADDR was enough, but on ILK+ DSPSURF is the reg that triggers the double buffer latch. v2: write DSPADDR too to cover pre-965 chipsets v3: use flush_display_plane instead, that's what it's for v4: send the right patch Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Keith Packard <keithp@keithp.com> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
| * drm/i915: apply timing generator bug workaround on CPT and PPTJesse Barnes2011-07-28
| | | | | | | | | | | | | | | | | | | | | | On CougarPoint and PantherPoint PCH chips, the timing generator may fail to start after DP training completes. This is due to a bug in the FDI autotraining detect logic (which will stall the timing generator and re-enable it once training completes), so disable it to avoid silent DP mode setting failures. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
| * drm/i915: Set crtc DPMS mode to ON in intel_crtc_mode_setKeith Packard2011-07-28
| | | | | | | | | | | | | | | | This corrects the DPMS mode tracking so that the DPMS code will actually turn the CRTC off the next time the screen saves. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * drm/i915: DP_PIPE_ENABLED must check transcoder on CPTKeith Packard2011-07-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Display port pipe selection on CPT is not done with a bit in the output register, rather it is controlled by a couple of bits in the separate transcoder register which indicate which display port output is connected to the transcoder. This patch replaces the simplistic macro DP_PIPE_ENABLED with the rather more complicated function dp_pipe_enabled which checks the output register to see if that is enabled, and then goes on to either check the output register pipe selection bit (on non-CPT) or the transcoder DP selection bits (on CPT). Before this patch, any time the mode of pipe A was changed, any display port outputs on pipe B would get disabled as intel_disable_pch_ports would ensure that the mode setting operation could occur on pipe A without interference from other outputs connected to that pch port Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Adam Jackson <ajax@redhat.com>
* | Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard2011-07-22
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| * drm/i915: load the LUT before pipe enable on ILK+Jesse Barnes2011-07-22
| | | | | | | | | | | | | | | | | | Per the specs and to address https://bugs.freedesktop.org/show_bug.cgi?id=36888. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: stable@kernel.org Signed-off-by: Keith Packard <keithp@keithp.com>
| * drm/i915: Add quirk to disable SSC on Lenovo U160 LVDSKeith Packard2011-07-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've tried several times to make this machine 'just work', but every patch that does causes many other machines to fail. This adds a quirk which special cases this hardware and forces ssc to be disabled. There's no way to override this from the command line; that would be a significantly more invasive change. This patch fixes #36656 on fdo bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36656 Signed-off-by: Keith Packard <keithp@keithp.com> References: https://bugs.freedesktop.org/show_bug.cgi?id=36656 Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: provide more error output when mode sets failJesse Barnes2011-07-21
| | | | | | | | | | | | | | | | | | | | If a mode set fails we may get a message from drm_crtc_helper if we're lucky, but it won't tell us anything about *why* we failed to set a mode. So add a few DRM_ERRORs for the cases that shouldn't happen so we can debug things more easily. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Share the common work of disabling active FBC before updatingChris Wilson2011-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upon review, all path share the same dependencies for updating the registers and so we can benefit from sharing the code and checking early. This removes the unsightly intel_wait_for_vblank() from the lowlevel functions and upon further analysis the only path that will require a wait is if we are performing an instantaneous transition between two valid FBC configurations. The page-flip path itself will have disabled FBC registers and will have waited for at least one vblank before finishing the flip and attempting to re-enable FBC. This wait can be accomplished simply by delaying the enable until after we are sure that a vblank will have passed, which we are already doing to make sure that the display is settled before enabling FBC. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Perform intel_enable_fbc() from a delayed taskChris Wilson2011-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | In order to accommodate the requirements of re-enabling FBC after page-flipping, but to avoid doing so and incurring the cost of a wait for vblank in the middle of a page-flip sequence, we defer the actual enablement by 50ms. If any request to disable FBC arrive within that interval, the enablement is cancelled and we are saved from blocking on the wait. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Disable FBC across page-flippingChris Wilson2011-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Page-flipping updates the scanout address, nukes the FBC compressed image and so forces an FBC update so that the displayed image remains consistent. However, page-flipping does not update the FBC registers themselves, which remain pointing to both the old address and the old CPU fence. Future updates to the new front-buffer (scanout) are then undetected! This first approach to demonstrate the issue and highlight the fix, simply disables FBC upon page-flip (a recompression will be forced on every flip so FBC becomes immaterial) and then re-enables FBC in the page-flip finish work function, so that the FBC registers are now pointing to the new framebuffer and front-buffer rendering works once more. Ideally, we want to only re-enable FBC after page-flipping is complete, as otherwise we are just wasting cycles and power (with needless recompression) whilst the page-flipping application is still running. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33487 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Set persistent-mode for ILK/SNB framebuffer compressionChris Wilson2011-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Persistent mode is intended for use with front-buffer rendering, such as X, where it is necessary to detect writes to the scanout either by the GPU or through the CPU's fence, and recompress the dirty regions on the fly. (By comparison to the back-buffer rendering, the scanout is always recompressed after a page-flip.) References: https://bugs.freedesktop.org/show_bug.cgi?id=33487 References: https://bugs.freedesktop.org/show_bug.cgi?id=31742 Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Use of a CPU fence is mandatory to update FBC regions upon CPU writesChris Wilson2011-07-08
| | | | | | | | | | | | | | | | | | ...and this requirement is enforced by intel_update_fbc() so we can remove the later check from g4x_enable_fbc() and ironlake_enable_fbc(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Remove vestigial pitch from post-gen2 FBC control routinesChris Wilson2011-07-08
| | | | | | | | | | | | | | | | | | | | The cfb_pitch was only used for 8xx_enable_fbc(), every later routine was just overwriting the value with itself thanks to a copy'n'paste error. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Replace direct calls to vfunc.disable_fbc with intel_disable_fbc()Chris Wilson2011-07-08
| | | | | | | | | | | | | | ...to ensure that any pending FBC enable tasklet is cancelled. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Only export the generic intel_disable_fbc() interfaceChris Wilson2011-07-08
| | | | | | | | | | | | | | | | | | | | | | As the enable/disable routines will be gain additional complexity in future patches, it is necessary that all callers do not bypass the generic interface by calling into the chipset routines directly. to do this we make the chipset routines static, so there is no choice. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: check for supported depth at fb init timeJesse Barnes2011-07-07
| | | | | | | | | | | | | | | | This will catch bad fb configs earlier. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: split out plane update codeJesse Barnes2011-07-07
| | | | | | | | | | | | | | | | | | | | | | Updating the planes is device specific, so create a new display callback and use it in pipe_set_base. (In fact we could go even further, valid display plane bits have changed with each generation, as has tiled buffer handling.) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: split out Ironlake pipe bpp picking codeJesse Barnes2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Figuring out which pipe bpp to use is a bit painful. It depends on both the encoder and display configuration attached to a pipe. For instance, to drive a 24bpp framebuffer out to an 18bpp panel, we need to use 6bpc on the pipe but also enable dithering. But driving that same framebuffer to a DisplayPort output on another pipe means using 8bpc and no dithering. So split out and enhance the code to handle the various cases, returning an appropriate pipe bpp as well as whether dithering should be enabled. Save the resulting pipe bpp in the intel_crtc struct for use by encoders in calculating bandwidth requirements (defaults to 24bpp on pre-ILK). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: set bpc for DP transcoderJesse Barnes2011-07-07
| | | | | | | | | | | | | | | | | | | | This may not be the default value, so pull the bpc out of the pipe reg and write it to the DP transcoder so proper dithering and signaling occurs. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: don't set transcoder bpc on CougarPointJesse Barnes2011-07-07
| | | | | | | | | | | | | | | | This prevents us from setting reserved or incorrect bits on CougarPoint. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: enable ring freq scaling, RC6 and graphics turbo on Ivy Bridge v3Jesse Barnes2011-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | They use the same register interfaces, so we can simply enable the existing code on IVB. v2: - resolve conflict with ring freq scaling, we can enable it too v3: - resolve conflict again, this time on drm-intel-next Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: load a ring frequency scaling table v3Jesse Barnes2011-06-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ring frequency scaling table tells the PCU to treat certain GPU frequencies as if they were a given CPU frequency for purposes of scaling the ring frequency. Normally the PCU will scale the ring frequency based on the CPU P-state, but with the table present, it will also take the GPU frequency into account. The main downside of keeping the ring frequency high while the CPU is at a low frequency (or asleep altogether) is increased power consumption. But then if you're keeping your GPU busy, you probably want the extra performance. v2: - add units to debug table header (from Eric) - use tsc_khz as a fallback if the cpufreq driver doesn't give us a freq (from Chris) v3: - fix comments & debug output - remove unneeded force wake get/put Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* | Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard2011-06-26
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| * drm/i915: add Ivy Bridge page flip supportJesse Barnes2011-06-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the blit ring for submitting flips since the render ring doesn't generate flip complete interrupts. Fixes bugs: https://bugs.freedesktop.org/show_bug.cgi?id=38362 https://bugs.freedesktop.org/show_bug.cgi?id=38392 https://bugs.freedesktop.org/show_bug.cgi?id=38393 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: Jian J Zhao <jian.j.zhao@intel.com> Signed-off-by: Keith Packard <keithp@keithp.com>
| * drm/i915: split page flip queueing into per-chipset functionsJesse Barnes2011-06-26
| | | | | | | | | | | | | | | | | | This makes things a little clearer and prevents us from running old code on a new chipset that may not be supported. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewied-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
| * drm/i915: Call intel_enable_plane from i9xx_crtc_mode_set (again)Keith Packard2011-06-21
| | | | | | | | | | | | | | This change got placed in the ironlake path instead of the 9xx path during a recent code shuffle. Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Combine pinning with setting to the display planeChris Wilson2011-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | We need to perform a few operations in order to move the object into the display plane (where it can be accessed coherently by the display engine) that are important for future safety to forbid whilst pinned. As a result, we want to need to perform some of the operations before pinning, but some are required once we have been bound into the GTT. So combine the pinning performed by all the callers with set_to_display_plane(), so this complication is contained within the single function. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Mark the cursor and the overlay as being part of the display planesChris Wilson2011-06-10
| | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Introduce i915_gem_object_finish_gpu()Chris Wilson2011-06-09
| | | | | | | | | | | | | | | | | | | | ... reincarnated from i915_gem_object_flush_gpu(). The semantic difference is that after calling finish_gpu() the object no longer resides in any GPU domain, and so will cause the GPU caches to be invalidated if it is ever used again. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Call intel_enable_plane from i9xx_crtc_mode_set (again)Keith Packard2011-06-09
|/ | | | | | | This change got placed in the ironlake path instead of the 9xx path during a recent code shuffle. Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: Replace ironlake_compute_wm0 with g4x_compute_wm0Chris Wilson2011-06-04
| | | | | | | | | | | | | | | The computation of the first-level watermarks for g4x and gen5+ are based on the same algorithm, so we can refactor those code paths to use a single function. Note that g4x_compute_wm0 takes a 'plane' argument while ironlake_compute_wm0 took a 'pipe' argument. Both should have used a 'plane' argument, so this patch fixes that as well (not that it caused a problem; ironlake always uses pipe == plane). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: fix regression after clock gating init splitJason Stubbs2011-06-04
| | | | | | | | | | | During the refactoring in revision 6067aaeadb5b3df26f27ac827256b1ef01e674f5, the intel_enable_clock_gating was split up into several functions that are then called indirectly. However, which function to call was not specified for the IS_PINEVIEW() case. This patch specifies the correct gating function. Signed-off-by: Jason Stubbs <jasonbstubbs@gmail.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* Merge branch 'drm-core-next' of ↵Linus Torvalds2011-05-24
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (169 commits) drivers/gpu/drm/radeon/atom.c: fix warning drm/radeon/kms: bump kms version number drm/radeon/kms: properly set num banks for fusion asics drm/radeon/kms/atom: move dig phy init out of modesetting drm/radeon/kms/cayman: fix typo in register mask drm/radeon/kms: fix typo in spread spectrum code drm/radeon/kms: fix tile_config value reported to userspace on cayman. drm/radeon/kms: fix incorrect comparison in cayman setup code. drm/radeon/kms: add wait idle ioctl for eg->cayman drm/radeon/cayman: setup hdp to invalidate and flush when asked drm/radeon/evergreen/btc/fusion: setup hdp to invalidate and flush when asked agp/uninorth: Fix lockups with radeon KMS and >1x. drm/radeon/kms: the SS_Id field in the LCD table if for LVDS only drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices drm/radeon/kms: fixup eDP connector handling drm/radeon/kms: bail early for eDP in hotplug callback drm/radeon/kms: simplify hotplug handler logic drm/radeon/kms: rewrite DP handling drm/radeon/kms/atom: add support for setting DP panel mode drm/radeon/kms: atombios.h updates for DP panel mode ...
| * Merge remote branch 'keithp/drm-intel-next' of ../drm-next into drm-core-nextDave Airlie2011-05-19
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'keithp/drm-intel-next' of ../drm-next: drm/i915: initialize gen6 rps work queue on Sandy Bridge and Ivy Bridge drm/i915/sdvo: Reorder i2c initialisation before ddc proxy drm/i915: FDI link training broken on Ironlake by Ivybridge integration drm/i915: enable rc6 by default drm/i915: add fbc enable flag, but disable by default drm/i915: clean up unused ring_get_irq/ring_put_irq functions drm/i915: fix user irq miss in BSD ring on g4x
| | * drm/i915: FDI link training broken on Ironlake by Ivybridge integrationKeith Packard2011-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 357555c00f8414057f0c12ee3f479f197264123d split out IVB-specific register definitions for FDI link training, but a piece of that commit stopped executing some critical code on Ironlake systems while leaving it running on Sandybridge. Turn that code back on both Ironlake and Sandybridge Signed-off-by: Keith Packard <keithp@keithp.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| | * drm/i915: add fbc enable flag, but disable by defaultJesse Barnes2011-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FBC has too many corner cases that we don't currently deal with, so disable it by default so we can enable more important features like RC6, which conflicts in some configurations. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31742 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
| * | Merge remote branch 'keithp/drm-intel-next' of /ssd/git/drm-next into ↵Dave Airlie2011-05-15
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drm-core-next * 'keithp/drm-intel-next' of /ssd/git/drm-next: (301 commits) drm/i915: split PCH clock gating init drm/i915: add Ivybridge clock gating init function drm/i915: Update the location of the ringbuffers' HWS_PGA registers for IVB. drm/i915: Add support for fence registers on Ivybridge. drm/i915: Use existing function instead of open-coding fence reg clear. drm/i915: split clock gating init into per-chipset functions drm/i915: set IBX pch type explicitly drm/i915: add Ivy Bridge PCI IDs and driver feature structs drm/i915: add PantherPoint PCH ID agp/intel: add Ivy Bridge support drm/i915: ring support for Ivy Bridge drm/i915: page flip support for Ivy Bridge drm/i915: interrupt & vblank support for Ivy Bridge drm/i915: treat Ivy Bridge watermarks like Sandy Bridge drm/i915: manual FDI training for Ivy Bridge drm/i915: add swizzle/tiling support for Ivy Bridge drm/i915: Ivy Bridge has split display and pipe control drm/i915: add IS_IVYBRIDGE macro for checks drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later drm/i915: split enable/disable vblank code into chipset specific functions ...
| | * drm/i915: split PCH clock gating initJesse Barnes2011-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Ibex Peak and CougarPoint already require a different setting (added here), and future chips will likely follow that precedent. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-27 21:01:47 -0400