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path: root/drivers/gpu/drm/i915/i915_drv.h
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* drm/i915: add pipe A force quirks to i915 driverJesse Barnes2010-07-26
| | | | | | | | | | | | Ported over from the old UMS list. Unfortunately they're still necessary especially on older laptop platforms. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=22126. Tested-by: Xavier <shiningxc@gmail.com> Tested-by: Diego Escalante Urrelo <diegoe@gnome.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: disable FBC when more than one pipe is activeJesse Barnes2010-07-26
| | | | | | | | | | | We're really supposed to do this to avoid trouble with underflows when multiple planes are active. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=26987. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: fangxun <xunx.fang@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* Merge branch 'for-linus' of ↵Linus Torvalds2010-07-01
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: fix page flip finish vs. prepare on plane B drm/i915: change default panel fitting mode to preserve aspect ratio drm/i915: fix uninitialized variable warning in i915_setup_compression() drm/i915: take struct_mutex in i915_dma_cleanup() drm/i915: Fix CRT hotplug regression in 2.6.35-rc1 i915: fix ironlake edp panel setup (v4) drm/i915: don't access FW_BLC_SELF on 965G drm/i915: Account for space on the ring buffer consumed whilst wrapping. drm/i915: gen3 page flipping fixes drm/i915: don't queue flips during a flip pending event drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer. drm/i915: Turn on 945 self-refresh only if single CRTC is active drm/i915/gen4: Fix interrupt setup ordering drm/i915: Use RSEN instead of HTPLG for tfp410 monitor detection. drm/i915: Move non-phys cursors into the GTT Revert "drm/i915: Don't enable pipe/plane/VCO early (wait for DPMS on)." (Included the "fix page flip finish vs. prepare on plane B" patch from Jesse on top of the pull request from Eric. -- Linus)
| * drm/i915: gen3 page flipping fixesJesse Barnes2010-06-18
| | | | | | | | | | | | | | | | | | | | | | | | | | Gen3 chips have slightly different flip commands, and also contain a bit that indicates whether a "flip pending" interrupt means the flip has been queued or has been completed. So implement support for the gen3 flip command, and make sure we use the flip pending interrupt correctly depending on the value of ECOSKPD bit 0. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer.Zou Nan hai2010-06-14
| | | | | | | | | | | | | | | | | | The ring_begin API was taking a number of bytes, while all of our other begin/end macros take number of dwords. Change the API over to dwords to prevent future bugs. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: fix oops on single crtc devices.Dave Airlie2010-06-07
|/ | | | | | | | | | (regression fix since fbdev/kms rework). My fb rework didn't remember about the 84/65s. Reported-by: Ondrej Zary <linux@rainbow-software.org> Tested-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/i915: Clean up leftover bits from hws move to ring structure.Eric Anholt2010-05-26
| | | | | | Fixes /debug/dri/0/i915_gem_interrupt output for status page. Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Add CxSR support on Pineview DDR3Li Peng2010-05-26
| | | | | | | | | | | | Pineview with DDR3 memory has different latencies to enable CxSR. This patch updates CxSR latency table to add Pineview DDR3 latency configuration. It also adds one flag "is_ddr3" for checking DDR3 setting in MCHBAR. Cc: Shaohua Li <shaohua.li@intel.com> Cc: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Li Peng <peng.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: combine all small integers into one single bitfieldDaniel Vetter2010-05-26
| | | | | | | | | This saves a whooping 7 dwords. Zero functional changes. Because some of the refcounts are rather tightly calculated, I've put BUG_ONs in the code to check for overflows. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: add power monitoring supportJesse Barnes2010-05-26
| | | | | | | | | | | | Add power monitoring support to the i915 driver for use by the IPS driver. Export the available power info to the IPS driver through a few new inter-driver hooks. When used together, the IPS driver and this patch can significantly increase graphics performance on Ironlake class chips. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [anholt: Fixed 32-bit compile. stupid obfuscating div_u64()] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: implement BSD ring buffer V2Zou Nan hai2010-05-26
| | | | | | | | | | | The BSD (bit stream decoder) ring is used for accessing the BSD engine which decodes video bitstream for H.264 and VC1 on G45+. It is asynchronous with the render ring and has access to separate parts of the GPU from it, though the render cache is coherent between the two. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: convert some gem structures to per-ring V2Zou Nan hai2010-05-26
| | | | | | | | | | | | The active list and request list move into the ringbuffer structure, so each can track its active objects in the order they are in that ring. The flushing list does not, as it doesn't matter which ring caused data to end up in the render cache. Objects gain a pointer to the ring they are active on (if any). Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: introduce intel_ring_buffer structure (V2)Zou Nan hai2010-05-26
| | | | | | | | | | | Introduces a more complete intel_ring_buffer structure with callbacks for setup and management of a particular ringbuffer, and converts the render ring buffer consumers to use it. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com> [anholt: Fixed up whitespace fail and rebased against prep patches] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Rename dev_priv->ring to dev_priv->render_ring.Eric Anholt2010-05-26
| | | | | | With the advent of the BSD ring, be clear about which ring this is. The docs are pretty consistent with calling this the Render engine at this point.
* drm/i915: Move ringbuffer-related code to intel_ringbuffer.c.Eric Anholt2010-05-26
| | | | | | | | | This is preparation for supporting multiple ringbuffers on Ironlake. The non-copy-and-paste changes are: - de-staticing functions - I915_GEM_GPU_DOMAINS moving to i915_drv.h to be used by both files. - i915_gem_add_request had only half its implementation copy-and-pasted out of the middle of it.
* drm/i915: move fence lru to struct drm_i915_fence_regDaniel Vetter2010-05-10
| | | | | | | | | This lru tracks fences, not objects, so move it to where it belongs. As a side effect, this nicely shrinks drm_i915_gem_object by two pointers. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix DDC bus selection for multifunction SDVOAdam Jackson2010-05-10
| | | | | | | | | | | | | | | | | | Multifunction SDVO cards stopped working after 14571b4, and would report something that looked remarkably like an ADD2 SPD ROM instead of EDID. This appears to be because DDC bus selection was utterly horked by that commit; controlled_output was no longer always a single bit, so intel_sdvo_select_ddc_bus would pick bus 0, which is (unsurprisingly) the SPD ROM bus, not a DDC bus. So, instead of that, let's just use the DDC bus the child device table tells us to use. I'm guessing at the bitmask and shifting from VBIOS dumps, but it can't possibly be worse. cf. https://bugzilla.redhat.com/584229 Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* Merge remote branch 'origin/master' into drm-intel-nextEric Anholt2010-05-10
|\ | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/gpu/drm/i915/i915_dma.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/radeon/r300.c The BSD ringbuffer support that is landing in this branch significantly conflicts with the Ironlake PIPE_CONTROL fix on master, and requires it to be tested successfully anyway.
| * drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy BridgeJesse Barnes2010-04-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 965, the hardware has supported the PIPE_CONTROL command, which provides fine grained GPU cache flushing control. On recent chipsets, this instruction is required for reliable interrupt and sequence number reporting in the driver. So add support for this instruction, including workarounds, on Ironlake and Sandy Bridge hardware. https://bugs.freedesktop.org/show_bug.cgi?id=27108 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: cleanup FBC buffers at unload timeJesse Barnes2010-04-22
| | | | | | | | | | | | | | This keeps the memory manager from complaining when we take it down. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Fix 82854 PCI ID, and treat it like other 85XAdam Jackson2010-04-18
| | | | | | | | | | | | | | pci.ids and the datasheet both say it's 358e, not 35e8. Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Make fbc control wrapper functionsAdam Jackson2010-05-07
| | | | | | | | | | Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: drop pointer to drm_gem_objectDaniel Vetter2010-04-19
| | | | | | | | | | | | | | | | | | Luckily the change is quite a little bit less invasive than I've feared. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/i915: don't use ->driver_private anymoreDaniel Vetter2010-04-19
| | | | | | | | | | | | | | | | Thanks to the to_intel_bo helper, this change is rather trivial. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/i915: embed the gem object into drm_i915_gem_objectDaniel Vetter2010-04-19
| | | | | | | | | | | | | | | | | | Just embed it and adjust the pointers, No other changes (that's for later patches). Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/i915: introduce i915_gem_alloc_objectDaniel Vetter2010-04-19
| | | | | | | | | | | | | | | | Just preparation, no functional change. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | Merge branch 'drm-fbdev-cleanup' into drm-core-nextDave Airlie2010-04-19
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * drm-fbdev-cleanup: drm/fb: remove drm_fb_helper_setcolreg drm/kms/fb: use slow work mechanism for normal hotplug also. drm/kms/fb: add polling support for when nothing is connected. drm/kms/fb: provide a 1024x768 fbcon if no outputs found. drm/kms/fb: separate fbdev connector list from core drm connectors drm/kms/fb: move to using fb helper crtc grouping instead of core crtc list drm/fb: fix fbdev object model + cleanup properly. Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/nouveau/nouveau_drv.h
| * | drm/kms/fb: move to using fb helper crtc grouping instead of core crtc listDave Airlie2010-04-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This move to using the list of crtcs in the fb helper and cleans up the whole picking code, now we store the crtc/connectors we want directly into the modeset and we use the modeset directly to set the mode. Fixes from James Simmons and Ben Skeggs. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | drm/fb: fix fbdev object model + cleanup properly.Dave Airlie2010-04-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fbdev layer in the kms code should act like a consumer of the kms services and avoid having relying on information being store in the kms core structures in order for it to work. This patch a) removes the info pointer/psuedo palette from the core drm_framebuffer structure and moves it to the fbdev helper layer, it also removes the core drm keeping a list of kernel kms fbdevs. b) migrated all the fb helper functions out of the crtc helper file into the fb helper file. c) pushed the fb probing/hotplug control into the driver d) makes the surface sizes into a structure for ease of passing This changes the intel/radeon/nouveau drivers to use the new helper. Signed-off-by: Dave Airlie <airlied@redhat.com>
* | | drm/i915: enable DP/eDP for Sandybridge/CougarpointZhenyu Wang2010-04-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DP on Cougarpoint has new training pattern definitions, and new transcoder DP control register is used to determine the mapping for transcoder and DP digital output. And eDP for Sandybridge has new voltage and pre-emphasis level definitions. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | | drm/i915: Probe for PCH chipset typeZhenyu Wang2010-04-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCH is the new name for south bridge from Ironlake/Sandybridge, which contains most of the display outputs except eDP. This one adds a probe function to detect current PCH type, and method to detect Cougarpoint PCH. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | | drm/i915: Sandybridge has no integrated TVZhenyu Wang2010-04-12
| |/ |/| | | | | | | | | | | Integrated TV is deprecated in new chips from Ironlake. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Ignore LVDS EDID when it is unavailabe or invalidZhao Yakui2010-04-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This trys to shut up complains about invalid LVDS EDID during mode probe, but uses fixed panel mode directly for panels with broken EDID. https://bugs.freedesktop.org/show_bug.cgi?id=23099 https://bugs.freedesktop.org/show_bug.cgi?id=26395 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Tested-by: Sitsofe Wheeler <sitsofe@yahoo.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: introduce to_intel_bo helperDaniel Vetter2010-03-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a purely cosmetic change to make changes in this area easier. And hey, it's not only clearer and typechecked, but actually shorter, too! [anholt: To clarify, this is a change to let us later make drm_i915_gem_object subclass drm_gem_object, instead of having drm_gem_object have a pointer to i915's private data] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Fix check with IS_GEN6Zhenyu Wang2010-03-17
|/ | | | | | | | | IS_GEN6 missed to include SandyBridge mobile chip, which failed in i915_probe_agp() for memory config detection. Fix it with a device info flag. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* Merge branch 'gpu-switcher' of /ssd/git//linux-2.6 into drm-next-stageDave Airlie2010-03-01
|\ | | | | | | | | | | | | | | | | | | | | * 'gpu-switcher' of /ssd/git//linux-2.6: vga_switcheroo: initial implementation (v15) fb: for framebuffer handover don't exit the loop early. Conflicts: drivers/gpu/drm/i915/i915_dma.c drivers/gpu/drm/radeon/Makefile drivers/gpu/drm/radeon/radeon.h
| * vga_switcheroo: initial implementation (v15)Dave Airlie2010-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many new laptops now come with 2 gpus, one to be used for low power modes and one for gaming/on-ac applications. These GPUs are typically wired to the laptop panel and VGA ports via a multiplexer unit which is controlled via ACPI methods. 4 combinations of systems typically exist - with 2 ACPI methods. Intel/ATI - Lenovo W500/T500 - use ATPX ACPI method ATI/ATI - some ASUS - use ATPX ACPI Method Intel/Nvidia - - use _DSM ACPI method Nvidia/Nvidia - - use _DSM ACPI method. TODO: This patch adds support for the ATPX method and initial bits for the _DSM methods that need to written by someone with access to the hardware. Add a proper non-debugfs interface - need to get some proper testing first. v2: add power up/down support for both devices on W500 puts i915/radeon into D3 and cuts power to radeon. v3: redo probing methods, no DMI list, drm devices call to register with switcheroo, it tries to find an ATPX method on any device and once there is two devices + ATPX it inits the switcher. v4: ATPX msg handling using buffers - should work on more machines v5: rearchitect after more mjg59 discussion - move ATPX handling to radeon driver. v6: add file headers + initial nouveau bits (to be filled out). v7: merge delayed switcher code. v8: avoid suspend/resume of gpu that is off v9: rearchitect - mjg59 is always right. - move all ATPX code to radeon, should allow simpler DSM also proper ATRM handling v10: add ATRM support for radeon BIOS, add mutex to lock vgasr_priv v11: fix bug in resuming Intel for 2nd time. v12: start fixing up nvidia code blindly. v13: blindly guess at finishing nvidia code v14: remove radeon audio hacks - fix up intel resume more like upstream v15: clean up printks + remove unnecessary igd/dis pointers mount debugfs /sys/kernel/debug/vgaswitcheroo/switch - should exist if ATPX detected + 2 cards. DIS - immediate change to discrete IGD - immediate change to IGD DDIS - delayed change to discrete DIGD - delayed change to IGD ON - turn on not in use OFF - turn off not in use Tested on W500 (Intel/ATI) and T500 (Intel/ATI) Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge.Eric Anholt2010-02-26
| | | | | | | | Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Record batch buffer following GPU errorChris Wilson2010-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to improve our diagnostic capabilities following a GPU hang and subsequent reset, we need to record the batch buffer that triggered the error. We assume that the current batch buffer, plus a few details about what else is on the active list, will be sufficient -- at the very least an improvement over nothing. The extra information is stored in /debug/dri/.../i915_error_state following an error, and may be decoded using intel_gpu_tools/tools/intel_error_decode. v2: Avoid excessive work under spinlocks. v3: Include ringbuffer for later analysis. v4: Use kunmap correctly and record more buffer state. v5: Search ringbuffer for current batch buffer v6: Use a work fn for the impossible IRQ error case. v7: Avoid non-atomic paths whilst in IRQ context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: reduce some of the duplication of tiling checkingOwain Ainsworth2010-02-22
| | | | | | | | | | | | | | | | | | | | i915_gem_object_fenceable was mostly just a repeat of the i915_gem_object_fence_offset_ok, but also checking the size (which was checkecd when we allowed that BO to be tiled in the first place). So instead, export the latter function and use it in place. Signed-Off-By: Owain G. Ainsworth <oga@openbsd.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: provide FBC status in debugfsJesse Barnes2010-02-22
| | | | | | | | | | | | | | | | | | Tools like powertop want to check the current FBC status and report it to the user. So add a debugfs file indicating whether FBC is enabled, and if not, why. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Deobfuscate the render p-state obfuscationMatthew Garrett2010-02-22
| | | | | | | | | | | | | | | | The ironlake render p-state support includes some rather odd variable names. Clean them up in order to improve the readability of the code. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: add dynamic performance control support for IronlakeJesse Barnes2010-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ironlake (and 965GM, which this patch doesn't support) supports a hardware performance and power management feature that allows it to adjust to changes in GPU load over time with software help. The goal if this is to maximize performance/power for a given workload. This patch enables that feature, which is also a requirement for supporting Intelligent Power Sharing, a feature which allows for dynamic budgeting of power between the CPU and GPU in Arrandale platforms. Tested-by: ykzhao <yakui.zhao@intel.com> [anholt: Resolved against the irq handler loop removal] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Keep MCHBAR always enabledZhenyu Wang2010-02-16
|/ | | | | | | | | As we need more and more controls within MCHBAR for memory config and power management, this trys to keep MCHBAR enabled from driver load and only tear down in driver unload. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Update write_domains on active list after flush.Daniel Vetter2010-02-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before changing the status of a buffer with a pending write we will await upon a new flush for that buffer. So we can take advantage of any flushes posted whilst the buffer is active and pending processing by the GPU, by clearing its write_domain and updating its last_rendering_seqno -- thus saving a potential flush in deep queues and improves flushing behaviour upon eviction for both GTT space and fences. In order to reduce the time spent searching the active list for matching write_domains, we move those to a separate list whose elements are the buffers belong to the active/flushing list with pending writes. Orignal patch by Chris Wilson <chris@chris-wilson.co.uk>, forward-ported by me. In addition to better performance, this also fixes a real bug. Before this changes, i915_gem_evict_everything didn't work as advertised. When the gpu was actually busy and processing request, the flush and subsequent wait would not move active and dirty buffers to the inactive list, but just to the flushing list. Which triggered the BUG_ON at the end of this function. With the more tight dirty buffer tracking, all currently busy and dirty buffers get moved to the inactive list by one i915_gem_flush operation. I've left the BUG_ON I've used to prove this in there. References: Bug 25911 - 2.10.0 causes kernel oops and system hangs http://bugs.freedesktop.org/show_bug.cgi?id=25911 Bug 26101 - [i915] xf86-video-intel 2.10.0 (and git) triggers kernel oops within seconds after login http://bugs.freedesktop.org/show_bug.cgi?id=26101 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Adam Lantos <hege@playma.org> Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Selectively enable self-reclaimChris Wilson2010-01-27
| | | | | | | | | | | | | | | | | | | | | | | | Having missed the ENOMEM return via i915_gem_fault(), there are probably other paths that I also missed. By not enabling NORETRY by default these paths can run the shrinker and take memory from the system (but not from our own inactive lists because our shrinker can not run whilst we hold the struct mutex) and this may allow the system to survive a little longer whilst our drivers consume all available memory. References: OOM killer unexpectedly called with kernel 2.6.32 http://bugzilla.kernel.org/show_bug.cgi?id=14933 v2: Pass gfp into page mapping. v3: Use new read_cache_page_gfp() instead of open-coding. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Cc: Hugh Dickins <hugh.dickins@tiscali.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Eric Anholt <eric@anholt.net> Cc: stable@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* drm/i915: parse eDP panel color depth from VBT blockZhenyu Wang2010-01-15
| | | | | Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: disable LVDS downclock by defaultJesse Barnes2010-01-15
| | | | | | | | | | | | | | | Many platform support this feature, and it can provide significant power savings when the reduced refresh rate is low. However, on some platforms a secondary (reduced) timing is provided but not actually supported by the hardware. This results in undesirable flicker at runtime. So disable the feature by default, but allow users to opt-in to the reduced clock behavior with a new module parameter, lvds_downclock, that can be set to 1 to enable the feature. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Don't wait interruptible for possible plane buffer flushZhenyu Wang2010-01-12
| | | | | | | | | | | | | | | | | | | When we setup buffer for display plane, we'll check any pending required GPU flush and possible make interruptible wait for flush complete. But that wait would be most possibly to fail in case of signals received for X process, which will then fail modeset process and put display engine in unconsistent state. The result could be blank screen or CPU hang, and DDX driver would always turn on outputs DPMS after whatever modeset fails or not. So this one creates new helper for setup display plane buffer, and when needing flush using uninterruptible wait for that. This one should fix bug like https://bugs.freedesktop.org/show_bug.cgi?id=24009. Also fixing mode switch stress test on Ironlake. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix RC6 suspend/resumeAndrew Lutomirski2010-01-06
| | | | | | | | | We restored RC6 twice on resume, even with modesetting off. Instead, only restore it once and skip RC6 initialization entirely in non-KMS mode. Signed-off-by: Andy Lutomirski <luto@mit.edu> Tested-by: Jeff Chua <jeff.chua.linux@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
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