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* Merge branch 'perf/mce' into perf/coreIngo Molnar2009-12-03
|\ | | | | | | | | | | Merge reason: It's ready for v2.6.33. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * mce, edac: Use an atomic notifier for MCEs decodingBorislav Petkov2009-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | Add an atomic notifier which ensures proper locking when conveying MCE info to EDAC for decoding. The actual notifier call overrides a default, negative priority notifier. Note: make sure we register the default decoder only once since mcheck_init() runs on each CPU. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> LKML-Reference: <20091003065752.GA8935@liondog.tnic> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | amd64_edac: fix CECCs reportingBorislav Petkov2009-11-04
| | | | | | | | | | | | Shift error type bits properly. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* | amd64_edac: fix a wrong goto clause in amd64_edac.cLi Hong2009-11-04
| | | | | | | | | | | | | | | | | | | | In amd64_edac_init(void) in amd64_edac.c, cache_k8_northbridges() is called before pci_register_driver. If it fails, should exit with err directly. Signed-off-by: Li Hong <lihong.hi@gmail.com> Acked-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* | edac: i5100 fix initialization codeKeith Mannthey2009-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow csrows to properly initialize when the topology only has active channels on 2 and 3. This new check allows proper detection and initialization in this topology. Only checking the first mrt that represented channels 0 and 1 is not sufficient. I also fixed up the related debug information path. I can submit as a 2nd patch if needed. Signed-off-by: Keith Mannthey <kmannth@us.ibm.com> Acked-by: Aristeu Rozanski <aris@ruivo.org> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | edac: i5400 fix missing CONFIG_PCI defineIra W. Snyder2009-10-29
| | | | | | | | | | | | | | | | | | | | | | When building without CONFIG_PCI the edac_pci_idx variable is unused, causing a build-time warning. Wrap the variable in #ifdef CONFIG_PCI, just like the rest of the PCI support. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | edac: i5400 fix csrow mappingJeff Roberson2009-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i5400 EDAC driver has several bugs with chip-select row computation which most likely lead to bugs in detailed error reporting. Attempts to contact the authors have gone mostly unanswered so I am presenting my diff here. I do not subscribe to lkml and would appreciate being kept in the cc. The most egregious problem was miscalculating the addresses of MTR registers after register 0 by assuming they are 32bit rather than 16. This caused the driver to miss half of the memories. Most motherboards tend to have only 8 dimm slots and not 16, so this may not have been noticed before. Further, the row calculations multiplied the number of dimms several times, ultimately ending up with a maximum row of 32. The chipset only supports 4 dimms in each of 4 channels, so csrow could not be higher than 4 unless you use a row per-rank with dual-rank dimms. I opted to eliminate this behavior as it is confusing to the user and the error reporting works by slot and not rank. This gives a much clearer view of memory by slot and channel in /sys. Signed-off-by: Jeff Roberson <jroberson@jroberson.net> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | amd64_edac: fix DRAM base and limit extraction masks, v2Borislav Petkov2009-10-16
|/ | | | | | This is a proper fix as a follow-up to 66216a7 and 916d11b. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* Merge branch 'x86-fixes-for-linus' of ↵Linus Torvalds2009-10-08
|\ | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, pci: Correct spelling in a comment x86: Simplify bound checks in the MTRR code x86: EDAC: carve out AMD MCE decoding logic initcalls: Add early_initcall() for modules x86: EDAC: MCE: Fix MCE decoding callback logic
| * x86: EDAC: carve out AMD MCE decoding logicBorislav Petkov2009-10-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts the MCE decoding logic into a standalone config option which can be built-in or a module, the first one being the default for MCEs happening early on in the boot process. This, beyond being separated in a cleaner way, also saves RAM by making the decoding logic modular. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andi Kleen <andi@firstfloor.org> LKML-Reference: <20091002133148.GD28682@aftab> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86: EDAC: MCE: Fix MCE decoding callback logicIngo Molnar2009-10-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make decoding of MCEs happen only on AMD hardware by registering a non-default callback only on CPU families which support it. While looking at the interaction of decode_mce() with the other MCE code i also noticed a few other things and made the following cleanups/fixes: - Fixed the mce_decode() weak alias - a weak alias is really not good here, it should be a proper callback. A weak alias will be overriden if a piece of code is built into the kernel - not good, obviously. - The patch initializes the callback on AMD family 10h and 11h. - Added the more correct fallback printk of: No support for human readable MCE decoding on this CPU type. Transcribe the message and run it through 'mcelog --ascii' to decode. On CPUs that dont have a decoder. - Made the surrounding code more readable. Note that the callback allows us to have a default fallback - without having to check the CPU versions during the printout itself. When an EDAC module registers itself, it can install the decode-print function. (there's no unregister needed as this is core code.) version -v2 by Borislav Petkov: - add K8 to the set of supported CPUs - always build in edac_mce_amd since we use an early_initcall now - fix checkpatch warnings Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andi Kleen <andi@firstfloor.org> LKML-Reference: <20091001141432.GA11410@aftab> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | amd64_edac: beef up DRAM error injectionBorislav Petkov2009-10-07
| | | | | | | | | | | | | | | | | | | | | | | | | | When injecting DRAM ECC errors (F3xBC_x8), EccVector[15:0] is a bitmask of which bits should be error injected when written to and holds the payload of 16-bit DRAM word when read, respectively. Add /sysfs members to show the DRAM ECC section/word/vector. Fail wrong injection values entered over /sysfs instead of truncating them. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* | amd64_edac: fix DRAM base and limit extractionBorislav Petkov2009-10-07
| | | | | | | | | | | | | | | | | | On Fam10h and above, F1x[1, 0][7C:40] are DRAM Base/Limit registers which specify the destination node of a DRAM address. Those address boundaries are being extracted into ->dram_base[] and ->dram_limit[]. Correct the extraction masks to match the respective address bits. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* | amd64_edac: fix chip select handlingBorislav Petkov2009-10-07
| | | | | | | | | | | | | | | | | | | | | | | | Different processor families support a different number of chip selects. Handle this in a family-dependent way with the proper values assigned at init time (see amd64_set_dct_base_and_mask). Remove _DCSM_COUNT defines since they're used at one place and originate from public documentation. CC: Keith Mannthey <kmannth@us.ibm.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* | amd64_edac: simple fix to allow reporting of CECC errorsKeith Mannthey2009-10-07
| | | | | | | | | | | | | | | | This allows the errors to be further decoded and mapped to csrows. Tested with ECC debug dimms and an Rev F cpu based system. Signed-off-by: Keith Mannthey <kmannth@us.ibm.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* | amd64_edac: fix K8 intlv_sel checkBorislav Petkov2009-10-07
| | | | | | | | | | | | | | | | | | The check when DRAM interleaving is enabled should be done against the pvt->dram_IntlvSel field and not against the ->dram_limit. Simplify first loop and fixup printk formatting while at it. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* | amd64_edac: fix interleave enable testsBorislav Petkov2009-10-07
| | | | | | | | | | | | | | | | The pvt->dram_IntlvEn saves the 3 "Interleave Enable" bits already right-shifted by 8 so the check in find_mc_by_sys_addr() by shifting the values to the left 8 bits is wrong. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* | amd64_edac: fix DRAM base and limit address extractionBorislav Petkov2009-10-07
| | | | | | | | | | | | | | | | K8 DRAM base and limit addresses from F1x40 +8*i and F1x44 + 8*i, where i in (0..7) are both bits 39-24 and therefore the shifting should be done by 24 and not by 8. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* | amd64_edac: fix driver instance lookup table allocationBorislav Petkov2009-10-07
|/ | | | | | | | | Allocate memory statically for 8-node machines max for simplicity instead of relying on MAX_NUMNODES which is 0 on !CONFIG_NUMA builds. Spotted by Jan Beulich. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* edac: core: remove completion-wait for complete with rcu_barrierJesper Dangaard Brouer2009-09-24
| | | | | | | | | | | | | | | | | | | Module edac_core.ko uses call_rcu() callbacks in edac_device.c, edac_mc.c and edac_pci.c. They all use a wait_for_completion() scheme, but this scheme it not 100% safe on multiple CPUs. See the _rcu_barrier() implementation which explains why extra precausion is needed. The patch adds a comment about rcu_barrier() and as a precausion calls rcu_barrier(). A maintainer needs to look at removing the wait_for_completion code. [dougthompson@xmission.com: remove the wait_for_completion code] Signed-off-by Jesper Dangaard Brouer <hawk@comx.dk> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* edac: i3200 memory controller driverJason Uhlenkott2009-09-24
| | | | | | | | | | | | | A driver for the Intel 3200 and 3210 memory controllers. It has only had light testing so far, and currently makes no attempt to decode error addresses at anything finer than csrow granularity. Signed-off-by: Jason Uhlenkott <juhlenko@akamai.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* edac: fix resource size calculationJulia Lawall2009-09-24
| | | | | | | | | | | | | | | | | | | | | | Use the function resource_size, which reduces the chance of introducing off-by-one errors in calculating the resource size. The semantic patch that makes this change is as follows: (http://www.emn.fr/x-info/coccinelle/) // <smpl> @@ struct resource *res; @@ - (res->end - res->start) + 1 + resource_size(res) // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* edac: mpc85xx add mpc83xx supportIra W. Snyder2009-09-24
| | | | | | | | | | | | | | | | | | | | | | Add support for the Freescale MPC83xx memory controller to the existing driver for the Freescale MPC85xx memory controller. The only difference between the two processors are in the CS_BNDS register parsing code, which has been changed so it will work on both processors. The L2 cache controller does not exist on the MPC83xx, but the OF subsystem will not use the driver if the device is not present in the OF device tree. I had to change the nr_pages calculation to make the math work out. I checked it on my board and did the math by hand for a 64GB 85xx using 64K pages. In both cases, nr_pages * PAGE_SIZE comes out to the correct value. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Cc: Kumar Gala <galak@gate.crashing.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* edac: mpc85xx add P2020DS supportYang Shi2009-09-24
| | | | | | | | | | | | | | | Based on Kumar's new compatible types patch, add P2020 into MPC85xx EDAC compatible lists so that EDAC can recognize P2020 meomry controller and L2 cache controller and export the relevant fields to sysfs. EDAC MPC85xx DDR3 support is needed if DDR3 memory stick is installed on a P2020DS board so that EDAC core can recognize DDR3 memory type. Signed-off-by: Yang Shi <yang.shi@windriver.com> Acked-by: Dave Jiang <djiang@mvista.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* trivial: fix typo "for for" in multiple filesAnand Gadiyar2009-09-21
| | | | | | | trivial: fix typo "for for" in multiple files Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* amd64_edac: check NB MCE bank enable on the current node properlyBorislav Petkov2009-09-16
| | | | | | | | | | | The old code was using smp_call_function_many which skips the current cpu if it is in the supplied cpumask. Switch to the rdmsr_on_cpus() interface which takes care of that. In addition, add get_cpus_on_this_dct_cpumask helper which computes a cpumask of all the cores on a node and thus on a DCT. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Rewrite unganged mode code of f10_early_channel_countWan Wei2009-09-16
| | | | | | | | | | | | Simplify the procedure by checking if there is any DIMM in each channel. This patch will fix the bugs such as when there is no DIMMs under certain node, two DIMMs in the same channel, and only one DIMM in each channel of the node. Borislav: minor fixups Signed-off-by: Wan Wei <wanwei@mail.dawning.com.cn> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: cleanup amd64_check_ecc_enabledBorislav Petkov2009-09-16
| | | | | | | | | | Simplify code flow and make sure return value is always valid since further driver init depends on it. Carve out long warning string and make code more readable. Shorten some names, while at it. There should be no functional change resulting from this patch. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* x86, EDAC: Provide function to return NodeId of a CPUAndreas Herrmann2009-09-16
| | | | | | Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Acked-by: H. Peter Anvin <hpa@zytor.com>
* amd64_edac: build driver only on AMD hardwareIngo Molnar2009-09-16
| | | | | | | | | | | | | | | | | | | | | -tip testing found the following build failure (config attached): drivers/built-in.o: In function `amd64_check': amd64_edac.c:(.text+0x3e9491): undefined reference to `amd_decode_nb_mce' drivers/built-in.o: In function `amd64_init_2nd_stage': amd64_edac.c:(.text+0x3e9b46): undefined reference to `amd_report_gart_errors' amd64_edac.c:(.text+0x3e9b55): undefined reference to `amd_register_ecc_decoder' drivers/built-in.o: In function `amd64_nbea_store': amd64_edac_dbg.c:(.text+0x3ea22e): undefined reference to `amd_decode_nb_mce' drivers/built-in.o: In function `amd64_remove_one_instance': amd64_edac.c:(.devexit.text+0x3eea): undefined reference to `amd_report_gart_errors' amd64_edac.c:(.devexit.text+0x3ef6): undefined reference to `amd_unregister_ecc_decoder' the AMD EDAC code has a dependency on CONFIG_CPU_SUP_AMD facilities. The patch below solves the problem here. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC, AMD: decode FR MCEsBorislav Petkov2009-09-14
| | | | | | See Fam10h BKDG (31116, rev. 3.28), Table 101. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC, AMD: decode load store MCEsBorislav Petkov2009-09-14
| | | | | | See Fam10h BKDG (31116, rev. 3.28), Table 100. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC, AMD: decode bus unit MCEsBorislav Petkov2009-09-14
| | | | | | ... according to Table 69, Fam10h BKDG (31116, rev. 3.28). Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC, AMD: decode instruction cache MCEsBorislav Petkov2009-09-14
| | | | | | See Fam10h BKDG (31116, rev. 3.28), Table 95 Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC, AMD: decode data cache MCEsBorislav Petkov2009-09-14
| | | | | | | Those get reported in MC0_STATUS, see Table 92, F10h BKDG (31116, rev. 3.28) for more details. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC, AMD: carve out decoding of MCi_STATUS ErrorCodeBorislav Petkov2009-09-14
| | | | | | | | | This is the MCE error code from the MCi_STATUS banks, bits [15:0] which describe what type of error was encountered: GART TLB, Memory or Bus error. The semantics of those bits are identical across all MCE banks so decode those separately, irrespectively of MCE type. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC, AMD: carve out MCi_STATUS decodingBorislav Petkov2009-09-14
| | | | | | | | The MCi_STATUS registers have most field definitions in common so decode them in the general path. Do not pass ecc_type along and compute it in __amd64_decode_bus_error instead. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* x86, mce: pass mce info to EDAC for decodingBorislav Petkov2009-09-14
| | | | | | | | | Move NB decoder along with required defines to EDAC MCE core. Add registration routines for further decoding of the MCE info in the AMD64 EDAC module. CC: Andi Kleen <andi@firstfloor.org> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: cleanup amd64_decode_bus_errorBorislav Petkov2009-09-14
| | | | Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: remove memory and GART TLB error decodersBorislav Petkov2009-09-14
| | | | Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: cleanup/complete NB MCE decodingBorislav Petkov2009-09-14
| | | | | | | | | | | * don't dump info which mcheck already does * update to newest BKDG * mv amd64_process_error_info -> amd64_decode_nb_mce * shorten error struct names * remove redundant info ptr in amd64_process_error_info * remove unused ErrorCodeExt[19:16] (MCx_STATUS) defines Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: cleanup amd64_process_error_infoBorislav Petkov2009-09-14
| | | | | | | | * mv amd64_error_info_regs -> err_regs * remove redundant info ptr Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC: beef up ErrorCodeExt error signaturesBorislav Petkov2009-09-14
| | | | Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC: move MCE error descriptions to EDAC coreBorislav Petkov2009-09-14
| | | | | | | | | | | | | | | This is in preparation of adding AMD-specific MCE decoding functionality to the EDAC core. The error decoding macros originate from the AMD64 EDAC driver albeit in a simplified and cleaned up version here. While at it, add macros to generate the error description strings and use them in the error type decoders directly which removes a bunch of code and makes the decoding functions much more readable. Also, fix strings and shorten macro names. Remove superfluous htlink_msgs. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: print debug statements only on errorDoug Thompson2009-08-04
| | | | | | | Add forgotten return calls for the successful cases. Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: fix ECC checkingDoug Thompson2009-08-03
| | | | | | | | | | On the good path of BIOS enabled ECC and no override, the value returned is 1 by omission and thus is deemed failing by the probe-function. Allow proper module initialization by clearing the retval explicitly. Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* edac: x38 fix mchbar high register addrLu Zhihe2009-07-29
| | | | | | | | | | | Intel X38 MCHBAR is a 64bits register, base from 0x48, so its higher base is 0x4C. Signed-off-by: Lu Zhihe <tombowfly@gmail.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Cc: <stable@kernel.org> [2.6.30.x] Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* amd64_edac: read the right F2 maskoffset regWan Wei2009-07-27
| | | | | Signed-off-by: Wan Wei <onewayforever@gmail.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* edac: add DDR3 memory type for MPC85xx EDACYang Shi2009-06-30
| | | | | | | | | | Since some new MPC85xx SOCs support DDR3 memory now, so add DDR3 memory type for MPC85xx EDAC. Signed-off-by: Yang Shi <yang.shi@windriver.com> Cc: Doug Thompson <norsk5@yahoo.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* amd64_edac: misc small cleanupsBorislav Petkov2009-06-26
| | | | | | | | - cleanup debug calls - shorten function names - cleanup error exit paths Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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