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path: root/drivers/edac/amd64_edac.h
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* amd64_edac: Erratum #637 workaroundBorislav Petkov2011-04-26
| | | | | | | | | F15h CPUs may report a non-DRAM address when reporting an error address belonging to a CC6 state save area. Add a workaround to detect this condition and compute the actual DRAM address of the error as documented in the Revision Guide for AMD Family 15h Models 00h-0Fh Processors. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Factor in CC6 save areaBorislav Petkov2011-04-26
| | | | | | | | | | F15h and later use a portion of DRAM as a CC6 storage area. BIOS programs D18F1x[17C:140,7C:40] DRAM Base/Limit accordingly by subtracting the storage area from the DRAM limit setting. However, in order for edac to consider that part of DRAM too, we need to include it into the per-node range. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Fix DRAM base macrosBorislav Petkov2011-03-17
| | | | | | Return unsigned u8 values only. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Fix node id signednessBorislav Petkov2011-03-17
| | | | | | | | A node id can never be negative since we use it as an index into the DRAM ranges array. This also makes one of the BUG_ON conditions redundant. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Drop redundant declarationsBorislav Petkov2011-03-17
| | | | | | Those were moved to the mce_amd.h header. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Enable driver on F15hBorislav Petkov2011-03-17
| | | | | | | | | Add the PCI device ids required for driver registration. Remove pvt->ctl_name and use the family descriptor directly, instead. Then, bump driver version and fixup its format. Finally, enable DRAM ECC decoding on F15h. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Adjust ECC symbol size to F15hBorislav Petkov2011-03-17
| | | | | | | F15h has the same ECC symbol size options as F10h revD and later so adjust checks to that. Simplify code a bit. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Simplify scrubrate settingBorislav Petkov2011-03-17
| | | | | | Drop per-instance variable and compute min scrubrate dynamically. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Improve DRAM address mappingBorislav Petkov2011-03-17
| | | | | | | | Drop static tables which map the bits in F2x80 to a chip select size in favor of functions doing the mapping with some bit fiddling. Also, add F15 support. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Sanitize ->read_dram_ctl_registerBorislav Petkov2011-03-17
| | | | | | | This function is relevant for F10h and higher, and it has only one callsite so drop its function pointer from the low_ops struct. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Revamp online spare handlingBorislav Petkov2011-03-17
| | | | | | | Replace per-DCT macros with smarter ones, drop hack and look for the spare rank on all chip selects on a channel. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Add support for interleaved region swappingBorislav Petkov2011-03-17
| | | | | | | | | On revC3 and revE Fam10h machines and later, non-interleaved graphics framebuffer memory under the 16G mark can be swapped with a region located at the bottom of memory so that the GPU can use the interleaved region and thus two channels. Add support for that. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Unify get_error_addressBorislav Petkov2011-03-17
| | | | | | | | | The address bits from MC4_STATUS differ only between K8 and the rest so no need for a per-family method. No functional change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Simplify decoding pathBorislav Petkov2011-03-17
| | | | | | | | | Use the struct mce directly instead of copying from it into a custom struct err_regs. No functionality change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup old defines cruftBorislav Petkov2011-03-17
| | | | | | Remove unused defines, drop family names from define names. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup NBCFG handlingBorislav Petkov2011-03-17
| | | | | | | | | The fact whether we are chipkill capable or not does not have any bearing when computing the channel index on a ganged DCT configuration so remove that. Also, simplify debug statements. Finally, remove old error injection leftovers, while at it. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup NBCTL codeBorislav Petkov2011-03-17
| | | | | | | | | Remove family names from macro names, drop single bit defines and comment their meaning instead. No functional change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup DCT Select Low/High codeBorislav Petkov2011-03-17
| | | | | | | | | Shorten macro names, remove family name from macros, fix macro arguments, shorten debug strings. No functionality change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup Dram Configuration registers handlingBorislav Petkov2011-03-17
| | | | | | | | | | | | | * Restrict DCT ganged mode check since only Fam10h supports it * Adjust DRAM type detection for BD since it only supports DDR3 * Remove second and thus unneeded DCLR read in k8_early_channel_count() - we do that in read_mc_regs() * Cleanup comments and remove family names from register macros * Remove unused defines There should be no functional change resulting from this patch. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Sanitize f10_get_base_addr_offsetBorislav Petkov2011-03-17
| | | | | | | | | | | | This function maps the system address to the normalized DCT address. Document what the code does for more clarity and wrap insane bitmasks in a more understandable macro which generates them. Also, reduce number of arguments passed to the function. Finally, rename this function to what it actually does. No functional change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup chipselect handlingBorislav Petkov2011-03-17
| | | | | | | | | | | | Add a struct representing the DRAM chip select base/limit register pairs. Concentrate all CS handling in a single function. Also, add CS looping macros for cleaner, more readable code. While at it, adjust code to F15h. Finally, do smaller macro names cleanups (remove family names from register macros) and debug messages clarification. No functional change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup DHAR handlingBorislav Petkov2011-03-17
| | | | | | Adjust to F15h, simplify code, fixup macros. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Remove DRAM base/limit subfields cachingBorislav Petkov2011-03-17
| | | | | | | | | | | | | | | | | Add a struct representing the DRAM base/limit range pairs and remove all cached subfields. Replace them with accessor functions, which actually saves us some space: text data bss dec hex filename 14712 1577 336 16625 40f1 drivers/edac/amd64_edac_mod.o.after 14831 1609 336 16776 4188 drivers/edac/amd64_edac_mod.o.before Also, it simplifies the code a lot allowing to merge the K8 and F10h routines. No functional change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Add support for F15h DCT PCI config accessesBorislav Petkov2011-03-17
| | | | | | | | | | | | F15h "multiplexes" between the configuration space of the two DRAM controllers by toggling D18F1x10C[DctCfgSel] while F10h has a different set of registers for DCT0, and DCT1 in extended PCI config space. Add DCT configuration space accessors per family thus wrapping all the different access prerequisites. Clean up code while at it, shorten names. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC: Fixup scrubrate manipulationBorislav Petkov2011-01-07
| | | | | | | | | Make the ->{get|set}_sdram_scrub_rate return the actual scrub rate bandwidth it succeeded setting and remove superfluous arg pointer used for that. A negative value returned still means that an error occurred while setting the scrubrate. Document this for future reference. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Carve out ECC-related hw settingsBorislav Petkov2011-01-07
| | | | | | | | | | | | | | | | This is in preparation for the init path reorganization where we want only to 1) test whether a particular node supports ECC 2) can it be enabled and only then do the necessary allocation/initialization. For that, we need to decouple the ECC settings of the node from the instance's descriptor. The should be no functional change introduced by this patch. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Remove PCI ECS enabling functionsBorislav Petkov2011-01-07
| | | | | | | PCI ECS is being enabled by default since 2.6.26 on AMD so this code is just superfluous now, remove it. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Allocate driver instances dynamicallyBorislav Petkov2011-01-07
| | | | | | | | | Remove static allocation in favor of dynamically allocating space for as many driver instances as northbridges present on the system. There should be no functional change resulting from this patch. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Rework printk macrosBorislav Petkov2011-01-07
| | | | | | | Add a macro per printk level, shorten up error messages. Add relevant information to KERN_INFO level. No functional change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Rename CPU PCI devicesBorislav Petkov2011-01-07
| | | | | | | Rename variables representing PCI devices to their BKDG names for faster search and shorter, clearer code. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Concentrate per-family init even moreBorislav Petkov2011-01-07
| | | | | | | | Move the remaining per-family init code into the proper place and simplify the rest of the initialization. Reorganize error handling in amd64_init_one_instance(). Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Simplify CPU family detectionBorislav Petkov2011-01-07
| | | | | | Concentrate CPU family detection in the per-family init function. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Add per-family init functionBorislav Petkov2011-01-07
| | | | | | | | Run a per-family init function which does all the settings based on the family this driver instance is running on. Move the scrubrate calculation in it and simplify code. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Remove F11h supportBorislav Petkov2011-01-07
| | | | | | F11h doesn't support DRAM ECC so whack it away. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC, MCE: Complete NB MCE decodersBorislav Petkov2010-10-21
| | | | | | | Add support for decoding F14h BU MCEs and improve decoding of the remaining families. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC, MCE: Rename filesBorislav Petkov2010-10-21
| | | | | | | Drop "edac_" string from the filenames since they're prefixed with edac/ in their pathname anyway. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC, MCE: Rework MCE injectionBorislav Petkov2010-10-21
| | | | | | | | | | | | Add sysfs injection facilities for testing of the MCE decoding code. Remove large parts of amd64_edac_dbg.c, as a result, which did only NB MCE injection anyway and the new injection code supports that functionality already. Add an injection module so that MCE decoding code in production kernels like those in RHEL and SLES can be tested. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Remove unneeded definesBorislav Petkov2010-08-03
| | | | | | | | All F2x110-related bit defines are used at only one place so replace them with simple BIT() macros. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Acked-by: Doug Thompson <dougthompson@xmission.com>
* amd64_edac: Sanitize syndrome extractionBorislav Petkov2010-08-03
| | | | | | | | Remove the two syndrome extraction macros and add a single function which does the same thing but with proper typechecking. While at it, make sure to cache ECC syndrome size and dump it in debug output. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Simplify ECC override handlingBorislav Petkov2010-03-01
| | | | | | | | | | No need for clearing ecc_enable_override and checking it in two places. Instead, simply check it during probing and act accordingly. Also, rename the flag bitfields according to the functionality they actually represent. What is more, make sure original BIOS ECC settings are restored when the module is unloaded. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: bump driver versionBorislav Petkov2009-12-08
| | | | | | This was long overdue ... Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: remove early hw support checkBorislav Petkov2009-12-07
| | | | | | | | The .probe_valid_hardware low_ops member checked whether the DCTs are in DDR3 mode and bailed out if so. Now that all the needed changes for DDR3 support is in place, remove it. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: enhance address to DRAM bank mappingBorislav Petkov2009-12-07
| | | | | | | | | | | | | | | Add cs mode to cs size mapping tables for DDR2 and DDR3 and F10 and all K8 flavors and remove klugdy table of pseudo values. Add a low_ops->dbam_to_cs member which is family-specific and replaces low_ops->dbam_map_to_pages since the pages calculation is a one liner now. Further cleanups, while at it: - shorten family name defines - align amd64_family_types struct members Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: cleanup DRAM cfg low debug outputBorislav Petkov2009-12-07
| | | | | | | | | | Carve out the register-specific debug statements into a separate function, clarify meanings of the single bitfields in the register, remove irrelevant output and macros. There should be no functionality change resulting from this patch. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: wrap-up pci config read error handlingBorislav Petkov2009-12-07
| | | | | | | | | | | | | Add a pci config read wrapper for signaling pci config space access errors instead of them being visible only on a debug build. This is important on amd64_edac since it uses all those pci config register values to access the DRAM/DIMM configuration of the nodes. In addition, the wrapper makes a _lot_ (look at the diffstat!) of error handling code superfluous and improves much of the overall code readability by removing error handling details out of the way. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: unify MCGCTL ECC switchingBorislav Petkov2009-12-07
| | | | | | | | | | Unify almost identical code into one function and remove NUMA-specific usage (specifically cpumask_of_node()) in favor of generic topology methods. Remove unused defines, while at it. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: beef up DRAM error injectionBorislav Petkov2009-10-07
| | | | | | | | | | | | | When injecting DRAM ECC errors (F3xBC_x8), EccVector[15:0] is a bitmask of which bits should be error injected when written to and holds the payload of 16-bit DRAM word when read, respectively. Add /sysfs members to show the DRAM ECC section/word/vector. Fail wrong injection values entered over /sysfs instead of truncating them. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: fix chip select handlingBorislav Petkov2009-10-07
| | | | | | | | | | | | Different processor families support a different number of chip selects. Handle this in a family-dependent way with the proper values assigned at init time (see amd64_set_dct_base_and_mask). Remove _DCSM_COUNT defines since they're used at one place and originate from public documentation. CC: Keith Mannthey <kmannth@us.ibm.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: fix driver instance lookup table allocationBorislav Petkov2009-10-07
| | | | | | | | | Allocate memory statically for 8-node machines max for simplicity instead of relying on MAX_NUMNODES which is 0 on !CONFIG_NUMA builds. Spotted by Jan Beulich. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* x86, mce: pass mce info to EDAC for decodingBorislav Petkov2009-09-14
| | | | | | | | | Move NB decoder along with required defines to EDAC MCE core. Add registration routines for further decoding of the MCE info in the AMD64 EDAC module. CC: Andi Kleen <andi@firstfloor.org> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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