aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/dma/ipu
Commit message (Collapse)AuthorAge
* dma: fix ipu_idmac.c to not discard the last queued bufferGuennadi Liakhovetski2009-05-12
| | | | | | | | | | This also fixes the case of a single queued buffer, for example, when taking a single frame snapshot with the mx3_camera driver. Reported-by: Agustin Ferrin Pozuelo <gatoguan-os@yahoo.com> Tested-by: Agustin Ferrin Pozuelo <gatoguan-os@yahoo.com> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* ipu_idmac: Use disable_irq_nosync() from within irq handlers.Ben Nizette2009-05-05
| | | | | | | | | | | | | | | disable_irq() should wait for all running handlers to complete before returning. As such, if it's used to disable an interrupt from that interrupt's handler it will deadlock. This replaces the dangerous instances with the _nosync() variant which doesn't have this problem. Note the 2 handlers in question are only used #ifdef DEBUG so I imagine these code paths don't get hit often. Signed-off-by: Ben Nizette <bn@niasdigital.com> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* Merge branch 'next' of ↵Linus Torvalds2009-04-03
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: dma: Add SoF and EoF debugging to ipu_idmac.c, minor cleanup dw_dmac: add cyclic API to DW DMA driver dmaengine: Add privatecnt to revert DMA_PRIVATE property dmatest: add dma interrupts and callbacks dmatest: add xor test dmaengine: allow dma support for async_tx to be toggled async_tx: provide __async_inline for HAS_DMA=n archs dmaengine: kill some unused headers dmaengine: initialize tx_list in dma_async_tx_descriptor_init dma: i.MX31 IPU DMA robustness improvements dma: improve section assignment in i.MX31 IPU DMA driver dma: ipu_idmac driver cosmetic clean-up dmaengine: fail device registration if channel registration fails
| * dma: Add SoF and EoF debugging to ipu_idmac.c, minor cleanupGuennadi Liakhovetski2009-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | Add Start-of-Frame and End-of-Frame debugging to ipu_idmac.c, in the future it might also be needed for the actual video processing in mx3-camera, at which point, the ISRs will have to be transferred to mx3_camera.c, for which ipu_irq_map() and ipu_irq_unmap() functions will have to be exported. Also simplify a couple of pointer-dereferences. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dmaengine: initialize tx_list in dma_async_tx_descriptor_initDan Williams2009-03-25
| | | | | | | | | | | | | | | | Centralize this common initialization (and one case where ipu_idmac is duplicating ->chan initialization). Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dma: i.MX31 IPU DMA robustness improvementsGuennadi Liakhovetski2009-03-25
| | | | | | | | | | | | | | | | | | Add DMA error handling to the ISR, move common code fragments to functions, fix scatter-gather element queuing in the ISR, survive channel freeing and re-allocation in a quick succession. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dma: improve section assignment in i.MX31 IPU DMA driverGuennadi Liakhovetski2009-03-25
| | | | | | | | | | | | | | | | The i.MX31 IPU DMA driver is a platform driver, but doesn't need hotplug, so we can use __init and __exit function attributes. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dma: ipu_idmac driver cosmetic clean-upGuennadi Liakhovetski2009-03-25
| | | | | | | | | | | | | | Remove superfluous semicolons, update comments. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | MX31 clkdev supportSascha Hauer2009-03-13
|/ | | | | | | This patch adds clkdev support for i.MX31. This is done in a similar way done previously for i.MX27 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ipu_idmac: fix spinlock typeLuotao Fu2009-03-04
| | | | | | | | | | fix a probably accidently dropped reference operator while calling spin_unlock_restore to an ipu lock. Signed-off-by: Luotao Fu <l.fu@pengutronix.de> Cc: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* i.MX31: Image Processing Unit DMA and IRQ driversGuennadi Liakhovetski2009-01-19
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control Module (CM), Display Interface (DI), Synchronous Display Controller (SDC), Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC). CM contains, among other blocks, an Interrupt Generator (IG) and a Clock and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are supported over dmaengine and irq-chip APIs respectively. IDMAC is a specialised DMA controller, its DMA channels cannot be used for general-purpose operations, even though it might be possible to configure a memory-to-memory channel for memcpy operation. This driver will not work with generic dmaengine clients, clients, wishing to use it must use respective wrapper structures, they also must specify which channels they require, as channels are hard-wired to specific IPU functions. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>