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path: root/drivers/dma/dw_dmac.c
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* Viresh has movedViresh Kumar2012-06-20
| | | | | | | | | | | viresh.kumar@st.com email-id doesn't exist anymore as I have left the company. Replace ST's id with viresh.linux@gmail.com. It also updates .mailmap file to fix address for 'git shortlog' Signed-off-by: Viresh Kumar <viresh.linux@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* dmaengine: Use sg_dma_address instead of sg_physLars-Peter Clausen2012-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | dmaengine drivers should always use sg_dma_address instead of sg_phys to get the addresses for the transfer from a sg element. To quote Russel King: sg_phys(sg) of course has nothing to do with DMA addresses. It's the physical address _to the CPU_ of the memory associated with the scatterlist entry. That may, or may not have the same value for the DMA engine, particularly if IOMMUs are involved. And if these drivers are used on ARM, they must be fixed, sooner rather than later. There's patches in the works which will mean we will end up with IOMMU support in the DMA mapping later, which means everything I've said above will become reality. The patch has been generated using the following coccinelle patch: <smpl> @@ struct scatterlist *sg; @@ -sg_phys(sg) +sg_dma_address(sg) </smpl> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: dw_dma: add Device Tree probing capabilityViresh Kumar2012-05-11
| | | | | | | | | SPEAr platforms now support DT and so must convert all drivers to support DT. This patch adds DT probing support for Synopsys DMA controller and updates its documentation too. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: dw_dmac: Add clk_{un}prepare() supportViresh Kumar2012-05-11
| | | | | | | | | clk_{un}prepare is mandatory for platforms using common clock framework. Since this driver is used by SPEAr platform, which supports common clock framework, add clk_{un}prepare() support for it. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: add context parameter to prep_slave_sg and prep_dma_cyclicAlexandre Bounine2012-03-21
| | | | | | | | | | | | Add context parameter to device_prep_slave_sg() and device_prep_dma_cyclic() interfaces to allow passing client/target specific information associated with the data transfer. Modify all affected DMA engine drivers. Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: consolidate initialization of cookiesRussell King - ARM Linux2012-03-13
| | | | | | | | | | | | Provide a common function to initialize a channels cookie values. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: consolidate tx_status functionsRussell King - ARM Linux2012-03-13
| | | | | | | | | | | | | | | | Now that we have the completed cookie in the dma_chan structure, we can consolidate the tx_status functions by providing a function to set the txstate structure and returning the DMA status. We also provide a separate helper to set the residue for cookies which are still in progress. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: provide a common function for completing a dma descriptorRussell King - ARM Linux2012-03-13
| | | | | | | | | | | | | Provide a common function to do the cookie mechanics for completing a DMA descriptor. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: consolidate assignment of DMA cookiesRussell King - ARM Linux2012-03-13
| | | | | | | | | | | | | | Everyone deals with assigning DMA cookies in the same way (it's part of the API so they should be), so lets consolidate the common code into a helper function to avoid this duplication. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: add private header fileRussell King - ARM Linux2012-03-13
| | | | | | | | | | | | | | | | Add a local private header file to contain definitions and declarations which should only be used by DMA engine drivers. We also fix linux/dmaengine.h to use LINUX_DMAENGINE_H to guard against multiple inclusion. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: move last completed cookie into generic dma_chan structureRussell King - ARM Linux2012-03-13
| | | | | | | | | | | | | | | Every DMA engine implementation declares a last completed dma cookie in their private dma channel structures. This is pointless, and forces driver specific code. Move this out into the common dma_chan structure. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine/dw_dmac: Add support for DMA_SLAVE_CONFIGViresh Kumar2012-02-22
| | | | | | | | | | | This patch adds support for DMA_SLAVE_CONFIG in dwc DMAC controller. Fields in struct dw_dma_slave for passing similar data are preserved in this patch untill all existing users are fixed. That will be handled later in this patchset. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine/dw_dmac: Add 64 bit access width support for slave xfers on mem sideViresh Kumar2012-02-22
| | | | | | | | 64 bit transfers are possible on both sides in slave transfers (memory as well as peripherals). This patch adds support for it memory side 64 bit transfers. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine/dw_dmac: Don't handle block interruptsViresh Kumar2012-02-22
| | | | | | | | | | | Block interrupts give interrupt on completion of every LLI, which is actually too much interrupts. This is just not required for current functioning of dw_dmac. So, just don't handle them at all. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine/dw_dmac: Use dev_get_platdata() instead of accessing dev directlyViresh Kumar2012-02-22
| | | | | | | | Use already defined function dev_get_platdata() instead of accessing pdev->dev.data. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine/dw_dmac: Don't use magic number for total number of channelsViresh Kumar2012-02-22
| | | | | | | | Total number of channels is passed in pdata->nr_channels variable, thus we must not use magic number '7' for total number of channels. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine/dw_dmac: Hibernation support in dw_dmacRajeev KUMAR2012-02-22
| | | | | | | | | | The suspend and resume implementation is through dev_pm_ops in dmac. So in order to support hibernation, freeze, thaw, restore and poweroff features are required. Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Acked-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine/dw_dmac: Reconfigure interrupt and chan_cfg register on resumeViresh Kumar2011-11-27
| | | | | | | | | | | | | | | | | In S2R all DMA registers are reset by hardware and thus they are required to be reprogrammed. The channels which aren't reprogrammed are channel configuration and interrupt enable registers, which are currently programmed at chan_alloc time. This patch creates another routine to initialize a channel. It will try to initialize channel on every dwc_dostart() call. If channel is already initialised then it simply returns, otherwise it configures registers. This routine will also initialize registers on wakeup from S2R, as we mark channels as uninitialized on suspend. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: move drivers to dma_transfer_directionVinod Koul2011-10-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | fixup usage of dma direction by introducing dma_transfer_direction, this patch moves dma/drivers/* to use new enum Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Mika Westerberg <mika.westerberg@iki.fi> Cc: H Hartley Sweeten <hartleys@visionengravers.com> Cc: Li Yang <leoli@freescale.com> Cc: Zhang Wei <zw@zh-kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Shawn Guo <shawn.guo@freescale.com> Cc: Yong Wang <yong.y.wang@intel.com> Cc: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com> Cc: Boojin Kim <boojin.kim@samsung.com> Cc: Barry Song <Baohua.Song@csr.com> Acked-by: Mika Westerberg <mika.westerberg@iki.fi> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: delete redundant chan_id and chancnt initialization in dma driversBarry Song2011-09-20
| | | | | | | | | | | | | | | | | dma_async_device_register will re-init chan_id and chancnt, so whatever chan_id and chancnt are set in drivers, they will be re-written by dma_async_device_register. Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Piotr Ziecik <kosmo@semihalf.com> Cc: Yong Wang <yong.y.wang@intel.com> Cc: Jaswinder Singh <jassi.brar@samsung.com> Cc: Pelagicore AB <info@pelagicore.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge branch 'next' of ↵Linus Torvalds2011-05-28
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (33 commits) x86: poll waiting for I/OAT DMA channel status maintainers: add dma engine tree details dmaengine: add TODO items for future work on dma drivers dmaengine: Add API documentation for slave dma usage dmaengine/dw_dmac: Update maintainer-ship dmaengine: move link order dmaengine/dw_dmac: implement pause and resume in dwc_control dmaengine/dw_dmac: Replace spin_lock* with irqsave variants and enable submission from callback dmaengine/dw_dmac: Divide one sg to many desc, if sg len is greater than DWC_MAX_COUNT dmaengine/dw_dmac: set residue as total len in dwc_tx_status if status is !DMA_SUCCESS dmaengine/dw_dmac: don't call callback routine in case dmaengine_terminate_all() is called dmaengine: at_hdmac: pause: no need to wait for FIFO empty pch_dma: modify pci device table definition pch_dma: Support new device ML7223 IOH pch_dma: Support I2S for ML7213 IOH pch_dma: Fix DMA setting issue pch_dma: modify for checkpatch pch_dma: fix dma direction issue for ML7213 IOH video-in dmaengine: at_hdmac: use descriptor chaining help function dmaengine: at_hdmac: implement pause and resume in atc_control ... Fix up trivial conflict in drivers/dma/dw_dmac.c
| * dmaengine/dw_dmac: Update maintainer-shipViresh Kumar2011-05-25
| | | | | | | | | | | | | | | | | | | | Nobody is currently maintaining dw_dmac. We are using dw_dmac for SPEAr13xx and are currently maintaining it. After discussing with Vinod, sending this patch to update maintainer-ship of dw_dmac. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Havard Skinnemoen <hskinnemoen@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine/dw_dmac: implement pause and resume in dwc_controlLinus Walleij2011-05-13
| | | | | | | | | | | | | | | | | | | | Some peripherals like amba-pl011 needs pause to be implemented in DMA controller drivers. This also returns correct status from dwc_tx_status() in case chan is paused. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine/dw_dmac: Replace spin_lock* with irqsave variants and enable ↵Viresh Kumar2011-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | submission from callback dmaengine routines can be called from interrupt context and with interrupts disabled. Whereas spin_unlock_bh can't be called from such contexts. So this patch converts all spin_*_bh routines to irqsave variants. Also, spin_lock() used in tasklet is converted to irqsave variants, as tasklet can be interrupted, and dma requests from such interruptions may also call spin_lock. Now, submission from callbacks are permitted as per dmaengine framework. So we shouldn't hold any locks while calling callbacks. As locks were taken by parent routines, so releasing them before calling callbacks doesn't look clean enough. So, locks are taken inside all routine now, whereever they are required. And dwc_descriptor_complete is always called without taking locks. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine/dw_dmac: Divide one sg to many desc, if sg len is greater than ↵Viresh Kumar2011-05-13
| | | | | | | | | | | | | | | | | | | | | | DWC_MAX_COUNT If len passed in sg for slave_sg transfers is greater than DWC_MAX_COUNT, then driver programmes controller incorrectly. This patch adds code to handle this situation by allocation more than one desc for same sg. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine/dw_dmac: set residue as total len in dwc_tx_status if status is ↵Viresh Kumar2011-05-13
| | | | | | | | | | | | | | | | | | | | !DMA_SUCCESS If transfer status is !=DMA_SUCCESS, return total transfer len as residue, instead of zero. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine/dw_dmac: don't call callback routine in case ↵Viresh Kumar2011-05-13
| | | | | | | | | | | | | | | | | | | | | | dmaengine_terminate_all() is called If dmaengine_terminate_all() is called for dma channel, then it doesn't make much sense to call registered callback routine. While in case of success or failure it must be called. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine/dw_dmac fix: dwc_scan_descriptors must compare first desc address ↵Viresh Kumar2011-03-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | also with llp dwc_scan_descriptors scans all descriptors from active_list in case transfer is not completed. It compares first_desc->lli.llp, and then all childrens of its tx_list. But it doesn't compare its own address, i.e. first_desc->txd.phys, as this is what we have initially programmed into the controller register. So this causes dma to stop and finish a transfer, which was never started. And thus fail. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | Haavard Skinnemoen has left AtmelJean Delvare2011-05-18
|/ | | | | | | | Haavard's e-mail address at Atmel is no longer valid. Signed-off-by: Jean Delvare <khali@linux-fr.org> Acked-by: Havard Skinnemoen <hskinnemoen@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* dw_dmac: Setting Default Burst length for transfers as 16.Viresh Kumar2011-03-06
| | | | | | | | This patch sets default Burst length for all transfer to 16. This will enhance performance when user doesn't have any chan->private data. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dw_dmac: Allow src/dst msize & flow controller to be configured at runtimeViresh KUMAR2011-03-06
| | | | | | | | | | | | | Msize or Burst Size is peripheral dependent in case of prep_slave_sg and cyclic_prep transfers, and in case of memcpy transfers it is platform dependent. So msize configuration must come from platform data. Also some peripherals (ex: JPEG), need to be flow controller for dma transfers, so this information in case of slave_sg & cyclic_prep transfers must come from platform data. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dw_dmac: Pass Channel Priority from platform_dataViresh Kumar2011-03-06
| | | | | | | | | | In Synopsys designware, channel priority is programmable. This patch adds support for passing channel priority through platform data. By default Ascending channel priority will be followed, i.e. channel 0 will get highest priority and channel 7 will get lowest. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dw_dmac: Pass Channel Allocation Order from platform_dataViresh Kumar2011-03-06
| | | | | | | | | | In SPEAr Platform channels 4-7 have more Fifo depth. So we must get better channel first. This patch introduces concept of channel allocation order in dw_dmac. If user doesn't pass anything or 0, than normal (ascending) channel allocation will follow, else channels will be allocated in descending order. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dw_dmac: Mark all tx_descriptors with DMA_CRTL_ACK after xfer finishViresh Kumar2011-03-06
| | | | | | | | | | dwc_desc_get checks all descriptors for DMA_CTRL_ACK before allocating them for transfers. And descriptors are not marked with DMA_CRTL_ACK after transfer finishes. Thus descriptor once used is not usable again. This patch marks descriptors with DMA_CRTL_ACK after dma xfer finishes Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dw_dmac: Change value of DWC_MAX_COUNT to 4095.Viresh Kumar2011-03-06
| | | | | | | | Every descriptor can transfer a maximum count of 4095 (12 bits, in control reg), So we must have DWC_MAX_COUNT as 4095 instead of 2048. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dw_dmac: Adding support for 64 bit access width for memcpy xfersViresh Kumar2011-03-06
| | | | | Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dw_dmac: Calling dwc_scan_descriptors from dwc_tx_status() after taking lockViresh Kumar2011-03-06
| | | | | | | | | | Lock must be taken before calling dwc_scan_descriptors, as this may access/modify shared data and queues. dwc_tx_status wasn't taking lock before calling this routine. This patch add code that takes lock before calling dwc_scan_descriptors. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dw_dmac: Move single descriptor from dwc->queue to dwc->active_list in ↵Viresh Kumar2011-03-06
| | | | | | | | | | | dwc_complete_all dwc_complete_all and other routines was removing all descriptors from dwc->queue and pushing them to dwc->active_list. Only one was required to be removed. Also we are calling dwc_dostart, once list is fixed. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dw_dmac: Replace module_init() with subsys_initcall()Viresh Kumar2011-03-06
| | | | | | | | | | In some cases users of dw_dmac are initialized before dw_dmac, and if they try to use dw_dmac, they simply fail. So its better we register init() routine of driver using subsys_initcall() instead of module_init(), so that dma driver is available at the earliest possible. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine/dw_dmac: provide a mechanism to indicate private devicesJamie Iles2011-01-30
| | | | | | | | | | | Some platforms (e.g. Picochip PC3XX) have multiple DMA controllers where some may be used for slave transfers and others for general purpose memcpy type transfers. Add a .is_private boolean to the platform data structure so that controllers can be marked as private so that the DMA_PRIVATE capability will be set for that controller. Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* dmaengine/dw_dmac: allow src/dst masters to be configured at runtimeJamie Iles2011-01-30
| | | | | | | | | | | | | | Some platforms have flexible mastering capabilities and this needs to be selected at runtime. If the platform has specified private data in the form of the dw_dma_slave then fetch the source and destination masters from here. If this isn't present, default to the previous of 0 and 1. v2: cleanup whitespace Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* dmaengine/dw_dmac: don't scan descriptors if no xfers in progressJamie Iles2011-01-30
| | | | | | | | | | | | | | Some hardware (picoChip picoXCell in particular) sometimes has the block transfer complete bit being set for a channel after the whole transfer has completed. If we don't have any transfers in the active list then don't bother to scan the descriptors. This often happens in normal operation and doesn't require the channel to be reset. v2: cleanup whitespace Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* DMAENGINE: extend the control command to include an argLinus Walleij2010-05-17
| | | | | | | | | | | This adds an argument to the DMAengine control function, so that we can later provide control commands that need some external data passed in through an argument akin to the ioctl() operation prototype. [dan.j.williams@intel.com: fix up some missed conversions] Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* dmaengine: provide helper for setting txstateDan Williams2010-03-26
| | | | | | Simple conditional struct filler to cut out some duplicated code. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* DMAENGINE: generic channel status v2Linus Walleij2010-03-26
| | | | | | | | | | | | | | | | | | | | | | | | Convert the device_is_tx_complete() operation on the DMA engine to a generic device_tx_status()operation which can return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE, DMA_TX_PAUSED. [dan.j.williams@intel.com: update for timberdale] Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Maciej Sosnowski <maciej.sosnowski@intel.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: Li Yang <leoli@freescale.com> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Magnus Damm <damm@opensource.se> Cc: Liam Girdwood <lrg@slimlogic.co.uk> Cc: Joe Perches <joe@perches.com> Cc: Roland Dreier <rdreier@cisco.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* DMAENGINE: generic slave control v2Linus Walleij2010-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | Convert the device_terminate_all() operation on the DMA engine to a generic device_control() operation which can now optionally support also pausing and resuming DMA on a certain channel. Implemented for the COH 901 318 DMAC as an example. [dan.j.williams@intel.com: update for timberdale] Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Maciej Sosnowski <maciej.sosnowski@intel.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: Li Yang <leoli@freescale.com> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Magnus Damm <damm@opensource.se> Cc: Liam Girdwood <lrg@slimlogic.co.uk> Cc: Joe Perches <joe@perches.com> Cc: Roland Dreier <rdreier@cisco.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* Merge branch 'fixes' of ↵Linus Torvalds2009-12-30
|\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: drivers/dma: Correct use after free drivers/dma: drop unnecesary memset ioat2,3: put channel hardware in known state at init async_tx: expand async raid6 test to cover ioatdma corner case ioat3: fix p-disabled q-continuation sh: fix DMA driver's descriptor chaining and cookie assignment dma: at_hdmac: correct incompatible type for argument 1 of 'spin_lock_bh'
| * drivers/dma: drop unnecesary memsetJulia Lawall2009-12-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | memset of 0 is not needed after kzalloc The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression x; statement S; @@ x = kzalloc(...); if (x == NULL) S ... when != x -memset(x,0,...);// </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | const: constify remaining dev_pm_opsAlexey Dobriyan2009-12-15
|/ | | | | | Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'next' of ↵NeilBrown2009-09-23
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx into for-linus
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