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| * | crypto: ux500 - make interrupt mode plausibleArnd Bergmann2014-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The interrupt handler in the ux500 crypto driver has an obviously incorrect way to access the data buffer, which for a while has caused this build warning: ../ux500/cryp/cryp_core.c: In function 'cryp_interrupt_handler': ../ux500/cryp/cryp_core.c:234:5: warning: passing argument 1 of '__fswab32' makes integer from pointer without a cast [enabled by default] writel_relaxed(ctx->indata, ^ In file included from ../include/linux/swab.h:4:0, from ../include/uapi/linux/byteorder/big_endian.h:12, from ../include/linux/byteorder/big_endian.h:4, from ../arch/arm/include/uapi/asm/byteorder.h:19, from ../include/asm-generic/bitops/le.h:5, from ../arch/arm/include/asm/bitops.h:340, from ../include/linux/bitops.h:33, from ../include/linux/kernel.h:10, from ../include/linux/clk.h:16, from ../drivers/crypto/ux500/cryp/cryp_core.c:12: ../include/uapi/linux/swab.h:57:119: note: expected '__u32' but argument is of type 'const u8 *' static inline __attribute_const__ __u32 __fswab32(__u32 val) There are at least two, possibly three problems here: a) when writing into the FIFO, we copy the pointer rather than the actual data we want to give to the hardware b) the data pointer is an array of 8-bit values, while the FIFO is 32-bit wide, so both the read and write access fail to do a proper type conversion c) This seems incorrect for big-endian kernels, on which we need to byte-swap any register access, but not normally FIFO accesses, at least the DMA case doesn't do it either. This converts the bogus loop to use the same readsl/writesl pair that we use for the two other modes (DMA and polling). This is more efficient and consistent, and probably correct for endianess. The bug has existed since the driver was first merged, and was probably never detected because nobody tried to use interrupt mode. It might make sense to backport this fix to stable kernels, depending on how the crypto maintainers feel about that. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: linux-crypto@vger.kernel.org Cc: Fabio Baltieri <fabio.baltieri@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: stable@vger.kernel.org Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qce - Build Qualcomm crypto driverStanimir Varbanov2014-07-03
| | | | | | | | | | | | | | | | | | | | | | | | Modify crypto Kconfig and Makefile in order to build the qce driver and adds qce Makefile as well. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qce - Qualcomm crypto engine driverStanimir Varbanov2014-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver is separated by functional parts. The core part implements a platform driver probe and remove callbaks. The probe enables clocks, checks crypto version, initialize and request dma channels, create done tasklet and init crypto queue and finally register the algorithms into crypto core subsystem. - DMA and SG helper functions implement dmaengine and sg-list helper functions used by other parts of the crypto driver. - ablkcipher algorithms implementation of AES, DES and 3DES crypto API callbacks, the crypto register alg function, the async request handler and its dma done callback function. - SHA and HMAC transforms implementation and registration of ahash crypto type. It includes sha1, sha256, hmac(sha1) and hmac(sha256). - infrastructure to setup the crypto hw contains functions used to setup/prepare hardware registers for all algorithms supported by the crypto block. It also exports few helper functions needed by algorithms: - to check hardware status - to start crypto hardware - to translate data stream to big endian form Adds register addresses and bit/masks used by the driver as well. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Fix error path crash when no firmware is presentTadeusz Struk2014-06-26
| | | | | | | | | | | | | | | | | | | | | | | | Firmware loader crashes when no firmware file is present. Reviewed-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Fixed new checkpatch warningsTadeusz Struk2014-06-26
| | | | | | | | | | | | | | | | | | | | | | | | After updates to checkpatch new warnings pops up this patch fixes them. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Acked-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Updated Firmware Info MetadataTadeusz Struk2014-06-26
| | | | | | | | | | | | | | | | | | | | | | | | Updated Firmware Info Metadata Reviewed-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Fix random config build warningsTadeusz Struk2014-06-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix random config build warnings: Implicit-function-declaration ‘__raw_writel’ Cast to pointer from integer of different size [-Wint-to-pointer-cast] Reviewed-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: caam - Correct the dma mapping for sg tableRuchika Gupta2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At few places in caamhash and caamalg, after allocating a dmable buffer for sg table , the buffer was being modified. As per definition of DMA_FROM_DEVICE ,afer allocation the memory should be treated as read-only by the driver. This patch shifts the allocation of dmable buffer for sg table after it is populated by the driver, making it read-only as per the DMA API's requirement. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: caam - Add definition of rd/wr_reg64 for little endian platformRuchika Gupta2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CAAM IP has certain 64 bit registers . 32 bit architectures cannot force atomic-64 operations. This patch adds definition of these atomic-64 operations for little endian platforms. The definitions which existed previously were for big endian platforms. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: caam - Configuration for platforms with virtualization enabled in CAAMRuchika Gupta2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For platforms with virtualization enabled 1. The job ring registers can be written to only is the job ring has been started i.e STARTR bit in JRSTART register is 1 2. For DECO's under direct software control, with virtualization enabled PL, BMT, ICID and SDID values need to be provided. These are provided by selecting a Job ring in start mode whose parameters would be used for the DECO access programming. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: caam - Correct definition of registers in memory mapRuchika Gupta2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some registers like SECVID, CHAVID, CHA Revision Number, CTPR were defined as 64 bit resgisters. The IP provides a DWT bit(Double word Transpose) to transpose the two words when a double word register is accessed. However setting this bit would also affect the operation of job descriptors as well as other registers which are truly double word in nature. So, for the IP to work correctly on big-endian as well as little-endian SoC's, change is required to access all 32 bit registers as 32 bit quantities. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Fix build problem with O=Herbert Xu2014-06-23
| | | | | | | | | | | | | | | | | | | | | | | | qat adds -I to the ccflags. Unfortunately it uses CURDIR which breaks when make is invoked with O=. This patch replaces CURDIR with $(src) which should work with/without O=. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: caam - remove duplicate FIFOST_CONT_MASK defineDan Carpenter2014-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FIFOST_CONT_MASK define is cut and pasted twice so we can delete the second instance. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Update to makefilesTadeusz Struk2014-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update to makefiles etc. Don't update the firmware/Makefile yet since there is no FW binary in the crypto repo yet. This will be added later. v3 - removed change to ./firmware/Makefile Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Intel(R) QAT DH895xcc acceleratorTadeusz Struk2014-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DH895xCC hardware specific code. It hooks to the common infrastructure and provides acceleration for crypto algorithms. Acked-by: John Griffin <john.griffin@intel.com> Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Intel(R) QAT accelengine part of fw loaderTadeusz Struk2014-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds acceleration engine handler part the firmware loader. Acked-by: Bo Cui <bo.cui@intel.com> Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com> Signed-off-by: Karen Xiang <karen.xiang@intel.com> Signed-off-by: Pingchaox Yang <pingchaox.yang@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Intel(R) QAT ucode part of fw loaderTadeusz Struk2014-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds microcode part of the firmware loader. v4 - splits FW loader part into two smaller patches. Acked-by: Bo Cui <bo.cui@intel.com> Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com> Signed-off-by: Karen Xiang <karen.xiang@intel.com> Signed-off-by: Pingchaox Yang <pingchaox.yang@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Intel(R) QAT crypto interfaceTadeusz Struk2014-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds qat crypto interface. Acked-by: John Griffin <john.griffin@intel.com> Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Intel(R) QAT FW interfaceTadeusz Struk2014-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds FW interface structure definitions. Acked-by: John Griffin <john.griffin@intel.com> Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Intel(R) QAT transport codeTadeusz Struk2014-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a code that implements communication channel between the driver and the firmware. Acked-by: John Griffin <john.griffin@intel.com> Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: qat - Intel(R) QAT driver frameworkTadeusz Struk2014-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a common infractructure that will be used by all Intel(R) QuickAssist Technology (QAT) devices. v2 - added ./drivers/crypto/qat/Kconfig and ./drivers/crypto/qat/Makefile v4 - splits common part into more, smaller patches Acked-by: John Griffin <john.griffin@intel.com> Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: ccp - Add platform device support for arm64Tom Lendacky2014-06-20
| | | | | | | | | | | | | | | | | | | | | Add support for the CCP on arm64 as a platform device. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: ccp - Modify PCI support in prep for arm64 supportTom Lendacky2014-06-20
| | | | | | | | | | | | | | | | | | | | | | | | Modify the PCI device support in prep for supporting the CCP as a platform device for arm64. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: drivers - Add 2 missing __exit_pJean Delvare2014-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | References to __exit functions must be wrapped with __exit_p. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: "David S. Miller" <davem@davemloft.net> Cc: Robert Jennings <rcj@linux.vnet.ibm.com> Cc: Marcelo Henrique Cerri <mhcerri@linux.vnet.ibm.com> Cc: Fionnuala Gunter <fin@linux.vnet.ibm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | crypto: caam - Introduce the use of the managed version of kzallocHimangi Saraogi2014-06-20
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves data allocated using kzalloc to managed data allocated using devm_kzalloc and cleans now unnecessary kfrees in probe and remove functions. Also, linux/device.h is added to make sure the devm_*() routine declarations are unambiguously available. Earlier, in the probe function ctrlpriv was leaked on the failure of ctrl = of_iomap(nprop, 0); as well as on the failure of ctrlpriv->jrpdev = kzalloc(...); . These two bugs have been fixed by the patch. The following Coccinelle semantic patch was used for making the change: identifier p, probefn, removefn; @@ struct platform_driver p = { .probe = probefn, .remove = removefn, }; @prb@ identifier platform.probefn, pdev; expression e, e1, e2; @@ probefn(struct platform_device *pdev, ...) { <+... - e = kzalloc(e1, e2) + e = devm_kzalloc(&pdev->dev, e1, e2) ... ?-kfree(e); ...+> } @rem depends on prb@ identifier platform.removefn; expression e; @@ removefn(...) { <... - kfree(e); ...> } Signed-off-by: Himangi Saraogi <himangi774@gmail.com> Acked-by: Julia Lawall <julia.lawall@lip6.fr> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* / crypto: caam - fix memleak in caam_jr moduleCristian Stoica2014-07-10
|/ | | | | | | | This patch fixes a memory leak that appears when caam_jr module is unloaded. Cc: <stable@vger.kernel.org> # 3.13+ Signed-off-by: Cristian Stoica <cristian.stoica@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto/nx: disable NX on little endian buildsAnton Blanchard2014-06-11
| | | | | | | The NX driver has endian issues so disable it for now. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6 ↵Linus Torvalds2014-06-07
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next Pull crypto updates from Herbert Xu: "Here is the crypto update for 3.16: - Added test vectors for SHA/AES-CCM/DES-CBC/3DES-CBC. - Fixed a number of error-path memory leaks in tcrypt. - Fixed error-path memory leak in caam. - Removed unnecessary global mutex from mxs-dcp. - Added ahash walk interface that can actually be asynchronous. - Cleaned up caam error reporting. - Allow crypto_user get operation to be used by non-root users. - Add support for SSS module on Exynos. - Misc fixes" * git://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6: (60 commits) crypto: testmgr - add aead cbc des, des3_ede tests crypto: testmgr - Fix DMA-API warning crypto: cesa - tfm->__crt_alg->cra_type directly crypto: sahara - tfm->__crt_alg->cra_name directly crypto: padlock - tfm->__crt_alg->cra_name directly crypto: n2 - tfm->__crt_alg->cra_name directly crypto: dcp - tfm->__crt_alg->cra_name directly crypto: cesa - tfm->__crt_alg->cra_name directly crypto: ccp - tfm->__crt_alg->cra_name directly crypto: geode - Don't use tfm->__crt_alg->cra_name directly crypto: geode - Weed out printk() from probe() crypto: geode - Consistently use AES_KEYSIZE_128 crypto: geode - Kill AES_IV_LENGTH crypto: geode - Kill AES_MIN_BLOCK_SIZE crypto: mxs-dcp - Remove global mutex crypto: hash - Add real ahash walk interface hwrng: n2-drv - Introduce the use of the managed version of kzalloc crypto: caam - reinitialize keys_fit_inline for decrypt and givencrypt crypto: s5p-sss - fix multiplatform build hwrng: timeriomem - remove unnecessary OOM messages ...
| * crypto: cesa - tfm->__crt_alg->cra_type directlyMarek Vasut2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | The checking for the type of algorithm implementation is pretty strange here. Use regular flags to check for the type instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: Kent Yoder <key@linux.vnet.ibm.com> Cc: Jamie Iles <jamie@jamieiles.com> Cc: Phil Sutter <phil.sutter@viprinet.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: sahara - tfm->__crt_alg->cra_name directlyMarek Vasut2014-05-22
| | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: padlock - tfm->__crt_alg->cra_name directlyMarek Vasut2014-05-22
| | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: n2 - tfm->__crt_alg->cra_name directlyMarek Vasut2014-05-22
| | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: dcp - tfm->__crt_alg->cra_name directlyMarek Vasut2014-05-22
| | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: cesa - tfm->__crt_alg->cra_name directlyMarek Vasut2014-05-22
| | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: ccp - tfm->__crt_alg->cra_name directlyMarek Vasut2014-05-22
| | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: geode - Don't use tfm->__crt_alg->cra_name directlyMarek Vasut2014-05-22
| | | | | | | | | | | | | | Use a standard accessor instead of directly digging into a structure. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: geode - Weed out printk() from probe()Marek Vasut2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> Cc: Eric Bénard <eric@eukrea.com> Cc: Jussi Kivilinna <jussi.kivilinna@mbnet.fi> Cc: Kent Yoder <key@linux.vnet.ibm.com> Cc: Michal Ludvig <michal@logix.cz> Cc: Varun Wadekar <vwadekar@nvidia.com> Cc: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Cc: linux-geode@lists.infradead.org Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: geode - Consistently use AES_KEYSIZE_128Marek Vasut2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consistently use AES_KEYSIZE_128 instead of arbitrary defined value. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> Cc: Eric Bénard <eric@eukrea.com> Cc: Jussi Kivilinna <jussi.kivilinna@mbnet.fi> Cc: Kent Yoder <key@linux.vnet.ibm.com> Cc: Michal Ludvig <michal@logix.cz> Cc: Varun Wadekar <vwadekar@nvidia.com> Cc: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Cc: linux-geode@lists.infradead.org Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: geode - Kill AES_IV_LENGTHMarek Vasut2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AES IV length is always 128bits, just use the define from aes.h Signed-off-by: Marek Vasut <marex@denx.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> Cc: Eric Bénard <eric@eukrea.com> Cc: Jussi Kivilinna <jussi.kivilinna@mbnet.fi> Cc: Kent Yoder <key@linux.vnet.ibm.com> Cc: Michal Ludvig <michal@logix.cz> Cc: Varun Wadekar <vwadekar@nvidia.com> Cc: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Cc: linux-geode@lists.infradead.org Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: geode - Kill AES_MIN_BLOCK_SIZEMarek Vasut2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is actually defined in include/crypto/aes.h , no need to have a a different symbol for the same thing twice. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> Cc: Eric Bénard <eric@eukrea.com> Cc: Jussi Kivilinna <jussi.kivilinna@mbnet.fi> Cc: Kent Yoder <key@linux.vnet.ibm.com> Cc: Michal Ludvig <michal@logix.cz> Cc: Varun Wadekar <vwadekar@nvidia.com> Cc: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Cc: linux-geode@lists.infradead.org Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: mxs-dcp - Remove global mutexFabio Estevam2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove mutex_lock from probe in order to avoid the following warning: [ 8.526613] Freeing unused kernel memory: 232K (c0683000 - c06bd000) starting pid 56, tty '': '/etc/rc.d/rcS' [ 9.110314] [ 9.111864] ===================================== [ 9.116603] [ BUG: init/1 still has locks held! ] [ 9.121488] 3.15.0-rc4-next-20140509-00001-g319564e #1154 Not tainted [ 9.128071] ------------------------------------- [ 9.132825] 1 lock held by init/1: [ 9.136252] #0: (global_mutex){+.+.+.}, at: [<c0387d68>] mxs_dcp_probe+0x14 [ 9.144196] [ 9.144196] stack backtrace: [ 9.148888] CPU: 0 PID: 1 Comm: init Not tainted 3.15.0-rc4-next-20140509-004 [ 9.157610] [<c000da40>] (unwind_backtrace) from [<c000bda4>] (show_stack+0x) [ 9.165595] [<c000bda4>] (show_stack) from [<c00153d4>] (do_fork+0x2c8/0x3cc) [ 9.172921] [<c00153d4>] (do_fork) from [<c0015550>] (sys_vfork+0x20/0x2c) [ 9.179973] [<c0015550>] (sys_vfork) from [<c0009580>] (ret_fast_syscall+0x0) Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: caam - reinitialize keys_fit_inline for decrypt and givencryptVakul Garg2014-05-13
| | | | | | | | | | | | | | | | | | | | | | Re-initialize keys_fit_inline to avoid using its stale encrypt() shared descriptor value prior to building descriptors for the decrypt() and givencrypt() cases. Signed-off-by: Vakul Garg <vakul@freescale.com> [reworded commit text, enhanced code readability] Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: s5p-sss - fix multiplatform buildArnd Bergmann2014-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we are preparing to enable multiplatform support on EXYNOS, we can no longer include mach/*.h or plat/*.h headers from device drivers. The s5p-sss driver was just enabled for EXYNOS when it used to be used only on s5pv210, and it includes two samsung platform specific header files for historic reasons. Fortunately, it no longer actually needs them, so we can remove the #includes and avoid the problem Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: <linux-samsung-soc@vger.kernel.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: s5p-sss - Look for the next request in the queueNaveen Krishna Chatradhi2014-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the driver enqueues a request only if the busy bit is false. And every request initiates a dequeue. If 2 requests arrive simultaneously, only one of them will be dequeued. To avoid this senario, we will enqueue the next request irrespective of the system condition (that is what queue is here for). Also schedule at a tasklet immediatly after the current request is done. The tasklet will dequeue the next request in the queue, giving continuous loop. tasklet will exit if there are no requests in the queue. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> CC: David S. Miller <davem@davemloft.net> CC: <linux-samsung-soc@vger.kernel.org> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: s5p-sss - Use clk_prepare/clk_unprepareNaveen Krishna Chatradhi2014-05-08
| | | | | | | | | | | | | | | | | | | | | | | | This patch set adds use of clk_prepare/clk_unprepare as required by generic clock framework. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> CC: David S. Miller <davem@davemloft.net> CC: <linux-samsung-soc@vger.kernel.org> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: s5p-sss - validate iv before memcpyNaveen Krishna Chatradhi2014-05-08
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds code to validate "iv" buffer before trying to memcpy the contents Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> CC: David S. Miller <davem@davemloft.net> CC: <linux-samsung-soc@vger.kernel.org> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: s5p-sss - Let Exynos SoCs select SSS driverNaveen Krishna Chatradhi2014-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies Kconfig such that ARCH_EXYNOS SoCs which includes (Exynos4210, Exynos5250 and Exynos5420) can also select Samsung SSS(Security SubSystem) driver. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> CC: David S. Miller <davem@davemloft.net> CC: <linux-samsung-soc@vger.kernel.org> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: s5p-sss - Add support for SSS module on ExynosNaveen Krishna Chatradhi2014-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new compatible and variant struct to support the SSS module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250) for which 1. AES register are at an offset of 0x200 and 2. hash interrupt is not available Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> CC: David S. Miller <davem@davemloft.net> CC: <linux-samsung-soc@vger.kernel.org> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: s5p-sss - Add device tree supportNaveen Krishna Chatradhi2014-05-08
| | | | | | | | | | | | | | | | | | | | This patch adds device tree support to the s5p-sss.c crypto driver. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> CC: David S. Miller <davem@davemloft.net> CC: <linux-samsung-soc@vger.kernel.org> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * crypto: s5p-sss - Use platform_get_irq() instead of _byname()Naveen Krishna Chatradhi2014-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the platform_get_irq() instead of the platform_get_irq_byname(). Making feeder control interrupt as resource "0" and hash interrupt as "1". reasons for this change. 1. Cannot find any Arch which is currently using this driver 2. Samsung Exynos4 and 5 SoCs only use the feeder control interrupt 3. Patches adding support for DT and H/W version are in pipeline Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> CC: David S. Miller <davem@davemloft.net> CC: <linux-samsung-soc@vger.kernel.org> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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