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* Merge tag 'samsung-clk-3' of ↵Olof Johansson2014-05-31
|\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Merge "Samsung 3rd clock updates for 3.16" from Kukjin Kim: - add clock for new exynos5410 SoC * tag 'samsung-clk-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: clk: exynos5410: register clocks using common clock framework Signed-off-by: Olof Johansson <olof@lixom.net>
| * clk: exynos5410: register clocks using common clock frameworkTarek Dakhran2014-05-30
| | | | | | | | | | | | | | | | | | | | The EXYNOS5410 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | Merge tag 'samsung-clk-2' of ↵Olof Johansson2014-05-29
|\| | | | | | | | | | | | | | | | | | | | | | | | | http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Merge "Samsung 2nd clock updates for 3.16" from Kukjin Kim: - Add missing sysmmu clocks for DISP and ISP blocks for exynos5250 * tag 'samsung-clk-2' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks Signed-off-by: Olof Johansson <olof@lixom.net>
| * clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocksCho KyongHo2014-05-25
| | | | | | | | | | | | | | | | | | | | This patch adds the missing sysmmu clocks for Display and ISP blocks. Signed-off-by: Cho KyongHo <pullip.cho@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | Merge tag 'samsung-clk' of ↵Olof Johansson2014-05-29
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Merge "Samsung clock updates for 3.16" from Kukjin Kim: In this time, it is having dependency with arch/arm/ for 3.16, I pulled them into samsung tree from Tomasz under agreement from Mike. - Pull for_3.16/exynos5260 from Tomasz Figa: "This pull request contains patches preparing Samsung Common Clock Framework helpers to support Exynos5260 by adding support for multiple clock providers and then adding clock driver for Exynos5260." - Pull for_3.16/clk_fixes_non_critical from Tomasz Figa: "This pull requests contains a number of non-critical fixes for Samsung clock framework and drivers, including: 1) a series of fixes for Exynos5420 to correct clock definitions and make the driver closer to the documentation, 2) several missing clocks and clock IDs added to Exynos4, Exynos5250 and Exynos5420 drivers, 3) fix for incorrect initialization of clock table with NULL, 4) compiler warning fix." - Pull for_3.16/clk_cleanup from Tomasz Figa: "This pull requests contains minor clean-up related to Samsung clock support, including: 1) move Kconfig entries of Samsung clock drivers to drivers/clk, 2) compile drivers/clk/samsung conditionally when COMMON_CLK_SAMSUNG is selected, 3) remove obsolete Kconfig lines after moving s3c24xx to CCF." - Pull for_3.16/exynos3250 from Tomasz Figa: "This small pull request contains a patch adding clock driver for Exynos3250, which depends on previous pull requests in this series." - add dt bindings for exynos3250 clock - add exynos5800 specific clocks in current exynos5420 clock Note that this branch is based on s3c24xx ccf branch * tag 'samsung-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (59 commits) clk: exynos5420: Add 5800 specific clocks dt-bindings: add documentation for Exynos3250 clock controller ARM: S3C24XX: fix merge conflict clk: samsung: exynos3250: Add clocks using common clock framework drivers: clk: use COMMON_CLK_SAMSUNG for Samsung clock support ARM: S3C24XX: move S3C24XX clock Kconfig options to Samsung clock Kconfig file ARM: select COMMON_CLK_SAMSUNG for ARCH_EXYNOS and ARCH_S3C64XX clk: samsung: add new Kconfig for Samsung common clock option ARM: S3C24XX: Remove omitted Kconfig selects and conditionals clk: samsung: exynos5420: add more registers to restore list clk: samsung: exynos5420: add misc clocks clk: samsung: exynos5420: update clocks for MAU Block clk: samsung: exynos5420: fix register offset for sclk_bpll clk: samsung: exynos5420: correct sysmmu-mfc parent clocks clk: samsung: exynos5420: update clocks for FSYS and FSYS2 blocks clk: samsung: exynos5420: update clocks for WCORE block clk: samsung: exynos5420: update clocks for PERIS and GEN blocks clk: samsung: exynos5420: update clocks for PERIC block clk: samsung: exynos5420: update clocks for DISP1 block clk: samsung: exynos5420: update clocks for G2D and G3D blocks ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * clk: exynos5420: Add 5800 specific clocksAlim Akhtar2014-05-19
| | | | | | | | | | | | | | | | | | | | | | | | Exynos5800 clock structure is mostly similar to 5420 with only a small delta changes. So the 5420 clock file is re-used for 5800 also. The common clocks for both are seggreagated and few clocks which are different for both are separately initialized. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: exynos3250: Add clocks using common clock frameworkTomasz Figa2014-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7 using common clock framework. The CMU (Clock Management Unit) of Exynos3250 control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses, and function clocks for individual IPs. The CMU of Exynos3250 includes following clock doamins: - CPU block for Cortex-A7 MPCore processor - LEFTBUS/RIGHTBUS block - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Karol Wrona <k.wrona@samsung.com> Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org>
| * drivers: clk: use COMMON_CLK_SAMSUNG for Samsung clock supportPankaj Dubey2014-05-14
| | | | | | | | | | | | | | | | | | | | This patch replaces PLAT_SAMSUNG with COMMON_CLK_SAMSUNG for Samsung common clock support. Any Samsung SoC want to use Samsung common clock infrastructure can simply select COMMON_CLK_SAMSUNG. CC: Mike Turquette <mturquette@linaro.org> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * ARM: S3C24XX: move S3C24XX clock Kconfig options to Samsung clock Kconfig filePankaj Dubey2014-05-14
| | | | | | | | | | | | | | | | | | | | | | | | This patch moves S3C24XX specific clock Kconfig options into "clk/samsung/Kconfig" and also removes COMMON_CLK selection from "mach-s3c24xx/Kconfig" as S3C24XX_COMMON_CLK is selecting it's dependency. CC: Ben Dooks <ben-linux@fluff.org> CC: Kukjin Kim <kgene.kim@samsung.com> CC: Russell King <linux@arm.linux.org.uk> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: add new Kconfig for Samsung common clock optionPankaj Dubey2014-05-14
| | | | | | | | | | | | | | | | | | This patch adds new Kconfig file for adding new COMMON_CLK_SAMSUNG option. Samsung platforms can select this for using common clock infrastructure. CC: Mike Turquette <mturquette@linaro.org> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: add more registers to restore listShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | | | This patch adds more register offsets to the list for preserving their values during S2R. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: add misc clocksShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | | | This patch adds some missing miscellaneous clocks specific to exynos5420. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: update clocks for MAU BlockShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | This patch adds the missing MAU block specific clocks. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: fix register offset for sclk_bpllShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | | | This patch fixes the wrong register offset for sclk_bpll clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: correct sysmmu-mfc parent clocksShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | This patch corrects the wrong parent-child relationship between sysmmu-mfc clocks. Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: update clocks for FSYS and FSYS2 blocksShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | | | This patch adds more clocks from FSYS and FSYS2 blocks and uses GATE_IP_* registers for gating IPs. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: update clocks for WCORE blockShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | This patch adds missing clocks for WCORE block. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: update clocks for PERIS and GEN blocksShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | | | | | This patch fixes some parent-child relationships according to the latest datasheet and adds more clocks related to PERIS and GEN blocks. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: update clocks for PERIC blockShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes, 1] renaming of the HSI2C clocks 2] renaming of spi clocks according to the datasheet 3] fixes for child-parent relationships 4] adding of more clocks related to PERIC block 5] use GATE_IP_* offsets instead of GATE_BUS_* Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: update clocks for DISP1 blockShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | | | This patch corrects some child-parent clock relationships, and updates the clocks according to the latest datasheet. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: update clocks for G2D and G3D blocksShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | | | This patch adds missing clocks of G2D block. It also removes the aclkg3d alias from G3D block clocks. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: fix parent clocks for mscl sysmmuShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | This patch fixes the parent clocks for mscl sysmmu. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: update clocks for GSCL and MSCL blocksShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | | | This patch adds the missing GSCL and MSCL block clocks and corrects some wrong parent-child relationships. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: add clocks for ISP blockShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | | | This patch adds minimum set of clocks to gate ISP block for power saving. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: Rename mux parent arraysShaik Ameer Basha2014-05-14
| | | | | | | | | | | | | | | | | | | | This patch renames the mux parent arrays as per the naming convension followed by the other exynos specific clock drivers. And it also renames "mout_cpu_kfc" clock to "mout_kfc". Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: Add clock IDs needed by GPUArun Kumar K2014-05-14
| | | | | | | | | | | | | | | | Adds IDs for the clocks needed by the ARM Mali GPU in exynos5420. Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos4: export sclk_hdmiphy clockTomasz Stanislawski2014-05-14
| | | | | | | | | | | | | | Export sclk_hdmiphy clock to be usable from DT. Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5250: Add clocks for G3DArun Kumar K2014-05-14
| | | | | | | | | | | | | | | | | | This patch adds the required clocks for ARM Mali IP in Exynos5250. Signed-off-by: Arun Kumar K <arun.kk@samsung.com> [t.figa: Changed clock ID to avoid conflict with CLK_SSS] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos4: Use single clock ID for CLK_MDMA gate clocksSylwester Nawrocki2014-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos4210 and Exynos4x12 SoCs have the PL330 MDMA IP block clock defined exactly in same way in documentation. Using different names for these clocks is a bit misleading. Since there is no users of CLK_MDMA2 in existing dts files this patch drops CLK_MDMA2 and replaces it with CLK_MDMA in the driver. This ensures PL330 MDMA has correct clock assigned on Exynos4x12 SoCs. Suggested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: fixed compiler warning [-Wpointer-to-int-cast]Pankaj Dubey2014-05-14
| | | | | | | | | | | | | | | | | | | | | | When compiled using ARM64 cross compiler, gcc complains as drivers/clk/samsung/clk.c:293:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: Fix VPLL lock offsetSachin Kamat2014-05-14
| | | | | | | | | | | | | | Set it as per the user manual. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5250/5420: Add gate clock for SSS moduleNaveen Krishna Chatradhi2014-05-14
| | | | | | | | | | | | | | | | | | This patch adds gating clock for SSS(Security SubSystem) module on Exynos5250/5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> [t.figa: Fixed sort order and group name.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: Initialize clock table with error pointersTomasz Figa2014-05-14
| | | | | | | | | | | | | | | | | | | | Before this patch, the driver was simply zeroing the clock table, which is incorrect, because invalid clock numbers returned NULL instead of error pointers. This patch fixes this by changing the driver to initialize the array with PTR_ERR(-ENOENT). Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
| * clk/exynos5260: add clock file for exynos5260Rahul Sharma2014-05-14
| | | | | | | | | | | | | | | | Add support for exynos5260 clocks in clock driver. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk/samsung: add support for pll2650xxRahul Sharma2014-05-14
| | | | | | | | | | | | | | | | | | | | | | Add support for pll2650xx in samsung pll file. This PLL variant is close to pll36xx but uses CON2 registers instead of CON1. Aud_pll in Exynos5260 is pll2650xx and uses this code. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk/samsung: add support for pll2550xxPankaj Dubey2014-05-14
| | | | | | | | | | | | | | | | | | | | | | exynos5260 use pll2550xx and it has different bit fields for P,M,S values as compared to pll2550. Support for pll2550xx is added here. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk/samsung: add support for multiple clock providersRahul Sharma2014-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: add clock controller driver for s3c2410, s3c2440 and s3c2442Heiko Stuebner2014-05-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver can handle the clock controllers of the socs mentioned above, as they share a common clock tree with only small differences. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As pll-rate-tables only the 12mhz variants are currently included. The original code was wrongly checking for 169mhz xti values [a 0 to much at the end], so the original 16mhz pll table would have never been included and its values are so obscure that I have no possibility to at least check their sane-ness. When using the formula from the manual the resulting frequency is near the table value but still slightly off. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add clock driver for external clock outputsHeiko Stuebner2014-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a driver for controlling the external clock outputs of s3c24xx architectures including the dclk muxes and dividers. The driver at the moment only supports the legacy non-dt boards using these clock outputs. The clock-output control itself is part of the system-controller mainly controlled by the pinctrl drivers. So it should most likely be integrated there for dt platforms. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add clock controller driver for s3c2412Heiko Stuebner2014-04-14
| | | | | | | | | | | | | | | | | | | | | | | | | | This driver can handle the clock controller in the s3c2412 soc. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add plls used by the early s3c24xx cpusHeiko Stuebner2014-04-14
| | | | | | | | | | | | | | | | | | | | | | | | | | The manuals do not give them explicit names like in later socs, so more generic names with a s3c2410-prefix were used for them. As it was common to do so in the previous implementation, functionality to change the pll rate is already included. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450Heiko Stuebner2014-04-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The three SoCs share a common clock tree which only differs in the existence of some special clocks. As with all parts common to these three SoCs the driver is named after the s3c2443, as it was the first SoC introducing this structure and there exists no other label to describe this s3c24xx epoch. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As an example the sclk_uart gate was never handled previously and the div_uart was made to be the clock used by the serial driver. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add plls used by the s3c2443Heiko Stuebner2014-04-14
| | | | | | | | | | | | | | | | | | | | The s3c2443 uses different plls that are not present yet. Therefore add the two needed types. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add pll_6552 variant for s3c2416Heiko Stuebner2014-04-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the manual s3c2416 and s3c2450 use a pll 6552 and 6553 and while the pll_6553 matches exactly the one already implemented the pll_6552 differs to the one from the s3c64xx series. The change is solely in the bit locations of the mdiv and pdiv values. All calculations are the same for both implementatons and even the proposed divider-values for specific frequencies in the manuals are the same. Therefore implement a variant that simply uses the changed bit locations if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | clk: at91: add slow clks driverBoris BREZILLON2014-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AT91 slow clk is a clk multiplexer. In some SoCs (sam9x5, sama5, sam9g45 families) this multiplexer can choose among 2 sources: an internal RC oscillator circuit and an oscillator using an external crystal. In other Socs (sam9260 family) the multiplexer source is hardcoded with the OSCSEL signal. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* | clk: at91: rework main clk implementationBoris BREZILLON2014-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AT91 main clk is a clk multiplexer and not a simple fixed rate clk as currently implemented. In some SoCs (sam9x5, sama5, sam9g45 families) this multiplexer can choose among 2 sources: an internal RC oscillator circuit and an oscillator using an external crystal. In other Socs (sam9260, rm9200 families) the multiplexer source is hardcoded to the external crystal oscillator. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* | vexpress: Initialise the sysregs before setting up the clocksCatalin Marinas2014-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following arm64 commit bc3ee18a7a57 (arm64: init: Move of_clk_init to time_init()), vexpress_osc_of_setup() is called via of_clk_init() long before initcalls are issued. Initialising the vexpress oscillators requires the vespress sysregs to be already initialised, so this patch adds an explicit call to vexpress_sysreg_of_early_init() in vexpress oscillator setup function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Will Deacon <will.deacon@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Tested-by: Pawel Moll <pawel.moll@arm.com> Acked-by: Pawel Moll <pawel.moll@arm.com> Cc: Mike Turquette <mturquette@linaro.org>
* | Merge tag 'vexpress/fixes-for-3.15' of ↵Arnd Bergmann2014-04-24
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/pawel.moll/linux into fixes ARM Versatile Express fixes for 3.15 This series contains straight-forward fixes for different Versatile Express infrastructure drivers: - NULL pointer dereference on the error path in the clk driver - out of boundary array access in the dcscb driver - broken restart/power off implementation - mis-interpreted voltage unit in the spc driver * tag 'vexpress/fixes-for-3.15' of git://git.linaro.org/people/pawel.moll/linux: ARM: vexpress/TC2: Convert OPP voltage to uV before storing power/reset: vexpress: Fix restart/power off operation arm/mach-vexpress: array accessed out of bounds clk: vexpress: NULL dereference on error path Includes an update to 3.15-rc2 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | clk: vexpress: NULL dereference on error pathDan Carpenter2014-04-24
| |/ | | | | | | | | | | | | | | | | If the allocation fails then we dereference the NULL in the error path. Just return directly. Fixes: ed27ff1db869 ('clk: Versatile Express clock generators ("osc") driver') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Pawel Moll <pawel.moll@arm.com>
* / clk: tegra: remove non-existent clocksStephen Warren2014-04-24
|/ | | | | | | | | The Tegra124 clock driver currently provides 3 clocks that don't actually exist; 2 for NAND and one for UART5/UARTE. Delete these. Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>