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* Merge tag 'clk-for-linus-3.18' of ↵Linus Torvalds2014-10-15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock tree updates from Mike Turquette: "The clk tree changes for 3.18 are dominated by clock drivers. Mostly fixes and enhancements to existing drivers as well as new drivers. This tag contains a bit more arch code than I usually take due to some OMAP2+ changes. Additionally it contains the restart notifier handlers which are merged as a dependency into several trees. The PXA changes are the only messy part. Due to having a stable tree I had to revert one patch and follow up with one more fix near the tip of this tag. Some dead code is introduced but it will soon become live code after 3.18-rc1 is released as the rest of the PXA family is converted over to the common clock framework. Another trend in this tag is that multiple vendors have started to push the complexity of changing their CPU frequency into the clock driver, whereas this used to be done in CPUfreq drivers. Changes to the clk core include a generic gpio-clock type and a clk_set_phase() function added to the top-level clk.h api. Due to some confusion on the fbdev mailing list the kernel boot parameters documentation was updated to further explain the clk_ignore_unused parameter, which is often required by users of the simplefb driver. Finally some fixes to the locking around the clock debugfs stuff was done to prevent deadlocks when interacting with other subsystems." * tag 'clk-for-linus-3.18' of git://git.linaro.org/people/mike.turquette/linux: (99 commits) clk: pxa clocks build system fix Revert "arm: pxa: Transition pxa27x to clk framework" clk: samsung: register restart handlers for s3c2412 and s3c2443 clk: rockchip: add restart handler clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate doc/kernel-parameters.txt: clarify clk_ignore_unused arm: pxa: Transition pxa27x to clk framework dts: add devicetree bindings for pxa27x clocks clk: add pxa27x clock drivers arm: pxa: add clock pll selection bits clk: dts: document pxa clock binding clk: add pxa clocks infrastructure clk: gpio-gate: Ensure gpiod_ APIs are prototyped clk: ti: dra7-atl-clock: Mark the device as pm_runtime_irq_safe clk: ti: LLVMLinux: Move __init outside of type definition clk: ti: consider the fact that of_clk_get() might return an error clk: ti: dra7-atl-clock: fix a memory leak clk: ti: change clock init to use generic of_clk_init clk: hix5hd2: add I2C clocks clk: hix5hd2: add watchdog0 clocks ...
| * clk: pxa clocks build system fixRobert Jarzmik2014-10-05
| | | | | | | | | | | | | | | | | | | | Fix the building of pxa clock drivers so that the files are actually compiled if and only if COMMON_CLK was selected by the architecture. This prevents conflicts with mach-pxa clock legacy implementation. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * Merge tag 'clk-mvebu-3.18-2' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette2014-10-03
| |\ | | | | | | | | | | | | | | | | | | | | | | | | clk-next clock mvebu changes for v3.18 (round 2) - armada 370/375 - Fix SSCG node lookup
| | * clk: mvebu: fix sscg node lookupThomas Petazzoni2014-09-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 15917b16022427c53755abff4dc7051f3076dd7a ("clk: mvebu: Fix clk frequency value if SSCG is enabled") introduced some logic in the common mvebu clock code to adjust the clock frequency according to the configuration of the SSCG. In order to do this, it looks up for a DT node called "sscg" and maps it before accessing the SSCG configuration register. However, the lookup is currently done using: sscg_np = of_find_node_by_name(np, "sscg"); where "np" is a pointer to the DT node of the clock for which we are calculating the adjusted frequency. This means that if the "sscg" node is *after* the clock node in the Device Tree, it works fine (and that's the case for Armada 370). However, if it turns out that the "sscg" node is *before* the clock node in the Device Tree, it won't work because the sscg node will not be found. What we really want here is a search of the entire Device Tree, not only starting from the clock node, so instead of passing "np" as first argument of of_find_node_by_name(), we simply need to pass NULL. Passing a non-NULL argument is typically used in a loop, so that the search for the next matching node starts right after the node that was matched. This makes the "np" argument to the kirkwood_fix_sscg_deviation() function unnecessary, which leads to further cleanups. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Fixes: 15917b1602242 ("clk: mvebu: Fix clk frequency value if SSCG is enabled") Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1410880503-2322-1-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | Merge tag 'v3.18-rockchip-clk2' of ↵Mike Turquette2014-10-01
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Allow parent rate changes for i2s on rk3288 and rockchip as well as s3c24xx restart handlers.
| | * | clk: samsung: register restart handlers for s3c2412 and s3c2443Heiko Stübner2014-10-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | S3C2412, S3C2443 and their derivatives contain a special software-reset register in their system-controller. Therefore register a restart handler for those. Tested on a s3c2416-based board, s3c2412 compile-tested. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
| | * | clk: rockchip: add restart handlerHeiko Stübner2014-10-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add infrastructure to write the correct value to the restart register and register the restart notifier for both rk3188 (including rk3066) and rk3288. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
| | * | clk: rockchip: rk3288: i2s_frac adds flag to set parent's rateJianqun2014-10-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The relation of i2s nodes as follows: i2s_src 0 0 594000000 0 i2s_frac 0 0 11289600 0 i2s_pre 0 0 11289600 0 sclk_i2s0 0 0 11289600 0 i2s0_clkout 0 0 11289600 0 hclk_i2s0 1 1 99000000 0 sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for "i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0". Tested on rk3288 board using max98090, with command "aplay <music.wav>" Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6 Signed-off-by: Jianqun <jay.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | | Merge branch 'clk-pxa27x' into clk-nextMike Turquette2014-09-30
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| | * | | clk: add pxa27x clock driversRobert Jarzmik2014-09-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move pxa27x clock drivers from arch/arm/mach-pxa to driver/clk. In the move : - convert to new clock framework legacy clocks - provide clocks as before for platform data based boards - provide clocks through devicetree Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| | * | | clk: add pxa clocks infrastructureRobert Jarzmik2014-09-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a the common code used by all PXA variants. This is the first step in the transition from architecture defined clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to have the same features (and not all the features) of the existing clocks, and enable the transition of PXA to device-tree. All PXA rely on a "CKEN" type clock, which : - has a gate (bit in CKEN register) - is generated from a PLL, generally divided - has an alternate low power clock Each variant will specialize the CKEN clock : - pxa25x have no low power clock - pxa27x in low power use always the 13 MHz ring oscillator - pxa3xx in low power have specific dividers for each clock The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get a handle on the clock. While pxa-clock.h will describe all the clocks of all the variants, each variant will only use a subset of it. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | clk: gpio-gate: Ensure gpiod_ APIs are prototypedMark Brown2014-09-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpio-gate clock uses the gpiod_ APIs but does not directly include the header for them causing build failures in some configurations including ARM allnoconfig. Include the header directly. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | Merge tag 'for_3.18/samsung-clk' of ↵Mike Turquette2014-09-30
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next Samsung clock patches for v3.18 1) non-critical fixes (without the need to push to stable) fa0111be4ff3 clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation b511593d7165 clk: samsung: exynos4: fix g3d clocks c14254300131 clk: samsung: exynos4: add missing smmu_g2d clock and update comments 22842d244af3 clk: samsung: exynos5260: fix typo in clock name e82ba578ccde clk: samsung: exynos3250: fix width field of mout_mmc0/1 59037b92f440 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock 5ce37f266650 clk: samsung: exynos3250: fix mout_cam_blk parent list 2) Clock driver extensions 07ccf02ba5c3 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU d0e73eaf1925 ARM: dts: exynos3250: Add CMU node for DMC domain clocks e3c3f19bc618 clk: samsung: exynos3250: Register DMC clk provider 4676f0aab9dc clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
| | * | | | clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiationThomas Abraham2014-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'div_core2' clock and the 'arm_clk' divider clocks are instances of the same divider clock. So remove the 'arm_clk' clock instance. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> [tomasz.figa@gmail.com: Fixed remaining occurences of 'arm_clk'.] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| | * | | | clk: samsung: exynos4: fix g3d clocksMarek Szyprowski2014-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked g3d gate clock bits for this purpose and didn't provide real g3d clock at all. This patch fixes this issue by adding proper definition for g3d clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d. In addition CLK_SET_RATE_PARENT flag is dropped from sclk_g3d, because it does not make any sense and most likely has been added by mistake. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> [tomasz.figa@gmail.com: Adjusted commit message.] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| | * | | | clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocksMarek Szyprowski2014-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for exporting mout_hdmi and mout_mixer to device tree. Access to those clocks is required to correctly setup HDMI module on Exynos 4210 and 4x12 SoCs. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> CC: Mike Turquette <mturquette@linaro.org> CC: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| | * | | | clk: samsung: exynos4: add missing smmu_g2d clock and update commentsMarek Szyprowski2014-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing smmu_g2d clock implementation and updates comment about Exynos4 clocks from 278-282 range. Those clocks are available on all Exynos4 SoC series, so the misleading comment has been removed. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| | * | | | clk: samsung: exynos3250: Register DMC clk providerKrzysztof Kozlowski2014-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock provider for clocks in DMC domain including EPLL and BPLL. The DMC clocks are necessary for Exynos3 devfreq driver. The DMC clock domain uses different address space (0x105C0000) than standard clock domain (0x10030000 - 0x10050000). The difference is huge enough to add new DT node for the clock provider, rather than extending existing address space. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| | * | | | clk: samsung: exynos5260: fix typo in clock nameChander Kashyap2014-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parent name added in parent list as mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, is different than the defined parent due to typo. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Chander Kashyap <k.chander@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| | * | | | clk: samsung: exynos3250: fix width field of mout_mmc0/1Pankaj Dubey2014-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per Exynos3250 user manual mmc0/1 mux selection has 4 bit wide. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| | * | | | clk: samsung: exynos3250: fix width and shift of div_spi0_isp clockPankaj Dubey2014-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update shift and width field of div_spi0_isp clock as per Exynos3250 user manual. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| | * | | | clk: samsung: exynos3250: fix mout_cam_blk parent listPankaj Dubey2014-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per user manual of Exynos3250 SRC_CAM can select div_cam_blk_320 if it's value is 0xC, so placing div_cam_blk_320 at proper index in parent list of mout_cam_blk. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * | | | | Merge branch 'for-v3.18/ti-clk-driver' of github.com:t-kristo/linux-pm into ↵Mike Turquette2014-09-30
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | clk-next
| | * | | | | clk: ti: dra7-atl-clock: Mark the device as pm_runtime_irq_safePeter Ujfalusi2014-09-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is safe to call the pm sync calls in interrupt context in this driver. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * | | | | clk: ti: LLVMLinux: Move __init outside of type definitionBehan Webster2014-09-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As written, the __init for ti_clk_get_div_table is in the middle of the return type. The gcc documentation indicates that section attributes should be added to the end of the function declaration: extern void foobar (void) __attribute__ ((section ("bar"))); However gcc seems to be very permissive with where attributes can be placed. clang on the other hand isn't so permissive, and fails if you put the section definition in the middle of the return type: drivers/clk/ti/divider.c:298:28: error: expected ';' after struct static struct clk_div_table ^ ; drivers/clk/ti/divider.c:298:1: warning: 'static' ignored on this declaration [-Wmissing-declarations] static struct clk_div_table ^ drivers/clk/ti/divider.c:299:9: error: type specifier missing, defaults to 'int' [-Werror,-Wimplicit-int] __init *ti_clk_get_div_table(struct device_node *node) ~~~~~~ ^ drivers/clk/ti/divider.c:345:9: warning: incompatible pointer types returning 'struct clk_div_table *' from a function with result type 'int *' [-Wincompatible-pointer-types] return table; ^~~~~ drivers/clk/ti/divider.c:419:9: warning: incompatible pointer types assigning to 'const struct clk_div_table *' from 'int *' [-Wincompatible-pointer-types] *table = ti_clk_get_div_table(node); ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~ 3 warnings and 2 errors generated. By convention, most of the kernel code puts section attributes between the return type and function name. In the case where the return type is a pointer, it's important to place the '*' on left of the __init. This updated code works for both gcc and clang. Signed-off-by: Behan Webster <behanw@converseincode.com> Reviewed-by: Mark Charlebois <charlebm@gmail.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * | | | | clk: ti: consider the fact that of_clk_get() might return an errorSebastian Andrzej Siewior2014-09-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I "forgot" to update the dtb and the kernel crashed: |Unable to handle kernel NULL pointer dereference at virtual address 0000002e |PC is at __clk_get_flags+0x4/0xc |LR is at ti_dt_clockdomains_setup+0x70/0xe8 because I did not have the clock nodes. of_clk_get() returns an error pointer which is not checked here. Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * | | | | clk: ti: dra7-atl-clock: fix a memory leakTero Kristo2014-09-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_clk_add_provider makes an internal copy of the parent_names property while its called, thus it is no longer needed after this call and can be freed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
| | * | | | | clk: ti: change clock init to use generic of_clk_initTero Kristo2014-09-29
| | | |/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the TI clock driver initialized all the clocks hierarchically under each separate clock provider node. Now, each clock that requires IO access will instead check their parent node to find out which IO range to use. This patch allows the TI clock driver to use a few new features provided by the generic of_clk_init, and also allows registration of clock nodes outside the clock hierarchy (for example, any external clocks.) Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Stefan Assmann <sassmann@kpanic.de> Acked-by: Tony Lindgren <tony@atomide.com>
| * | | | | Merge tag 'hix5hd2-clock-for-3.18-v2' of ↵Mike Turquette2014-09-28
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://github.com/hisilicon/linux-hisi into clk-next Hisilicon HiX5HD2 clock updates for 3.18-v2 - Add I2C clocks - Add watchdog clocks - Add sd clocks - Add complex clock implementation to support sata, usb and ethernet
| | * | | | | clk: hix5hd2: add I2C clocksWei Yan2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hix5hd2 add I2C clocks (I2C0~i2C5) Signed-off-by: Wei Yan <sledge.yanwei@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| | * | | | | clk: hix5hd2: add watchdog0 clocksGuoxiong Yan2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hix5hd2 add watchdog0 clocks Signed-off-by: Guoxiong Yan <yanguoxiong@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| | * | | | | clk: hix5hd2: add sd clkJiancheng Xue2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| | * | | | | clk: hix5hd2: add complex clkZhangfei Gao2014-09-27
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support clk of sata, usb and ethernet Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | | | | clk: use uninitialized_var instead setting 'flags' to 0 directly.Xiubo Li2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting 'flags' to zero will be certainly a misleading way to avoid warning of 'flags' may be used uninitialized. uninitialized_var is a correct way because the warning is a false possitive. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | Merge tag 'sunxi-clocks-for-3.18' of ↵Mike Turquette2014-09-27
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner Clocks Additions for 3.18 The most important part of this serie is the addition of the phase API to handle the MMC clocks in the Allwinner SoCs. Apart from that, the A23 gained a new mbus driver, and there's a fix for a incorrect divider table on the APB0 clock.
| | * | | | | clk: sunxi: Add sun8i MBUS clock supportChen-Yu Tsai2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MBUS clock on sun8i is slightly different from the old mod0 clocks. The divider is 3 bits wider, while also needing a divider table for the higher 4 values, which all set the same divider. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | clk: sunxi: mod0: Introduce MMC proper phase handlingMaxime Ripard2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MMC clock we thought we had until now are actually not one but three different clocks. The main one is unchanged, and will have three outputs: - The clock fed into the MMC - a sample and output clocks, to deal with when should we output/sample data to/from the MMC bus The phase control we had are actually controlling the two latter clocks, but the main MMC one is unchanged. We can adjust the phase with a 3 bits value, from 0 to 7, 0 meaning a 180 phase shift, and the other values being the number of periods from the MMC parent clock to outphase the clock of. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| | * | | | | clk: sunxi: Move mbus to mod0 fileMaxime Ripard2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the MBUS clock to the module clocks file. It's pretty trivial, but still requires to enable the clocks to make sure it won't get disabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| | * | | | | clk: sunxi: Move mod0 clock to a file of its ownMaxime Ripard2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we know have the ability to declare factors clock outside of clk-sunxi, create a new mod0 driver to deal with the mod0 clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| | * | | | | clk: sunxi: Introduce mbus compatibleMaxime Ripard2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though the mbus clock is a regular module clock, given its nature, it needs to be enabled all the time. Introduce a new compatible, to differentiate it from the other module clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| | * | | | | clk: sunxi: factors: Invert the probing logicMaxime Ripard2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, the factors clock probing was done directly by sunxi_init_clocks, with the factors registration being called directly with the clocks data passed as an argument. This approch has shown its limits when we added more clocks, since we couldn't really split code with such a logic in smaller files, and led to a huge file having all the clocks. Introduce an intermediate probing function, so that factor clocks will be able to directly be called by CLK_OF_DECLARE, which will in turn ease the split into several files. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| | * | | | | clk: Add a function to retrieve phaseMaxime Ripard2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function. This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset. Add a new get_phase function for the drivers to implement so that we can get this value. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Hans de Goede <hdegoede@redhat.com>
| | * | | | | clk: introduce clk_set_phase function & callbackMike Turquette2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A common operation for a clock signal generator is to shift the phase of that signal. This patch introduces a new function to the clk.h API to dynamically adjust the phase of a clock signal. Additionally this patch introduces support for the new function in the common clock framework via the .set_phase call back in struct clk_ops. Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Hans de Goede <hdegoede@redhat.com>
| | * | | | | clk: sunxi: add correct divider table for sun4i-apb0 clockChen-Yu Tsai2014-09-13
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sun4i-apb0 clock, as found on all platforms using it, is a power-of-two-based divider clock, with a special divider of 2 for value 0. This was causing the clock framework to incorrectly calculate the clock rate for apb1 and related modules on sun6i and sun8i. On sun[4/5/7]i, u-boot SPL configures the divider with value 1 for /2 divider, so no suprises there. This patch adds a proper divider table for it, so the correct clock rate can be calculated. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | | | Merge tag 'v3.18-rockchip-cpuclk' of ↵Mike Turquette2014-09-27
| |\ \ \ \ \ | | | |_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next CPU clock handling for Rockchip SoCs
| | * | | | clk: rockchip: switch to using the new cpuclk type for armclkHeiko Stuebner2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the necessary soc-specific divider values and switches the armclk to use the newly introduced cpuclk type. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org>
| | * | | | clk: rockchip: add new clock-type for the cpuclkHeiko Stuebner2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When changing the armclk on Rockchip SoCs it is supposed to be reparented to an alternate parent before changing the underlying pll and back after the change. Additionally there exist clocks that are very tightly bound to the armclk whose divider values are set according to the armclk rate. Add a special clock-type to handle all that. The rate table and divider values will be supplied from the soc-specific clock controllers. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> On a rk3288-board: Tested-by: Doug Anderson <dianders@chromium.org>
| | * | | | clk: rockchip: make tightly bound armclk child-clocks read-onlyHeiko Stuebner2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rockchip SoCs contain clocks tightly bound to the armclk, where the best rate / divider is supplied by the vendor after careful measuring. Often this ideal rate may be greater than the current rate. Therefore prevent the ccf from trying to set these dividers itself by setting them to read-only. In the case of the rk3066, this also includes the aclk_cpu, which makes it necessary to also split its direct child-clocks (pclk_cpu, hclk_cpu, ...) into individual definitions for rk3066 and rk3188. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org>
| | * | | | clk: rockchip: reparent aclk_cpu_pre to the gpllHeiko Stuebner2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | aclk_cpu_pre on the rk3188 can either be sourced from the armclk or the gpll. To reduce complexity on apll changes caused by cpufreq, reparent it always to the gpll source. If really necessary it could be reparented back on a per board level using the assigned-clocks mechanism. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * | | | clk: rockchip: fix rk3288 pll status register locationJianqun2014-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In RK3288, APLL lock status bit is in GRF_SOC_STATUS1, but in RK3188, is GRFSOC_STATUS0. Signed-off-by: Jianqun <jay.xu@rock-chips.com> Also name the constant accordingly as GRF_SOC_STATUS1 to prevent confusion. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 22:18:03 -0500