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* Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6Linus Torvalds2009-06-11
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (266 commits) sh: Tie sparseirq in to Kconfig. sh: Wire up sys_rt_tgsigqueueinfo. sh: Fix sys_pwritev() syscall table entry for sh32. sh: Fix sh4a llsc-based cmpxchg() sh: sh7724: Add JPU support sh: sh7724: INTC setting update sh: sh7722 clock framework rewrite sh: sh7366 clock framework rewrite sh: sh7343 clock framework rewrite sh: sh7724 clock framework rewrite V3 sh: sh7723 clock framework rewrite V2 sh: add enable()/disable()/set_rate() to div6 code sh: add AP325RXA mode pin configuration sh: add Migo-R mode pin configuration sh: sh7722 mode pin definitions sh: sh7724 mode pin comments sh: sh7723 mode pin V2 sh: rework mode pin code sh: clock div6 helper code sh: clock div4 frequency table offset fix ...
| * sh: Tie sparseirq in to Kconfig.Paul Mundt2009-06-11
| | | | | | | | | | | | | | | | | | Now that the dependent patches are merged, we are ready to enable sparseirq support. This simply adds the Kconfig option, and then converts from the _cpu to the _node allocation routines to follow the upstream sparseirq API changes. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Wire up sys_rt_tgsigqueueinfo.Paul Mundt2009-06-11
| | | | | | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Fix sys_pwritev() syscall table entry for sh32.Paul Mundt2009-06-11
| | | | | | | | | | | | | | | | There was a typo here that had this as sys_writev() instead of sys_pwritev(), fix this up. sh64 got this right, as did the preadv() case. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Fix sh4a llsc-based cmpxchg()Aoi Shinkai2009-06-11
| | | | | | | | | | | | | | | | | | | | This fixes up a typo in the ll/sc based cmpxchg code which apparently wasn't getting a lot of testing due to the swapped old/new pair. With that fixed up, the ll/sc code also starts using it and provides its own atomic_add_unless(). Signed-off-by: Aoi Shinkai <shinkoi2005@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: sh7724: Add JPU supportKuninori Morimoto2009-06-11
| | | | | | | | | | | | Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Acked-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: sh7724: INTC setting updateKuninori Morimoto2009-06-11
| | | | | | | | | | | | | | This patch follows Rev 0.50 manual Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: sh7722 clock framework rewriteMagnus Damm2009-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch rewrites the sh7722 clock framework code. The new code makes use of the recently merged div4, div6 and mstp32 helper code. Both extal and dll are supported as input clocks to the pll. While at it, now when all SuperH Mobile processors are converted, fix CONFIG_SH_CLK_CPG_LEGACY to depend on CONFIG_ARCH_SHMOBILE. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: sh7366 clock framework rewriteMagnus Damm2009-06-11
| | | | | | | | | | | | | | | | | | | | This patch rewrites the sh7366 clock framework code. The new code makes use of the recently merged div4, div6 and mstp32 helper code. Both extal and dll are supported as input clocks to the pll. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: sh7343 clock framework rewriteMagnus Damm2009-06-11
| | | | | | | | | | | | | | | | | | | | This patch rewrites the sh7343 clock framework code. The new code makes use of the recently merged div4, div6 and mstp32 helper code. Both extal and dll are supported as input clocks to the pll. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: sh7724 clock framework rewrite V3Magnus Damm2009-06-11
| | | | | | | | | | | | | | | | | | | | | | This patch contains V3 of the sh7724 clock framework rewrite. The new code makes use of the recently merged div4, div6 and mstp32 helper code. Both extal and fll are supported as input clocks to the pll. The div6 clocks are fed through a divide-by-3 block. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: sh7723 clock framework rewrite V2Magnus Damm2009-06-11
| | | | | | | | | | | | | | | | | | | | This patch contains V2 of the sh7723 clock framework rewrite. The new code makes use of the recently merged div4, div6 and mstp32 helper code. Both extal and dll are supported as input clocks to the pll. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: add enable()/disable()/set_rate() to div6 codeMagnus Damm2009-06-11
| | | | | | | | | | | | | | | | | | | | This patch updates the div6 clock helper code to add support for enable(), disable() and set_rate() callbacks. Needed by the camera clock enabling board code on Migo-R. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: add AP325RXA mode pin configurationMagnus Damm2009-06-11
| | | | | | | | | | | | | | This patch adds mode pin configuration to ap325rxa. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: add Migo-R mode pin configurationMagnus Damm2009-06-11
| | | | | | | | | | | | | | | | This patch adds mode pin configuration and a machvec structure to Migo-R. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: sh7722 mode pin definitionsMagnus Damm2009-06-11
| | | | | | | | | | | | | | | | This patch adds sh7722 mode pin and pin function controller comments. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: sh7724 mode pin commentsMagnus Damm2009-06-11
| | | | | | | | | | | | | | | | This patch adds comments for the sh7724 mode pins and pin function controller. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: sh7723 mode pin V2Magnus Damm2009-06-11
| | | | | | | | | | | | | | | | This patch is sh7723 mode pin V2. Mode pins and pin function controller comments are added. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: rework mode pin codeMagnus Damm2009-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch reworks the mode pin code to keep the pin definitions in one place. The mode pins values are now the value of the bit instead of bit number. With this patch in place the sh7785 header file contains mode pin comments. The sh7785 clock code and the sh7785lcr board code are updated to reflect the new shared mode pins. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: clock div6 helper codeMagnus Damm2009-06-11
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds div6 clock helper code. The div6 clocks are simply 6-bit divide-by-n modules where n is 1 to 64. Needed for vclk on sh7722, sh7723, sh7343 and sh7366. sh7724 needs this even more for vclk, fclka, fclkb, irdaclk and spuclk. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: clock div4 frequency table offset fixMagnus Damm2009-06-11
| | | | | | | | | | | | | | | | | | This patch fixes the per clock offset calculation in sh_clk_div4_register(). Without this patch the offset to the frequency table for each clock is incorrect. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * Merge branch 'master' of ↵Paul Mundt2009-06-11
| |\ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
| * | sh: plug vsyscall dir in to archclean.Paul Mundt2009-06-10
| | | | | | | | | | | | | | | | | | | | | | | | The vsyscall targets are presently not cleaned up, so just handle it in the archclean rule. Reported-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: 16-bit get_unaligned() sh4a fixMagnus Damm2009-06-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the 16-bit case of the sh4a specific unaligned access implementation. Without this patch the 16-bit version of sh4a get_unaligned() results in a 32-bit read which may read more data than intended and/or cross page boundaries. Unbreaks mtd NOR write handling on Migo-R. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: sh7723: L2 cache initialization.Kuninori Morimoto2009-06-01
| | | | | | | | | | | | | | | Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: sh7724: L2 cache initialization.Kuninori Morimoto2009-06-01
| | | | | | | | | | | | | | | Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: add weak l2_cache_init function.Kuninori Morimoto2009-06-01
| | | | | | | | | | | | | | | Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: add RAMCR definition for sh4Kuninori Morimoto2009-06-01
| | | | | | | | | | | | | | | Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: fix CONFIG_SH_PCLK_FREQ bug for sh7724Kuninori Morimoto2009-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SH_PCLK_FREQ=33333333 is correct for sh7724. sh7724 master clock is 33333333, but peripheral is 41666666. This bug came to light because sh-sci driver had changed clk from "module_clk" to "peripheral_clk" Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: Tidy up SH-4A boot_cpu_data.flags probing.Paul Mundt2009-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This tidies up the boot_cpu_data.flags probing on SH-4A. All of them have a few things in common, which we can blindly set, rather than having each subtype have to set the same flags. We can also make assumptions about cache ways and the validity of PTEA, so this also kills off CPU_HAS_PTEA as a config option. There was also a bug in the FPU probing, which is now tidied up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: Tidy up the optional L2 probing, wire it up for SH7786.Paul Mundt2009-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | This tidies up the L2 probing, as it may or may not be implemented on a CPU, regardless of whether it is supported. This converts the cvr validity checks from BUG_ON()'s to simply clearing the CPU_HAS_L2_CACHE flag and moving on with life. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: hook up shared div4 clock code to sh7785Magnus Damm2009-06-01
| | | | | | | | | | | | | | | | | | | | | Hook up the shared 4-bit divisor clock code to sh7785. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: shared div4 clock codeMagnus Damm2009-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add shared code for 4-bit divisor clocks. Processor specific code can use SH_CLK_DIV4() to initialize div4 clocks, and then use sh_clk_div4_register() for registration. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: hook up shared mstp32 clock code to sh7785Magnus Damm2009-06-01
| | | | | | | | | | | | | | | | | | | | | Hook up the shared 32-bit module stop bit code to sh7785. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: shared mstp32 clock codeMagnus Damm2009-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add shared 32-bit module stop bit clock support. Processor specific code can use SH_CLK_MSTP32() to initialize module stop bit clocks, and then use sh_clk_mstp32() for registration. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: SH7724 has an L2 cache.Kuninori Morimoto2009-06-01
| | | | | | | | | | | | | | | | | | | | | Add the CPU_HAS_L2_CACHE flag to SH7724. Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: sh7785 pll configuration from mode pinMagnus Damm2009-06-01
| | | | | | | | | | | | | | | | | | | | | | | | This patch modifies the sh7785 clock code to use the MODE4 value to switch between 72x and 36x PLL multiplication. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: sh7785lcr mode pin configurationMagnus Damm2009-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds mode pin support to the sh7785lcr board. The harware allows the user to control the mode pins using dip switches S1 and S2, but from the software the pins are fixed to the factory default since we have no way to reading out this configuration from software. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: sh7785 mode pin definitionsMagnus Damm2009-06-01
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds sh7785 mode pin definitions. Mode pins and pin function controller comments are added as well. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: boot word / mode pin support V2Magnus Damm2009-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mode pin support for the SuperH architecture V2. With this patch applied the board code can add their own function to export the cpu mode pin configuration. In most cases this will be a constant bitmap, but boards that allow reading this from a register can instead read out the pin state from hardware. The code warns if a pin is tested but no board specific mode pin function has been provided. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | sh: pci-sh7780: Fix up for PCI_DISABLE_MWI changes.Paul Mundt2009-05-26
| | | | | | | | | | | | | | | | | | | | | | | | This fixes a build error where references to pci_cache_line_size are undefined, as this ceases to be exported when PCI_DISABLE_MWI is enabled, as is now the default. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | Merge branch 'sh/clkfwk'Paul Mundt2009-05-26
| |\ \
| | * | sh: remove clk_ops->build_rate_table()Magnus Damm2009-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the ->build_rate_table() callback, ->recalc() may instead be used for this purpose. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| | * | sh: use shared frequency tables on sh7785Magnus Damm2009-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch converts the sh7785 clock code to make use of clk_rate_table_build() and clk_rate_table_round(). The ->build_rate_table() callback is removed, the table building is instead handled in ->recalc(). Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| | * | sh: add shared clock framework frequency table codeMagnus Damm2009-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SuperH-specific clock framework helper functions: - clk_rate_table_build() - build cpufreq table from divisors/multipliers - clk_rate_table_round() - use cpufreq table to find matching frequency Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| | * | sh: add pll_clk to sh7785Magnus Damm2009-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch converts the sh7785 pll implementation from the all-in-one code in frqmr_recalc() and frqmr_build_rate_table() to a separate struct clk. This allows us to remove the processor specific multiplier and use generic rate table functions. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| | * | sh: clkfwk: Make clock-cpg usable for non-legacy platforms.Paul Mundt2009-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a new SH_CLK_CPG for parts that have CPG support. SH_CLK_CPG_LEGACY is made to depend on this, and still needs to be set for platforms that want clock-cpg to register the legacy clocks. With this new config item in place, it is now possible to start layering more generic CPG code in place while other platforms transition off of the legacy clocks. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| | * | sh: clkfwk: beyond ARRAY_SIZE of onchip_ops for sh7722.Roel Kluin2009-05-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not go beyond ARRAY_SIZE of onchip_ops Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| | * | sh: clkfwk branch compile fix for clock-sh7722Magnus Damm2009-05-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix clkfwk branch compile error in clock-sh7722.c. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| | * | sh: clkfwk: Add MSTP bits to SH7785 clock framework.Paul Mundt2009-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This plugs in all of the MSTP functions in to the clock framework, and hands them off to the platform devices that want them. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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