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* [MIPS] Add MTD device support for CobaltYoichi Yuasa2007-02-20
| | | | | | | | This patch has added MTD device support for Cobalt. Moreover, removes old type FlashROM support. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [PATCH] tick management: make broadcast dependent on local APICThomas Gleixner2007-02-19
| | | | | | | | | | The broadcast functionality is only necessary when a local APIC is available. Make the config switch depend on X86_LOCAL_APIC. This resolves the mach-voyager breakage introduced by the tick managament code. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [PATCH] Declare init_irq_proc before we use it.Andrew Morton2007-02-19
| | | | | | | | | | | | | | | | | | | | | | | powerpc gets: init/main.c: In function `do_basic_setup': init/main.c:714: warning: implicit declaration of function `init_irq_proc' but we cannot include linux/irq.h in generic code. Fix it by moving the declaration into linux/interrupt.h instead. And make sure all code that defines init_irq_proc() is including linux/interrupt.h. And nuke an ifdef-in-C Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@elte.hu> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2007-02-19
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Update defconfigs [MIPS] Support for several more SNI RM models. [MIPS] Include <asm/bugs> to for declaration of check_bugs32. [MIPS] Add external declaration of pagetable_init() to pgalloc.h [MIPS] Make kernel_thread_helper() static [MIPS] Make __declare_dbe_table static and avoid it getting optimized away [MIPS] Use MIPS R2 instructions for bitops. [MIPS] signals: Share even more code. [MIPS] Fix CONFIG_MIPS32_N32=y CONFIG_MIPS32_O32=n build [MIPS] Iomap implementation. [MIPS] <asm/compat-signal.h> needs to include <asm/uaccess.h>. [MIPS] IP27: Fix warning. [MIPS] Fix sigset_t endianess swapping issues in 32-bit compat code.
| * [MIPS] Update defconfigsRalf Baechle2007-02-18
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Support for several more SNI RM models.Thomas Bogendoerfer2007-02-18
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Include <asm/bugs> to for declaration of check_bugs32.Ralf Baechle2007-02-18
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Add external declaration of pagetable_init() to pgalloc.hAtsushi Nemoto2007-02-18
| | | | | | | | | | | | | | | | | | | | This fixes some sparse warnings. pgtable-32.c:15:6: warning: symbol 'pgd_init' was not declared. Should it be static? pgtable-32.c:32:13: warning: symbol 'pagetable_init' was not declared. Should it be static? Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Make kernel_thread_helper() staticAtsushi Nemoto2007-02-18
| | | | | | | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Make __declare_dbe_table static and avoid it getting optimized awayRalf Baechle2007-02-18
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] signals: Share even more code.Ralf Baechle2007-02-18
| | | | | | | | | | | | | | native and compat do_signal and handle_signal are identical and can easily be unified. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Fix CONFIG_MIPS32_N32=y CONFIG_MIPS32_O32=n buildRalf Baechle2007-02-18
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Iomap implementation.Ralf Baechle2007-02-18
| | | | | | | | | | | | | | | | | | | | | | This implementation has support for the concept of one separate ioport address space by PCI domain. A pointer to the virtual address where the port space of a domain has been mapped has been added to struct pci_controller and systems should be fixed to fill in this value. For single domain systems this will be the same value as passed to set_io_port_base(). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] IP27: Fix warning.Ralf Baechle2007-02-18
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Fix sigset_t endianess swapping issues in 32-bit compat code.Atsushi Nemoto2007-02-18
| | | | | | | | | | | | | | | | | | | | access_ok in compat-signal.h is wrong (checking destination instead of source) and redundant (already checked before calling this function). Also sf_mask in struct sigframe32 should be compat_sigset_t type. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivialLinus Torvalds2007-02-19
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial: (25 commits) Documentation/kernel-docs.txt update. arch/cris: typo in KERN_INFO Storage class should be before const qualifier kernel/printk.c: comment fix update I/O sched Kconfig help texts - CFQ is now default, not AS. Remove duplicate listing of Cris arch from README kbuild: more doc. cleanups doc: make doc. for maxcpus= more visible drivers/net/eexpress.c: remove duplicate comment add a help text for BLK_DEV_GENERIC correct a dead URL in the IP_MULTICAST help text fix the BAYCOM_SER_HDX help text fix SCSI_SCAN_ASYNC help text trivial documentation patch for platform.txt Fix typos concerning hierarchy Fix comment typo "spin_lock_irqrestore". Fix misspellings of "agressive". drivers/scsi/a100u2w.c: trivial typo patch Correct trivial typo in log2.h. Remove useless FIND_FIRST_BIT() macro from cardbus.c. ...
| * | arch/cris: typo in KERN_INFONicolas Kaiser2007-02-17
| | | | | | | | | | | | | | | | | | | | | Typo in KERN_INFO. Signed-off-by: Nicolas Kaiser <nikai@nikai.net> Signed-off-by: Adrian Bunk <bunk@stusta.de>
| * | Storage class should be before const qualifierTobias Klauser2007-02-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The C99 specification states in section 6.11.5: The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature. Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Adrian Bunk <bunk@stusta.de>
| * | Fix typos concerning hierarchyUwe Kleine-König2007-02-17
| | | | | | | | | | | | | | | | | | | | | | | | heirarchical, hierachical -> hierarchical heirarchy, hierachy -> hierarchy Signed-off-by: Uwe Kleine-König <zeisberg@informatik.uni-freiburg.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
| * | Fix comment typo "spin_lock_irqrestore".Robert P. J. Day2007-02-17
| | | | | | | | | | | | | | | | | | | | | Fix "spin_lock_irqrestore" to "spin_unlock_irqrestore." Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Adrian Bunk <bunk@stusta.de>
| * | Replace remaining references to "driverfs" with "sysfs".Robert P. J. Day2007-02-17
| | | | | | | | | | | | | | | | | | | | | Globally, s/driverfs/sysfs/g. Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Adrian Bunk <bunk@stusta.de>
| * | Use ARRAY_SIZE() macro in i386 relocs.c fileRobert P. J. Day2007-02-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Change the explicit code in the relocs.c file to use ARRAY_SIZE() and add a definition of ARRAY_SIZE() since this is a userspace program and wouldn't include kernel.h. Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Adrian Bunk <bunk@stusta.de>
| * | Various typo fixes.Robert P. J. Day2007-02-17
| | | | | | | | | | | | | | | | | | | | | | | | Correct mis-spellings of "algorithm", "appear", "consistent" and (shame, shame) "kernel". Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Adrian Bunk <bunk@stusta.de>
| * | kbuild: Replace remaining "depends" with "depends on"Robert P. J. Day2007-02-17
| |/ | | | | | | | | | | | | | | Replace the very few remaining "depends" Kconfig directives with "depends on". Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* | Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2007-02-19
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (117 commits) [ARM] 4058/2: iop32x: set ->broken_parity_status on n2100 onboard r8169 ports [ARM] 4140/1: AACI stability add ac97 timeout and retries [ARM] 4139/1: AACI record support [ARM] 4138/1: AACI: multiple channel support for IRQ handling [ARM] 4211/1: Provide a defconfig for ns9xxx [ARM] 4210/1: base for new machine type "NetSilicon NS9360" [ARM] 4222/1: S3C2443: Remove reference to missing S3C2443_PM [ARM] 4221/1: S3C2443: DMA support [ARM] 4220/1: S3C24XX: DMA system initialised from sysdev [ARM] 4219/1: S3C2443: DMA source definitions [ARM] 4218/1: S3C2412: fix CONFIG_CPU_S3C2412_ONLY wrt to S3C2443 [ARM] 4217/1: S3C24XX: remove the dma channel show at startup [ARM] 4090/2: avoid clash between PXA and SA1111 defines [ARM] 4216/1: add .gitignore entries for ARM specific files [ARM] 4214/2: S3C2410: Add Armzone QT2410 [ARM] 4215/1: s3c2410 usb device: per-platform vbus_draw [ARM] 4213/1: S3C2410 - Update definition of ADCTSC_XY_PST [ARM] 4098/1: ARM: rtc_lock only used with rtc_cmos [ARM] 4137/1: Add kexec support [ARM] 4201/1: SMP barriers pair needed for the secondary boot process ... Fix up conflict due to typedef removal in sound/arm/aaci.h
| * \ Merge the easy part of the IOP branchRussell King2007-02-18
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| | * | [ARM] 4184/1: iop: cp6 access handler (undef_hook)Dan Williams2007-02-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable svc access to cp6 via an undefined instruction hook. Do not enable access for usr code. This patch also makes iop13xx select PLAT_IOP, this requires a small change to drivers/i2c/busses/i2c-iop3xx.c. Per Lennert Buytenhek's note, the cp6 trap routine is moved to arch/arm/plat-iop Per Nicolas Pitre's note, the cp_wait is skipped since the latency to return to the faulting function is longer than cp_wait. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | [ARM] 4183/1: do_undefinstr: read svc undefined instructions with svc privilegesDan Williams2007-02-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | do_undefinstr currently does not expect undefined instructions in kernel code, since it always uses get_user() to read the instruction. Dereference the 'pc' pointer directly in the SVC case. Per Nicolas Pitre's note, kernel code is never in thumb mode. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | [ARM] 4182/1: iop3xx: fix the ioremap implementation to not remap static rangesDan Williams2007-02-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a custom ioremap implementation for iop3xx. This saves establishing new mappings. It also cleans up the PCI IO resource to be a physical address rather than a virtual address as Russell pointed out on the original iop13xx port. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | Merge NetSilicon NS93xx treeRussell King2007-02-18
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed conflicts: arch/arm/Makefile arch/arm/mm/Kconfig Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | [ARM] 4211/1: Provide a defconfig for ns9xxxUwe Kleine-König2007-02-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a follow up for the patch providing the base support for the ns9xxx machine type. Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | [ARM] 4210/1: base for new machine type "NetSilicon NS9360"Uwe Kleine-König2007-02-17
| | |/ / | | | | | | | | | | | | | | | | Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | [ARM] 4058/2: iop32x: set ->broken_parity_status on n2100 onboard r8169 portsLennert Buytenhek2007-02-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the n2100, both onboard r8169 ports exhibit PCI parity problems. Set the ->broken_parity_status flag for both ports so that the r8169 drivers knows it should ignore error interrupts. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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| *---------. \ \ Merge AT91, EP93xx, General devel, PXA, S3C, V6+ and Xscale treesRussell King2007-02-17
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| | | | | | | * | | [ARM] 4123/1: xsc3: general cleanupLennert Buytenhek2007-02-08
| | | | | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up proc-xsc3: - Correct a number of typos. - Fix up indentation in a number of places. - Change references to the various caches to be more clear about whether we're talking about the L1 D, the L1 I or the unified L2 cache. - Rename "drain write buffer" to "data write barrier", the official name used in the Manzano manual. - Change the xsc3 cpu name from "XScale-Core3" to "XScale-V3 based processor". Also, since a previously merged patch implements proper support for using a MAC or iWMMXt coprocessor on xsc3 platforms, we no longer need to enable access to CP0 on boot. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | [ARM] 4201/1: SMP barriers pair needed for the secondary boot processCatalin Marinas2007-02-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some situations, the pen_release store in platform_secondary_init() may stay forever in the write buffer while the CPU is waiting on the boot_lock to be released in boot_secondary(). The primary CPU could never see the pen_release update without the barriers. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | [ARM] 4130/1: Add L220 support to RealView/EBCatalin Marinas2007-02-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the L220 on the RealView/EB MPCore platform. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | Merge Realview GIC codeRussell King2007-02-15
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| | | | | | | * | | [ARM] 4109/2: Add support for the RealView/EB MPCore revC platformCatalin Marinas2007-02-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel originally supported revB only. This patch enables revC by default and adds a config option for building the kernel for the revB platform. Since the SCU base address was hard-coded in the proc-v6.S file (and only valid for RealView/EB revB), this patch also adds a more generic support for defining the SCU information. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | * | | [ARM] 4190/2: Add the secondary GIC support for the RealView/EBCatalin Marinas2007-02-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPCore platform This patch adds the registration of the secondary GIC on the baseboard, together with the IRQ chaining setup. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | * | | [ARM] 4108/2: Allow multiple GIC interrupt controllers in a systemCatalin Marinas2007-02-15
| | | | | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation only assumes one GIC to be present in the system. However, there are platforms with more than one cascaded interrupt controllers (RealView/EB MPCore for example). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | [ARM] 4135/1: Add support for the L210/L220 cache controllersCatalin Marinas2007-02-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the support for the L210/L220 (outer) cache controller. The cache range operations are done by index/way since L2 cache controller only accepts physical addresses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | [ARM] Always mark ARMv6 PTWs outer cacheableRussell King2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other platforms other than SMP may have an outer cache. For these, we also need to mark the page table walks outer cacheable. Since marking the walks always outer cacheable apparantly has no side effects, we might as well always mark them so. However, we continue to only mark PTWs shared if we have SMP enabled. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | [ARM] 4153/1: fix consistent_sync() off-by-one BUG checkLennert Buytenhek2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In consistent_sync(), start + size can end up pointing one byte beyond the end of the direct RAM mapping. We shouldn't BUG() when this happens. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | [ARM] Convert DMA cache handling to take const void * argsRussell King2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA cache handling functions take virtual addresses, but in the form of unsigned long arguments. This leads to a little confusion about what exactly they take. So, convert them to take const void * instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | [ARM] 4134/1: Add generic support for outer cachesCatalin Marinas2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The outer cache can be L2 as on RealView/EB MPCore platform or even L3 or further on ARMv7 cores. This patch adds the generic support for flushing the outer cache in the DMA operations. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | [ARM] Don't call consistent_sync() for DMA coherent memoryRussell King2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory allocated by the coherent memory allocators will be marked uncacheable, which means it's pointless calling consistent_sync() to perform cache maintainence on this memory; it's just a waste of CPU cycles. Moreover, with the (subsequent) merge of outer cache support, it actually breaks things to call consistent_sync() on anything but direct-mapped memory. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | [ARM] 4129/1: Add barriers after the TLB operationsCatalin Marinas2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The architecture specification states that TLB operations are guaranteed to be complete only after the execution of a DSB (Data Synchronisation Barrier, former Data Write Barrier or Drain Write Buffer). The branch target cache invalidation is also needed. The ISB (Instruction Synchronisation Barrier, formerly Prefetch Flush) is needed unless there will be a return from exception before the corresponding mapping is used (i.e. user mappings). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | [ARM] 4128/1: Architecture compliant TTBR changing sequenceCatalin Marinas2007-02-08
| | | | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On newer architectures (ARMv6, ARMv7), the depth of the prefetch and branch prediction is implementation defined and there is a small risk of wrong ASID tagging when changing TTBR0 before setting the new context id. The recommended solution is to set a reserved ASID during TTBR changing. This patch reserves ASID 0. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | [ARM] 4222/1: S3C2443: Remove reference to missing S3C2443_PMBen Dooks2007-02-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | S3C2443_PM is not defined in our Kconfig, so remove the reference from CPU_S3C2443 to stop the configuration process warning about it. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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