aboutsummaryrefslogtreecommitdiffstats
path: root/arch
Commit message (Collapse)AuthorAge
* Merge tag 'arm64-for-linus' of ↵Linus Torvalds2012-12-12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64 Pull ARM64 updates from Catalin Marinas: - Generic execve, kernel_thread, fork/vfork/clone. - Preparatory patches for KVM support (initialising EL2 mode for later installing KVM support, hypervisor stub). - Signal handling corner case fix (alternative signal stack set up for a SEGV handler, which is raised in response to RLIMIT_STACK being reached). - Sub-nanosecond timer error fix. * tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: (30 commits) arm64: Update the MAINTAINERS entry arm64: compat for clock_adjtime(2) is miswired arm64: move FP-SIMD save/restore code to a macro arm64: hyp: initialize vttbr_el2 to zero arm64: add hypervisor stub arm64: record boot mode when entering the kernel arm64: move vector entry macro to assembler.h arm64: add AArch32 execution modes to ptrace.h arm64: expand register mapping between AArch32 and AArch64 arm64: generic timer: use virtual counter instead of physical at EL0 arm64: vdso: defer shifting of nanosecond component of timespec arm64: vdso: rework __do_get_tspec register allocation and return shift arm64: vdso: check sequence counter even for coarse realtime operations arm64: vdso: fix clocksource mask when extracting bottom 56 bits ARM64: Remove incorrect Kconfig symbol HAVE_SPARSE_IRQ Documentation: Fixes a word in Documentation/arm64/memory.txt arm64: Make !dirty ptes read-only arm64: Convert empty flush_cache_{mm,page} functions to static inline arm64: signal: let the compiler inline compat_get_sigframe arm64: signal: return struct rt_sigframe from get_sigframe ... Conflicts: arch/arm64/include/asm/unistd32.h
| * arm64: compat for clock_adjtime(2) is miswiredAl Viro2012-12-05
| | | | | | | | | | | | | | | | | | | | struct timex is different on arm and arm64; adjtimex(2) takes care to convert, clock_adjtime(2) doesn't... Signed-off-by: Al Viro <viro@ZenIV.linux.org.uk> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@vger.kernel.org>
| * arm64: move FP-SIMD save/restore code to a macroMarc Zyngier2012-12-05
| | | | | | | | | | | | | | | | In order to be able to reuse the save-restore code in KVM, move it to a pair of macros, similar to what the 32bit code does. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: hyp: initialize vttbr_el2 to zeroMarc Zyngier2012-12-05
| | | | | | | | | | | | | | | | The architecture doesn't mandate any reset value for vttbr_el2. Better set it to a known value before some HYP code gets confused. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: add hypervisor stubMarc Zyngier2012-12-05
| | | | | | | | | | | | | | | | | | | | | | | | If booted in EL2, install an dummy hypervisor whose only purpose is to be replaced by a full fledged one. A minimal API allows to: - obtain the current HYP vectors (__hyp_get_vectors) - set new HYP vectors (__hyp_set_vectors) Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: record boot mode when entering the kernelMarc Zyngier2012-12-05
| | | | | | | | | | | | | | | | | | | | | | To be able to signal the availability of EL2 to other parts of the kernel, record the boot mode. Once booted, two predicates indicate if HYP mode is available, and if not, whether this is due to a boot mode mismatch or not. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: move vector entry macro to assembler.hMarc Zyngier2012-12-05
| | | | | | | | | | | | | | | | | | | | This macro is also useful to other bits defining vectors (hypervisor stub, KVM...). Move it to a common location. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: add AArch32 execution modes to ptrace.hMarc Zyngier2012-12-05
| | | | | | | | | | Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: expand register mapping between AArch32 and AArch64Marc Zyngier2012-12-05
| | | | | | | | | | | | | | | | | | | | | | The general purpose registers in AArch32 are mapped in an architecturally defined manner into the AArch64 registers. It allows the AArch32 registers of an application or a virtual machine to be inspected by the OS or an hypervisor. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: generic timer: use virtual counter instead of physical at EL0Will Deacon2012-12-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to use the virtual counter at EL0, as the physical counter may not track the current clocksource for guests running under a hypervisor. This patch updates the vdso and generic timer driver to use the virtual counter. The kernel EL2 entry code is also updated to ensure that the virtual offset is initialised to zero. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: vdso: defer shifting of nanosecond component of timespecWill Deacon2012-12-05
| | | | | | | | | | | | | | | | | | | | | | | | | | Shifting the nanosecond component of the computed timespec early can lead to sub-ns inaccuracies when using the truncated value as input to further arithmetic for things like conversions to monotonic time. This patch defers the timespec shifting until after the final value has been computed. Reported-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: vdso: rework __do_get_tspec register allocation and return shiftWill Deacon2012-12-05
| | | | | | | | | | | | | | | | | | In preparation for sub-ns precision in the vdso timespec maths, change the __do_get_tspec register allocation so that we return the clocksource shift value instead of the unused xtime tspec. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: vdso: check sequence counter even for coarse realtime operationsWill Deacon2012-12-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When returning coarse realtime values from clock_gettime, we must still check the sequence counter to ensure that the kernel does not update the vdso datapage whilst we are loading the coarse timespec as this could potentially result in time appearing to go backwards. This patch delays the coarse realtime check until after we have loaded successfully from the vdso datapage. This does mean that we always load the wtm timespec, but conditionalising the load and adding an extra sequence test is unlikely to buy us anything other than messy code, particularly as the sequence test implies a read barrier. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: vdso: fix clocksource mask when extracting bottom 56 bitsWill Deacon2012-12-05
| | | | | | | | | | | | | | | | | | | | | | | | | | The generic timer clocksource has 56 bits of precision and as such must be masked appropriately after we have read it. The current mask generated by a movn instruction is off by 4 bits, so we accidentally include the top 4 bits in the final value. This patch fixes the broken mask. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * ARM64: Remove incorrect Kconfig symbol HAVE_SPARSE_IRQAlexander Shiyan2012-11-29
| | | | | | | | | | | | | | | | | | | | | | Kernel does not contain symbol HAVE_SPARSE_IRQ. Definition in arch/arm64/Kconfig seems typo because valid symbol is MAY_HAVE_SPARSE_IRQ. In any case SPARSE_IRQ is selected by default and we just remove selecting of this symbol. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: Make !dirty ptes read-onlyCatalin Marinas2012-11-29
| | | | | | | | | | | | | | | | | | The AArch64 Linux port relies on the mm code to wrprotect clean ptes. This however is not the case with newly created ptes and PAGE_SHARED(_EXEC) is writable but !dirty. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@vger.kernel.org>
| * arm64: Convert empty flush_cache_{mm,page} functions to static inlineCatalin Marinas2012-11-23
| | | | | | | | | | | | These functions are empty, just make them static inline in the header. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: signal: let the compiler inline compat_get_sigframeWill Deacon2012-11-23
| | | | | | | | | | | | | | | | There's no reason to mark compat_get_sigframe inline explicitly, so remove the annotation and let the compiler decide what's best. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: signal: return struct rt_sigframe from get_sigframeWill Deacon2012-11-23
| | | | | | | | | | | | | | | | | | We only have one type of frame (rt_sigframe) for arm64, so just return that type directly and dispense with the framesize argument, which is presumably a hangover from code copied from arch/arm/. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: signal: align return types for compat and native setup_returnWill Deacon2012-11-23
| | | | | | | | | | | | | | | | setup_return is a void function, so make compat_setup_return look the same rather then unconditionally return 0. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: signal: push the unwinding prologue on the signal stackWill Deacon2012-11-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To allow debuggers to unwind through signal frames, we create a fake stack unwinding prologue containing the link register and frame pointer of the interrupted context. The signal frame is then offset by 16 bytes to make room for the two saved registers which are pushed onto the frame of the *interrupted* context, rather than placed directly above the signal stack. This doesn't work when an alternative signal stack is set up for a SEGV handler, which is raised in response to RLIMIT_STACK being reached. In this case, we try to push the unwinding prologue onto the full stack and subsequently take a fault which we fail to resolve, causing setup_return to return -EFAULT and handle_signal to force_sigsegv on the current task. This patch fixes the problem by including the unwinding prologue as part of the rt_sigframe definition, which is populated during setup_sigframe, ensuring that it always ends up on the signal stack. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@vger.kernel.org>
| * arm64: Include the clkdev.h generic headerCatalin Marinas2012-11-23
| | | | | | | | | | | | | | | | This patch updates the arm64 asm/Kbuild file to include the clkdev.h generic header. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Viresh Kumar <Viresh.kumar@linaro.org>
| * arm64: Force use of common clk at architecture levelDeepak Saxena2012-11-20
| | | | | | | | | | | | | | | | | | Force all platforms to use the common clk framework to ensure that we do not end up with platform-specific implementations ala ARM32. Signed-off-by: Deepak Saxena <dsaxena@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * Merge branch 'execve' into upstreamCatalin Marinas2012-11-19
| |\ | | | | | | | | | | | | * execve: arm64: get rid of fork/vfork/clone wrappers
| | * Merge remote-tracking branch 'viro/arch-arm64' into execveCatalin Marinas2012-11-19
| | |\ | | | | | | | | | | | | | | | | * viro/arch-arm64: arm64: get rid of fork/vfork/clone wrappers
| | | * Merge commit '6ba1bc826d160fe4f32bcb188687dcca4bdfaf3d' into arch-arm64Al Viro2012-11-16
| | | |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backmerge from mainline commit that introduced a trivial conflict in arch/arm64/kernel/process.c - a bunch of functions removed next to the place where kernel_thread() used to be. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
| | | * | arm64: get rid of fork/vfork/clone wrappersAl Viro2012-10-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [fixes from Catalin Marinas folded] Acked-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
| * | | | Merge branch 'execve' into upstreamCatalin Marinas2012-11-14
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * execve: arm64: Use generic sys_execve() implementation arm64: Use generic kernel_execve() implementation arm64: Use generic kernel_thread() implementation
| | * | | Merge tag 'v3.7-rc5' into execveCatalin Marinas2012-11-13
| | |\ \ \ | | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | Linux 3.7-rc5 Conflicts: arch/arm64/kernel/process.c
| | * | | arm64: Use generic sys_execve() implementationCatalin Marinas2012-10-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch converts the arm64 port to use the generic sys_execve() implementation removing the arm64-specific (compat_)sys_execve_wrapper() functions. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| | * | | arm64: Use generic kernel_execve() implementationCatalin Marinas2012-10-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables CONFIG_GENERIC_KERNEL_EXECVE on arm64 and removes the arm64-specific implementation of kernel_execve(). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| | * | | arm64: Use generic kernel_thread() implementationCatalin Marinas2012-10-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables CONFIG_GENERIC_KERNEL_THREAD on arm64, changes copy_threads to cope with kernel threads creation and adapts ret_from_fork accordingly. The arm64-specific kernel_thread implementation is no longer needed. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | | | arm64: mm: update max_dma32 before calculating size of NORMAL zoneWill Deacon2012-11-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f483a853b0b9 ("arm64: mm: fix booting on systems with no memory below 4GB") sets max_dma32 to the minimum of the maximum pfn and MAX_DMA32_PFN. This value is later used as the base of the NORMAL zone, which is incorrect when MAX_DMA32_PFN is below the minimum pfn (i.e. all memory is above 4GB). This patch fixes the problem by ensuring that max_dma32 is always set to the end of the DMA32 zone. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | | | arm64: Make the user fault reporting more specificCatalin Marinas2012-11-14
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | For user space faults the kernel reports "unhandled page fault" and it gives the ESR value. With this patch the error message looked up in the fault info array to give a better description. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | | | Merge branch 'omap-serial' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds2012-12-12
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM OMAP serial updates from Russell King: "This series is a major reworking of the OMAP serial driver code fixing various bugs in the hardware-assisted flow control, extending up into serial_core for a couple of issues. These fixes have been done as a set of progressive changes and transformations in the hope that no new bugs will be introduced by this series. The problems are many-fold, from the driver not being informed about updated settings, to the driver not knowing what the intentions of the upper layers are. The first four patches tackle the serial_core layer, allowing it to provide the necessary information to drivers, and the remaining patches allow the OMAP serial driver to take advantage of this. This brings hardware assisted RTS/CTS and XON/OFF flow control into a useful state. These patches have been in linux-next for most of the last cycle; indeed they predate the previous merge window. They've also been posted to the OMAP people." * 'omap-serial' of git://git.linaro.org/people/rmk/linux-arm: (21 commits) SERIAL: omap: fix hardware assisted flow control SERIAL: omap: simplify (2) SERIAL: omap: move xon/xoff setting earlier SERIAL: omap: always set TCR SERIAL: omap: simplify SERIAL: omap: don't read back LCR/MCR/EFR SERIAL: omap: serial_omap_configure_xonxoff() contents into set_termios SERIAL: omap: configure xon/xoff before setting modem control lines SERIAL: omap: remove OMAP_UART_SYSC_RESET and OMAP_UART_FIFO_CLR SERIAL: omap: move driver private definitions and structures to driver SERIAL: omap: remove 'irq_pending' bitfield SERIAL: omap: fix MCR TCRTLR bit handling SERIAL: omap: fix set_mctrl() breakage SERIAL: omap: no need to re-read EFR SERIAL: omap: remove setting of EFR SCD bit SERIAL: omap: allow hardware assisted IXANY mode to be disabled SERIAL: omap: allow hardware assisted rts/cts modes to be disabled SERIAL: core: add throttle/unthrottle callbacks for hardware assisted flow control SERIAL: core: add hardware assisted h/w flow control support SERIAL: core: add hardware assisted s/w flow control support ... Conflicts: drivers/tty/serial/omap-serial.c
| * | | | SERIAL: omap: remove OMAP_UART_SYSC_RESET and OMAP_UART_FIFO_CLRRussell King2012-11-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP_UART_SYSC_RESET and OMAP_UART_FIFO_CLR are unused, remove them. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | SERIAL: omap: move driver private definitions and structures to driverRussell King2012-11-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct uart_omap_port and struct uart_omap_dma, and associated definitions are private to the driver, so there's no point them sitting in an include file under arch/arm. Move them into the driver itself. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | Merge branch 'x86-timers-for-linus' of ↵Linus Torvalds2012-12-11
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 timer update from Ingo Molnar: "This tree includes HPET fixes and also implements a calibration-free, TSC match driven APIC timer interrupt mode: 'TSC deadline mode' supported in SandyBridge and later CPUs." * 'x86-timers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86: hpet: Fix inverted return value check in arch_setup_hpet_msi() x86: hpet: Fix masking of MSI interrupts x86: apic: Use tsc deadline for oneshot when available
| * | | | | x86: hpet: Fix inverted return value check in arch_setup_hpet_msi()Jan Beulich2012-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | setup_hpet_msi_remapped() returns a negative error indicator on error - check for this rather than for a boolean false indication, and pass on that error code rather than a meaningless "-1". Signed-off-by: Jan Beulich <jbeulich@suse.com> Cc: David Woodhouse <dwmw2@infradead.org> Link: http://lkml.kernel.org/r/5093E00D02000078000A60E2@nat28.tlf.novell.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | | | | x86: hpet: Fix masking of MSI interruptsJan Beulich2012-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HPET_TN_FSB is not a proper mask bit; it merely toggles between MSI and legacy interrupt delivery. The proper mask bit is HPET_TN_ENABLE, so use both bits when (un)masking the interrupt. Signed-off-by: Jan Beulich <jbeulich@suse.com> Cc: stable@vger.kernel.org Link: http://lkml.kernel.org/r/5093E09002000078000A60E6@nat28.tlf.novell.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | | | | x86: apic: Use tsc deadline for oneshot when availableSuresh Siddha2012-11-02
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the TSC deadline mode is supported, LAPIC timer one-shot mode can be implemented using IA32_TSC_DEADLINE MSR. An interrupt will be generated when the TSC value equals or exceeds the value in the IA32_TSC_DEADLINE MSR. This enables us to skip the APIC calibration during boot. Also, in xapic mode, this enables us to skip the uncached apic access to re-arm the APIC timer. As this timer ticks at the high frequency TSC rate, we use the TSC_DIVISOR (32) to work with the 32-bit restrictions in the clockevent API's to avoid 64-bit divides etc (frequency is u32 and "unsigned long" in the set_next_event(), max_delta limits the next event to 32-bit for 32-bit kernel). Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: venki@google.com Cc: len.brown@intel.com Link: http://lkml.kernel.org/r/1350941878.6017.31.camel@sbsiddha-desk.sc.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | | | | Merge branch 'x86-nuke386-for-linus' of ↵Linus Torvalds2012-12-11
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull "Nuke 386-DX/SX support" from Ingo Molnar: "This tree removes ancient-386-CPUs support and thus zaps quite a bit of complexity: 24 files changed, 56 insertions(+), 425 deletions(-) ... which complexity has plagued us with extra work whenever we wanted to change SMP primitives, for years. Unfortunately there's a nostalgic cost: your old original 386 DX33 system from early 1991 won't be able to boot modern Linux kernels anymore. Sniff." I'm not sentimental. Good riddance. * 'x86-nuke386-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86, 386 removal: Document Nx586 as a 386 and thus unsupported x86, cleanups: Simplify sync_core() in the case of no CPUID x86, 386 removal: Remove CONFIG_X86_POPAD_OK x86, 386 removal: Remove CONFIG_X86_WP_WORKS_OK x86, 386 removal: Remove CONFIG_INVLPG x86, 386 removal: Remove CONFIG_BSWAP x86, 386 removal: Remove CONFIG_XADD x86, 386 removal: Remove CONFIG_CMPXCHG x86, 386 removal: Remove CONFIG_M386 from Kconfig
| * | | | | x86, 386 removal: Document Nx586 as a 386 and thus unsupportedH. Peter Anvin2012-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per Alan Cox, Nx586 did not support WP in supervisor mode, making it a 386 by Linux kernel standards. As such, it is too unsupported now. Reported-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Link: http://lkml.kernel.org/r/20121128205203.05868eab@pyramind.ukuu.org.uk Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
| * | | | | x86, cleanups: Simplify sync_core() in the case of no CPUIDH. Peter Anvin2012-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the implementation of sync_core() for the case where we may not have the CPUID instruction available. [ v2: stylistic cleanup of the #else clause per suggestion by Borislav Petkov. ] Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Link: http://lkml.kernel.org/r/1354132230-21854-9-git-send-email-hpa@linux.intel.com Cc: Borislav Petkov <bp@alien8.de>
| * | | | | x86, 386 removal: Remove CONFIG_X86_POPAD_OKH. Peter Anvin2012-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The check_popad() routine tested for a 386-specific bug, and never actually did anything useful with it anyway other than print a message. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Link: http://lkml.kernel.org/r/1354132230-21854-8-git-send-email-hpa@linux.intel.com
| * | | | | x86, 386 removal: Remove CONFIG_X86_WP_WORKS_OKH. Peter Anvin2012-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All 486+ CPUs support WP in supervisor mode, so remove the fallback 386 support code. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Link: http://lkml.kernel.org/r/1354132230-21854-7-git-send-email-hpa@linux.intel.com
| * | | | | x86, 386 removal: Remove CONFIG_INVLPGH. Peter Anvin2012-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All 486+ CPUs support INVLPG, so remove the fallback 386 support code. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Link: http://lkml.kernel.org/r/1354132230-21854-6-git-send-email-hpa@linux.intel.com
| * | | | | x86, 386 removal: Remove CONFIG_BSWAPH. Peter Anvin2012-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All 486+ CPUs support BSWAP, so remove the fallback 386 support code. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Link: http://lkml.kernel.org/r/1354132230-21854-5-git-send-email-hpa@linux.intel.com
| * | | | | x86, 386 removal: Remove CONFIG_XADDH. Peter Anvin2012-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All 486+ CPUs support XADD, so remove the fallback 386 support code. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Link: http://lkml.kernel.org/r/1354132230-21854-4-git-send-email-hpa@linux.intel.com
| * | | | | x86, 386 removal: Remove CONFIG_CMPXCHGH. Peter Anvin2012-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All 486+ CPUs support CMPXCHG, so remove the fallback 386 support code. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Link: http://lkml.kernel.org/r/1354132230-21854-3-git-send-email-hpa@linux.intel.com
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 05:11:26 -0500