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* sparc64: Add CAMELLIA driver making use of the new camellia opcodes.David S. Miller2012-08-28
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Fix spelling of CAMELLIA in CFR macro name and comment.David S. Miller2012-08-28
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Add DES driver making use of the new des opcodes.David S. Miller2012-08-26
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Add CRC32C driver making use of the new crc32c opcode.David S. Miller2012-08-22
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Add AES driver making use of the new aes opcodes.David S. Miller2012-08-22
| | | | | Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
* sparc64: Add MD5 driver making use of the 'md5' instruction.David S. Miller2012-08-20
| | | | | Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
* sparc64: Add SHA384/SHA512 driver making use of the 'sha512' instruction.David S. Miller2012-08-20
| | | | | Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
* sparc64: Add SHA224/SHA256 driver making use of the 'sha256' instruction.David S. Miller2012-08-20
| | | | | Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
* sparc64: Add SHA1 driver making use of the 'sha1' instruction.David S. Miller2012-08-20
| | | | | Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
* sparc64: Update generic comments in perf event code to match reality.David S. Miller2012-08-19
| | | | | | | | | Describe how we support two types of PMU setups, one with a single control register and two counters stored in a single register, and another with one control register per counter and each counter living in it's own register. Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Add SPARC-T4 perf event support.David S. Miller2012-08-19
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Support perf event encoding for multi-PCR PMUs.David S. Miller2012-08-19
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Make sparc_pmu_{enable,disable}_event() multi-pcr aware.David S. Miller2012-08-19
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Rework sparc_pmu_enable() so that the side effects are clearer.David S. Miller2012-08-19
| | | | | | | | | When cpuc->n_events is zero, we actually don't do anything and we just write the cpuc->pcr[0] value as-is without any modifications. The "pcr = 0;" assignment there was just useless and confusing. Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Prepare perf event layer for handling multiple PCR registers.David S. Miller2012-08-19
| | | | | | | | | Make the per-cpu pcr save area an array instead of one u64. Describe how many PCR and PIC registers the chip has in the sparc_pmu descriptor. Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Specify user and supervisor trace PCR bits in sparc_pmu.David S. Miller2012-08-19
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Abstract PMC read/write behind sparc_pmu.David S. Miller2012-08-19
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Allow max hw perf events to be variable.David S. Miller2012-08-19
| | | | | | Now specified in sparc_pmu descriptor. Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Add perf_event abstractions for orthogonal PMUs.David S. Miller2012-08-19
| | | | | | | | | | | Starting with SPARC-T4 we have a seperate PCR control register for each performance counter, and there are absolutely no restrictions on what events can run on which counters. Add flags that we can use to elide the conflict and dependency logic used to handle older chips. Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Add PCR ops for SPARC-T4.David S. Miller2012-08-19
| | | | | | | This is enough to get the NMIs working, more work is needed for perf events. Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Abstract away the %pcr values used to enable/disable NMIDavid S. Miller2012-08-19
| | | | | | | | | | We assumed PCR_PIC_PRIV can always be used to disable it, but that won't be true for SPARC-T4. This allows us also to get rid of some messy defines used in only one location. Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Abstract away the NMI PIC counter computation.David S. Miller2012-08-19
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Abstract away PIC register accesses.David S. Miller2012-08-19
| | | | | | | | | | And, like for the PCR, allow indexing of different PIC register numbers. This also removes all of the non-__KERNEL__ bits from asm/perfctr.h, nothing kernel side should include it any more. Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Add 'reg_num' argument to pcr_ops methods.David S. Miller2012-08-19
| | | | | | | SPARC-T4 and later have multiple PCR registers, one for each PIC counter. Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Add hypervisor interfaces for SPARC-T4 perf counter access.David S. Miller2012-08-19
| | | | | | | | Unlike for previous chips, access to the perf-counter control registers are all hyper-privileged. Therefore, access to them must go through a hypervisor interface. Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc64: Add detection for features new in SPARC-T4.David S. Miller2012-08-19
| | | | | | | | | | | | | | | | Compare and branch, pause, and the various new cryptographic opcodes. We advertise the crypto opcodes to userspace using one hwcap bit, HWCAP_SPARC_CRYPTO. This essentially indicates that the %cfr register can be interrograted and used to determine exactly which crypto opcodes are available on the current cpu. We use the %cfr register to report all of the crypto opcodes available in the bootup CPU caps log message, and via /proc/cpuinfo. Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds2012-08-18
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM fixes from Russell King: "The largest thing in this set of changes is bringing back some of the ARMv3 code to fix a compile problem noticed on RiscPC, which we still support, even though we only support ARMv4 there. (The reason is that the system bus doesn't support ARMv4 half-word accesses, so we need the ARMv3 library code for this platform.) The rest are all quite minor fixes." * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7490/1: Drop duplicate select for GENERIC_IRQ_PROBE ARM: Bring back ARMv3 IO and user access code ARM: 7489/1: errata: fix workaround for erratum #720789 on UP systems ARM: 7488/1: mm: use 5 bits for swapfile type encoding ARM: 7487/1: mm: avoid setting nG bit for user mappings that aren't present ARM: 7486/1: sched_clock: update epoch_cyc on resume ARM: 7484/1: Don't enable GENERIC_LOCKBREAK with ticket spinlocks ARM: 7483/1: vfp: only advertise VFPv4 in hwcaps if CONFIG_VFPv3 is enabled ARM: 7482/1: topology: fix section mismatch warning for init_cpu_topology
| * ARM: 7490/1: Drop duplicate select for GENERIC_IRQ_PROBEStephen Boyd2012-08-15
| | | | | | | | | | | | | | | | Seems that Thomas' and my patches collided during the last merge window. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: Bring back ARMv3 IO and user access codeRussell King2012-08-13
| | | | | | | | | | | | | | | | | | | | | | | | This partially reverts 357c9c1f07d4546bc3fbc0fd1044d96b114d14ed (ARM: Remove support for ARMv3 ARM610 and ARM710 CPUs). Although we only support StrongARM on the RiscPC, we need to keep the ARMv3 user access code for this platform because the bus does not understand half-word load/stores. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7489/1: errata: fix workaround for erratum #720789 on UP systemsWill Deacon2012-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 5a783cbc4836 ("ARM: 7478/1: errata: extend workaround for erratum #720789") added workarounds for erratum #720789 to the range TLB invalidation functions with the observation that the erratum only affects SMP platforms. However, when running an SMP_ON_UP kernel on a uniprocessor platform we must take care to preserve the ASID as the workaround is not required. This patch ensures that we don't set the ASID to 0 when flushing the TLB on such a system, preserving the original behaviour with the workaround disabled. Cc: <stable@vger.kernel.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7488/1: mm: use 5 bits for swapfile type encodingWill Deacon2012-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Page migration encodes the pfn in the offset field of a swp_entry_t. For LPAE, we support physical addresses of up to 36 bits (due to sparsemem limitations with the size of page flags), requiring 24 bits to represent a pfn. A further 3 bits are used to encode a swp_entry into a pte, leaving 5 bits for the type field. Furthermore, the core code defines MAX_SWAPFILES_SHIFT as 5, so the additional type bit does not get used. This patch reduces the width of the type field to 5 bits, allowing us to create up to 31 swapfiles of 64GB each. Cc: <stable@vger.kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7487/1: mm: avoid setting nG bit for user mappings that aren't presentWill Deacon2012-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Swap entries are encoding in ptes such that !pte_present(pte) and pte_file(pte). The remaining bits of the descriptor are used to identify the swapfile and offset within it to the swap entry. When writing such a pte for a user virtual address, set_pte_at unconditionally sets the nG bit, which (in the case of LPAE) will corrupt the swapfile offset and lead to a BUG: [ 140.494067] swap_free: Unused swap offset entry 000763b4 [ 140.509989] BUG: Bad page map in process rs:main Q:Reg pte:0ec76800 pmd:8f92e003 This patch fixes the problem by only setting the nG bit for user mappings that are actually present. Cc: <stable@vger.kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7486/1: sched_clock: update epoch_cyc on resumeColin Cross2012-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many clocks that are used to provide sched_clock will reset during suspend. If read_sched_clock returns 0 after suspend, sched_clock will appear to jump forward. This patch resets cd.epoch_cyc to the current value of read_sched_clock during resume, which causes sched_clock() just after suspend to return the same value as sched_clock() just before suspend. In addition, during the window where epoch_ns has been updated before suspend, but epoch_cyc has not been updated after suspend, it is unknown whether the clock has reset or not, and sched_clock() could return a bogus value. Add a suspended flag, and return the pre-suspend epoch_ns value during this period. The new behavior is triggered by calling setup_sched_clock_needs_suspend instead of setup_sched_clock. Signed-off-by: Colin Cross <ccross@android.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7484/1: Don't enable GENERIC_LOCKBREAK with ticket spinlocksStephen Boyd2012-08-11
| | | | | | | | | | | | | | | | | | | | | | | | Now that ARM has implemented its spinlocks with tickets we don't need to use the generic lockbreak algorithm. Remove the Kconfig from ARM so that we use the arch_spin_is_contended() definition from the asm header. This also saves a word in each lock because we don't need the break_lock member anymore. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7483/1: vfp: only advertise VFPv4 in hwcaps if CONFIG_VFPv3 is enabledWill Deacon2012-08-11
| | | | | | | | | | | | | | | | | | VFPv4 support depends on the VFPv3 context save/restore code, so only advertise support in the hwcaps if the kernel can actually handle it. Cc: <stable@vger.kernel.org> # 3.1+ Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7482/1: topology: fix section mismatch warning for init_cpu_topologyVenkatraman Sathiyamoorthy2012-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of this warning.. arch/arm/kernel/built-in.o(.text+0xac78): Section mismatch in reference from the function init_cpu_topology() to the function .init.text:parse_dt_topology() The function init_cpu_topology() references the function __init parse_dt_topology(). This is often because init_cpu_topology lacks a __init annotation or the annotation of parse_dt_topology is wrong. Signed-off-by: Venkatraman S <svenkatr@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreamingLinus Torvalds2012-08-17
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull C6X atomic64 support from Mark Salter: "Enable atomic64 ops in C6X - define L1_CACHE_SHIFT - select GENERIC_ATOMIC64" * tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming: C6X: select GENERIC_ATOMIC64 C6X: add Lx_CACHE_SHIFT defines
| * | C6X: select GENERIC_ATOMIC64Mark Salter2012-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic atomic64 support came in 2009 to support the perf subsystem with the expectation that all architectures would implement atomic64 support. Since then, other optional parts of the generic kernel have also come to expect atomic64 support. This patch enables generic atomic64 support for C6X architecture. Signed-off-by: Mark Salter <msalter@redhat.com>
| * | C6X: add Lx_CACHE_SHIFT definesMark Salter2012-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | C6X currently lacks Lx_CACHE_SHIFT defines which are needed in a few places in the generic kernel. This patch adds _SHIFT defines for the various caches and bases the Lx_CACHE_BYTES defines on them. Signed-off-by: Mark Salter <msalter@redhat.com>
* | | Merge tag 'stable/for-linus-3.6-rc1-tag' of ↵Linus Torvalds2012-08-16
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen Pull Xen fix from Konrad Rzeszutek Wilk: "Way back in v3.5 we added a mechanism to populate back pages that were released (they overlapped with MMIO regions), but neglected to reserve the proper amount of virtual space for extend_brk to work properly. Coincidentally some other commit aligned the _brk space to larger area so I didn't trigger this until it was run on a machine with more than 2GB of MMIO space." * On machines with large MMIO/PCI E820 spaces we fail to boot b/c we failed to pre-allocate large enough virtual space for extend_brk. * tag 'stable/for-linus-3.6-rc1-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen: xen/p2m: Reserve 8MB of _brk space for P2M leafs when populating back.
| * | | xen/p2m: Reserve 8MB of _brk space for P2M leafs when populating back.Konrad Rzeszutek Wilk2012-08-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we release pages back during bootup: Freeing 9d-100 pfn range: 99 pages freed Freeing 9cf36-9d0d2 pfn range: 412 pages freed Freeing 9f6bd-9f6bf pfn range: 2 pages freed Freeing 9f714-9f7bf pfn range: 171 pages freed Freeing 9f7e0-9f7ff pfn range: 31 pages freed Freeing 9f800-100000 pfn range: 395264 pages freed Released 395979 pages of unused memory We then try to populate those pages back. In the P2M tree however the space for those leafs must be reserved - as such we use extend_brk. We reserve 8MB of _brk space, which means we can fit over 1048576 PFNs - which is more than we should ever need. Without this, on certain compilation of the kernel we would hit: (XEN) domain_crash_sync called from entry.S (XEN) CPU: 0 (XEN) RIP: e033:[<ffffffff818aad3b>] (XEN) RFLAGS: 0000000000000206 EM: 1 CONTEXT: pv guest (XEN) rax: ffffffff81a7c000 rbx: 000000000000003d rcx: 0000000000001000 (XEN) rdx: ffffffff81a7b000 rsi: 0000000000001000 rdi: 0000000000001000 (XEN) rbp: ffffffff81801cd8 rsp: ffffffff81801c98 r8: 0000000000100000 (XEN) r9: ffffffff81a7a000 r10: 0000000000000001 r11: 0000000000000003 (XEN) r12: 0000000000000004 r13: 0000000000000004 r14: 000000000000003d (XEN) r15: 00000000000001e8 cr0: 000000008005003b cr4: 00000000000006f0 (XEN) cr3: 0000000125803000 cr2: 0000000000000000 (XEN) ds: 0000 es: 0000 fs: 0000 gs: 0000 ss: e02b cs: e033 (XEN) Guest stack trace from rsp=ffffffff81801c98: .. which is extend_brk hitting a BUG_ON. Interestingly enough, most of the time we are not going to hit this b/c the _brk space is quite large (v3.5): ffffffff81a25000 B __brk_base ffffffff81e43000 B __brk_limit = ~4MB. vs earlier kernels (with this back-ported), the space is smaller: ffffffff81a25000 B __brk_base ffffffff81a7b000 B __brk_limit = 344 kBytes. where we would certainly hit this and hit extend_brk. Note that git commit c3d93f880197953f86ab90d9da4744e926b38e33 (xen: populate correct number of pages when across mem boundary (v2)) exposed this bug). [v1: Made it 8MB of _brk space instead of 4MB per Jan's suggestion] CC: stable@vger.kernel.org #only for 3.5 Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
* | | | Merge tag 'sh-for-linus' of git://github.com/pmundt/linux-shLinus Torvalds2012-08-16
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull SuperH fixes from Paul Mundt. * tag 'sh-for-linus' of git://github.com/pmundt/linux-sh: sh: intc: Handle domain association for sparseirq pre-allocated vectors. sh: sh7269: Fix LCD pinmux sh: dma: fix request_irq usage
| * \ \ \ Merge branches 'sh/urgent' and 'sh/gpiolib' into sh-latestPaul Mundt2012-08-09
| |\ \ \ \
| | * | | | sh: sh7269: Fix LCD pinmuxPhil Edworthy2012-08-09
| | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two ports that can output the LCD data, therefore they have to use separate pimux identifiers so we can select the one we want to use. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * / | | sh: dma: fix request_irq usageMike Frysinger2012-08-09
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When calling request_irq with IRQF_SHARED, the dev cookie must be set (i.e. non-NULL), otherwise the code rejects it immediately with -EINVAL. So restore the logic here where we'd pass a pointer to the name as a dummy unique val. Otherwise, booting up on my LANDISK system would fail with: DMAC Address Error0 request_irq fail This was introduced in commit 7f47c7189b3e8f19a589f77a3ad169d7b691b582. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | | | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparcLinus Torvalds2012-08-15
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull two sparc fixes from David S. Miller. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc: sparc64: Be less verbose during vmemmap population. sparc64: do not clobber personality flags in sys_sparc64_personality()
| * | | | sparc64: Be less verbose during vmemmap population.David S. Miller2012-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a 2-node machine with 256GB of ram we get 512 lines of console output, which is just too much. This mimicks Yinghai Lu's x86 commit c2b91e2eec9678dbda274e906cc32ea8f711da3b (x86_64/mm: check and print vmemmap allocation continuous) except that we aren't ever going to get contiguous block pointers in between calls so just print when the virtual address or node changes. This decreases the output by an order of 16. Also demote this to KERN_DEBUG. Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | sparc64: do not clobber personality flags in sys_sparc64_personality()Jiri Kosina2012-08-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are multiple errors in how sys_sparc64_personality() handles personality flags stored in top three bytes. - directly comparing current->personality against PER_LINUX32 doesn't work in cases when any of the personality flags stored in the top three bytes are used. - directly forcefully setting personality to PER_LINUX32 or PER_LINUX discards any flags stored in the top three bytes Fix the first one by properly using personality() macro to compare only PER_MASK bytes. Fix the second one by setting only the bits that should be set, instead of overwriting the whole value. Signed-off-by: Jiri Kosina <jkosina@suse.cz> Signed-off-by: David S. Miller <davem@davemloft.net>
* | | | | Merge branch 'for-linus' of ↵Linus Torvalds2012-08-14
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux Pull s390 patches from Martin Schwidefsky: "Included are bug fixes and a patch to enable system call filtering with BPF." * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: s390/compat: fix mmap compat system calls s390/compat: fix compat wrappers for process_vm system calls s390: do not clobber personality flags in sys_32_personality() s390/seccomp: add support for system call filtering using BPF s390/sclp_sdias: Add missing break and "fall through" s390/mm: remove MAX_PHYSADDR_BITS define
| * | | | | s390/compat: fix mmap compat system callsHeiko Carstens2012-08-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The native 31 bit and the compat behaviour for the mmap system calls differ: In native 31 bit mode the passed in address for the mmap system call will be unmodified passed to sys_mmap_pgoff(). In compat mode however the passed in address will be modified with compat_ptr() which masks out the most significant bit. The result is that in native 31 bit mode each mmap request (with MAP_FIXED) will fail where the most significat bit is set, while in compat mode it may succeed. This odd behaviour was introduced with d3815898 "[S390] mmap: add missing compat_ptr conversion to both mmap compat syscalls". To restore a consistent behaviour accross native and compat mode this patch functionally reverts the above mentioned commit. Cc: stable@vger.kernel.org Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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