| Commit message (Collapse) | Author | Age |
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Fix IOMUX settings for UART1 and make UART1 functional.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Commit 816ad74 (ARM: i.MX53: Add full iomux support for mx53) renamed some of the pad names.
Make the changes accordingly so that mx53_loco and mx53_cmd can build without errors.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The usbh1 port of the pcm043 does not use ulpi, so put it outside
the corresponding ifdefs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@freescale.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@freescale.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
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Get rid of ## preprocessor construct where it only makes the
code harder to read.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@freescale.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@freescale.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
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This is a very initial pm support and basically does nothing.
With this pm support entry, drivers can start testing their own
pm functions.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Daiane Angolini <daiane.angolini@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Read fec mac address from ocotp and save it into fec_platform_data
mac field for fec driver to use.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Reuse dummy_clk for the imx-keypad device instead of using a dedicated kpp_clk.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This iomux file contains all the available pins that are iomux
capable.
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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There are devices-imx51.h and devices-imx53.h under
arch/arm/mach-mx5 directory. So, had better rename
devices-mx50.h to devices-imx50.h to follow the same
naming convention with imx51 and imx53 part.
Signed-off-by: Jason Liu <r64343@freescale.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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* 'next' of git://git.monstr.eu/linux-2.6-microblaze:
microblaze: Fix asm/pgtable.h
microblaze: Fix missing pagemap.h
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Function ptep_test_and_clear_young have had wrong the first argument.
It is also necessary to add __HAVE macros for ptep_test_and_clear_young and
ptep_get_and_clear functions.
Error log:
In file included from linux/arch/microblaze/include/asm/pgtable.h:570,
from arch/microblaze/mm/pgtable.c:35:
include/asm-generic/pgtable.h:23: error: conflicting types for 'ptep_test_and_clear_young'
linux/arch/microblaze/include/asm/pgtable.h:449: error:
previous definition of 'ptep_test_and_clear_young' was here
include/asm-generic/pgtable.h:73: error: redefinition of 'ptep_get_and_clear'
linux/arch/microblaze/include/asm/pgtable.h:462: error:
previous definition of 'ptep_get_and_clear' was here
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Add missing linux/pagemap.h to solve compilation error.
Error log:
In file included from linux/arch/microblaze/include/asm/tlb.h:17,
from mm/pgtable-generic.c:9:
include/asm-generic/tlb.h: In function 'tlb_flush_mmu':
include/asm-generic/tlb.h:76: error: implicit declaration of function 'release_pages'
include/asm-generic/tlb.h: In function 'tlb_remove_page':
include/asm-generic/tlb.h:105: error: implicit declaration of function 'page_cache_release'
Signed-off-by: Michal Simek <monstr@monstr.eu>
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git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (25 commits)
m68knommu: fix broken setting of irq_chip and handler
m68knommu: switch to using -mcpu= flags for ColdFire targets
m68knommu: arch/m68knommu/Kconfig whitespace cleanup
m68knommu: create optimal separate instruction and data cache for ColdFire
m68knommu: support ColdFire caches that do copyback and write-through
m68knommu: support version 2 ColdFire split cache
m68knommu: make cache push code ColdFire generic
m68knommu: clean up ColdFire cache control code
m68knommu: move inclusion of ColdFire v4 cache registers
m68knommu: merge bit definitions for version 3 ColdFire cache controller
m68knommu: create bit definitions for the version 2 ColdFire cache controller
m68knommu: remove empty __iounmap() it is no used
m68knommu: remove kernel_map() code, it is not used
m68knommu: remove do_page_fault(), it is not used
m68knommu: use user stack pointer hardware on some ColdFire cores
m68knommu: remove command line printing DEBUG
m68knommu: remove fasthandler interrupt code
m68knommu: move UART addressing to part specific includes
m68knommu: fix clock rate value reported for ColdFire 54xx parts
m68knommu: move ColdFire CPU names into their headers
...
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Fix compile error, by using correct loop variable:
arch/m68knommu/platform/68328/ints.c: In function ‘init_IRQ’:
arch/m68knommu/platform/68328/ints.c:182: error: ‘irq’ undeclared (first use in this function)
arch/m68knommu/platform/68328/ints.c:182: error: (Each undeclared identifier is reported only once
arch/m68knommu/platform/68328/ints.c:182: error: for each function it appears in.)
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Gcc has deprecated the use of the following ColdFire cpu options:
-m5206e, -m528x, -m5307 and -m5407. In there place we should use
the equivilent -mcpu= option and setting.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Replace 8 spaces, or even 7, by TAB at begin of lines.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Create separate functions to deal with instruction and data cache flushing.
This way we can optimize them for the vairous cache types and arrangements
used across the ColdFire family.
For example the unified caches in the version 3 cores means we don't
need to flush the instruction cache. For the version 2 cores that do
not do data cacheing (or where we choose instruction cache only) we
don't need to do any data flushing.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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The version 3 and version 4 ColdFire cache controllers support both
write-through and copy-back modes on the data cache. Allow for Kconfig
time configuration of this, and set the cache mode appropriately.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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The newer version 2 ColdFire CPU cores support a configurable cache
arrangement. The cache memory can be used as all instruction cache, all
data cache, or split in half for both instruction and data caching.
Support this setup via a Kconfig time menu that allows a kernel builder
to choose the arrangement they want to use.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Currently the code to push cache lines is only available to version 4
cores. Version 3 cores may also need to use this if we support copy-
back caches on them. Move this code to make it more generic, and
useful for all version ColdFire cores.
With this in place we can now have a single cache_flush_all() code
path that does all the right things on all version cores.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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The cache control code for the ColdFire CPU's is a big ugly mess
of "#ifdef"ery liberally coated with bit constants. Clean it up.
The cache controllers in the various ColdFire parts are actually quite
similar. Just differing in some bit flags and options supported. Using
the header defines now in place it is pretty easy to factor out the
small differences and use common setup and flush/invalidate code.
I have preserved the cache setups as they where in the old code
(except where obviously wrong - like in the case of the 5249). Following
from this it should be easy now to extend the possible setups used on
the CACHE controllers that support split cacheing or copy-back or
write through options.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Move the inclusion of the version 4 cache controller registers so that
it is with all the other register bit flag definitions. This makes it
consistent with the other version core inclusion points, and means we
don't need "#ifdef"ery in odd-ball places for these definitions.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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All version 3 based ColdFire CPU cores have a similar cache controller.
Merge all the exitsing definitions into a single file, and make them
similar in style and naming to the existing version 2 and version 4
cache controller definitions.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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The empty __iounmap() function is not used on m68knommu at all.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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