| Commit message (Collapse) | Author | Age |
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Added dr_mode property in dwc3 and set its default mode to device.
Signed-off-by: George Cherian <george.cherian@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
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smps10 should be enabled only in the case of host mode. So stop
doing always_on, boot_on from smps10_out1. The driver will enable
it in host mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
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Do not reset GPIO1 at boot-up because GPIO 7 in GPIO1 block is used on
OMAP4460 PandaBoard-ES to select voltage register in TPS62361 which
supplies VDD_MPU.
Without this, OMAP4460 PandaBoard-ES boards fail to boot-up because
MPU voltage switches over to VSET0 voltage value (boot voltage) which
is not sufficient to operate the device at OPP100.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
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Do not reset GPIO0 at boot-up because GPIO0 is used
on AM335x EVM-SK to control VTT regulators on DDR3.
Without this EVM-SK boards fail to boot-up because
of DDR3 corruption.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
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On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches to
PMIC, and SoC internal Bus IPs, some or most of which
should either not be reset or idled or both at init.
(In some cases there are erratas which prevent an IP
from being reset)
Have a way to pass this information from DT.
Update the am33xx/omap4 and omap5 dtsi files with the
new bindings for modules which either should not be
idled. reset or both. A later patch would cleanup the
same information that exists today as part of the hwmod
data files.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
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The generic PHY framewrok expects different properties than the
old USB PHY framework. Supply those properties.
Fixes USB OTG port on GAT04 and N900 after the Generic PHY framework was
merged in greg/usb-next. [1]
[1] - https://lkml.org/lkml/2013/9/27/581
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
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The arm arch timers frequency are now programmed in the CNTFREQ
per-cpu register by the timer code using the secure API [1].
So remove the redundant entry from the dts.
[1] http://marc.info/?l=linux-omap&m=138139106312786&w=2
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
From Tony Lindgren:
Few patches to make cpufreq work for omap3 with device tree.
Note that this branch has a dependency to the patches merged
with omap-for-v3.13/board-removal-signed-take2.
* tag 'omap-for-v3.13/cpufreq-late' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP3+: use cpu0-cpufreq driver in device tree supported boot
ARM: OMAP2+: add missing lateinit hook for calling pm late init
ARM: OMAP3+: do not register non-dt OPP tables for device tree boot
Signed-off-by: Olof Johansson <olof@lixom.net>
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With OMAP3+ and AM33xx supported SoC having defined CPU device tree
entries with operating-points and clock nodes defined, we can now use
the SoC generic cpufreq-cpu0 driver by registering appropriate device.
Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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AM335x, AM43xx, OMAP5 and DRA7 have missing late init hook. Introduce
SoC specific hook with a call to OMAP2+ generic lateinit hook. This
allows the generic late initializations such as cpufreq hooks to be
active.
Based on out-of-tree patches that need to be introduced in
mainline, this introduction allows us to provide the foundation for
further SoC specific features as they are developed.
Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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OMAP3+ supports both device tree and non-device tree boot.
Device tree bindings for OMAP3+ is supposed to be added via dts following:
Documentation/devicetree/bindings/power/opp.txt
Since we now have device tree entries for OMAP3+ cpu OPPs,
The current code wrongly adds duplicate OPPs. So, dont register OPPs
when booting using device tree.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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From Jason Cooper, mvebu dt changes for v3.13 (round 4):
- mvebu
- core divider clock driver dt binding and nodes
* tag 'dt-3.13-4' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Add the core-divider clock to Armada 370/XP
ARM: mvebu: Add a 2 GHz fixed-clock Armada 370/XP
ARM: mvebu: Add Core Divider clock device-tree binding
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The Armada 370/XP SoC has a clock provider called "Core Divider",
that is derived from a fixed 2 GHz PLL clock.
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Armada 370/XP SoCs have a 2 GHz fixed PLL that is used to feed
other clocks. This commit adds a DT representation of this clock
through a fixed-clock compatible node.
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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into next/dt
From Shawn Guo:
The imx/mxs device tree changes for 3.13:
- Use macros for mxs pinctrl settings
- New board support: VF610 Cosmic/Cosmic+, imx6q-udoo, MSR M28CU3
- Support DSPI device for vf610
- Add PCIe device for imx6qdl
- Add UHS pinctrl states for imx6sl and imx6qdl
- Display support for APF and imx51-babbage boards
- Enable SPI NOR and USB for imx6sl-evk board
- Enable LVDS for imx6q-sabrelite and SPDIF for imx6qdl-wandboard
- Misc updates on boards: TX28, imx6qdl-wandboard, imx53-qsb etc.
- Some random updates on imx51 device tree
* tag 'imx-dt-3.13' of git://git.linaro.org/people/shawnguo/linux-2.6: (44 commits)
ARM: imx: imx6sl iomuxc syscon is compatible to imx6q
ARM: dts: imx6sl-evk: enable the SPI NOR
ARM: dts: imx6sl: add a pinctrl for ECSPI1
ARM: imx27: add missing #pwm-cells property
ARM: dts: imx6sl: add pinctrl uhs states for usdhc
ARM: dts: imx6qdl-sabresd: Add backlight support for lvds
ARM: dts: imx51-babbage: Make DVI and WVGA panel functional
ARM: imx27-apf27dev: Add framebuffer support
ARM: imx51-apf51dev: Add parallel display support
ARM: dts: imx53-qsb: Do not use GPIO1_8 as wakeup source
ARM: dts: imx53-qsb: SDHC1 does not have cd-gpios
ARM: dts: imx53-qsb: SDHC3 is connected in 8-bit mode
ARM: dts: mxs: Add MSR M28CU3 board
ARM: dts: imx6qdl-wandboard: Provide phy-reset-gpios
ARM: dts: imx6qdl-sabresd: Provide phy-reset-gpios
ARM: dts: imx6q-sabrelite: Add ethernet phy reset pin into hog
ARM: dts: imx6qdl: add pcie device node
ARM: dts: imx6q-udoo: Add initial board support
ARM: dts: mxs: Add muxing options for the SSP2 MMC
ARM: dts: add initial VF610 Cosmic/Cosmic+ board support
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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The imx6sl iomuxc syscon is compatible to imx6q, so let's add
compatible string 'fsl,imx6q-iomuxc-gpr' for imx6sl iomuxc syscon node.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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enable the spi nor for imx6sl-evk boards.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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add a pinctrl for ECSPI1. This pinctrl can be used in the imx6sl-evk board.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The pwm-node is missing its #pwm-cells property. The pwm-framework will
complain about this.
Add the missing property.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This is needed for SD3.0 cards working on UHS mode.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This patch adds support for lvds backlight on boards
i.MX6q-SabreSD and i.MX6dl-SabreSD
Signed-off-by: Rogerio Pimentel <rogerio.pimentel@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Currently we get the following errors on imx51-babbage:
/display@di0: could not find display-timings node
/display@di0: no timings specified
/display@di1: could not find display-timings node
/display@di1: no timings specified
imx-drm imx-drm: failed to allocate buffer with size 0
Provide timing values for IPU1, which is connected to a DVI bridge and
to IPU2, which can be connected to the WVGA panel, so that both of them can
be functional.
While at it, disable the WVGA panel, so that DVI output becomes the default one.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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On the mx53qsb board with mc34708 PMIC, GPIO1_8 resets the system, so better not
to use it as a wakeup source.
Use GPIO 2_14 and 2_15 for wakeup sources instead.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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SDHC1 does not have any GPIO for reading the card detection status, so
remove 'cd-gpios'.
After this change card detection works via the internal SD controller mechanism.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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SDHC3 is 8 bit-wide, so pass the bus-width property to reflect that.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This board is based on the M28 SoM with custom baseboard. Supported
are LEDs, ethernet, PWM, LCD, SD slots.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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GPIO3_29 is used to reset the ethernet phy.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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GPIO1_25 is used to reset the ethernet phy.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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MX6QDL_PAD_EIM_D23__GPIO3_IO23 pin is used to reset the ethernet phy.
Add it to the 'hog' group.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Add pcie device node for imx6qdl.
Signed-off-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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For more information about the Udoo board:
http://www.udoo.org/
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Add pinmux for 4-bit SD card connected to SSP2.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Add initial PHYTEC VF610 Cosmic/Cosmic+ board support with
UART and FEC enabled.
Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This pin definition had been added after the initial patch to use
symbolic pin names in DTS files.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Update the Ka-Ro TX28 DTS file.
- add Copyright header
- use label references for better readability
- sort the entries alphabetically
- add some aliases used by U-Boot to modify the DT data
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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For some reason, the select input of pin function USB_OTG_ID is not
implemented via a regular select input register but using the bit
USB_OTG_ID_ SEL (shift 13) of IOMUXC_GPR1 register (offset 0x4).
As per the workaround for such quirk implemented in pinctrl driver,
we need to compose the input_val cell as below.
31 23 15 7 0
| 0xff | shift | width | select |
Thus, we have 0xff0d0100 for MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID and
0xff0d0101 for MX6QDL_PAD_GPIO_1__USB_OTG_ID in input_val cell.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Peter Chen <peter.chen@freescale.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
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Convert mx23/mx28 dts files to use the padconfig defintions from
mxs-pinfunc.h.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Convert mx23/mx28 dts filed to use the pinctrl header files.
NOTE: During automatic conversion of these files to use the pinconfig
definitions an inconsistency has been found in:
arch/arm/boot/dts/imx28-apx4devkit.dts
According to the comment the function for pad SSP2_SS0 should have
been MX28_PAD_SSP2_SS0__GPIO_2_19, while the given value 0x2131
represents: MX28_PAD_SSP2_SS0__AUART3_TX
I used the later (though probably wrong) definition because that's
what is actually being used in the DTB.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Remove the list of possible pin configurations from the documentation
file and create header files containing those definitions.
This eliminates the need for error-prone manual lookup of those values
in the documentation and guarantees consistency between the human
readable representation of the pad function in the .dts file and the
actual binary value used in DT.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Provide 'lradc-touchscreen-wires' property to the LRADC driver, so that
touchscreen can be functional.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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On imx6qdl-sabresd the SDHC2 and SDHC3 are 8 bit-wide, so pass the bus-width
property to reflect that.
Otherwise the mmc driver will operate with the default bus-width value of 4.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This is needed for supporting ultra high speed cards like SD3.0 cards.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Add spi aliases.
While at it, keep the aliases entries sorted.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Enable USB function for OTG 1 and OTG 2 at mx6sololite evk.
Besides, fix the wrong interrupt number for OTG2 and host 1.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Add iomuxc gpr device node for imx6sl.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Nicolin Chen <b42378@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This patch enables DSPI0 and at26df081a flash device for Vybrid VF610
TOWER board.
Signed-off-by: Chao Fu <b44548@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Add Freescale DSPI node into vf610 dts.
Signed-off-by: Chao Fu <b44548@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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