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* [POWERPC] Fix building of pmac32 when CONFIG_NVRAM=mTony Breeds2008-04-29
| | | | | | | | | | | | | | | | | Kamalesh Babulal (kamalesh@linux.vnet.ibm.com) reports that CONFIG_NVRAM=m is valid in terms of Kconfig but fails to build with: Building modules, stage 2. MODPOST 1401 modules ERROR: "pmac_newworld" [arch/powerpc/platforms/powermac/nvram.ko] undefined! ERROR: "__alloc_bootmem" [arch/powerpc/platforms/powermac/nvram.ko] undefined! make[1]: *** [__modpost] Error The arch/powerpc/platforms/powermac/nvram.c code really needs to be builtin, but as its compilation is dependent on a generic Kconfig symbol we force nvram.c to be builtin if CONFIG_NVRAM is 'y' or 'm'. Signed-off-by: Tony Breeds <tony@bakeyournoodle.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Add IRQSTACKS support on ppc32Kumar Gala2008-04-29
| | | | | | | | | | | | | | | | | | | | This makes it possible to use separate stacks for hard and soft IRQs on 32-bit powerpc as well as on 64-bit. The code for 32-bit is just the 32-bit analog of the 64-bit code. * Added allocation and initialization of the irq stacks. We limit the stacks to be in lowmem for ppc32. * Implemented ppc32 versions of call_do_softirq() and call_handle_irq() to switch the stack pointers * Reworked how we do stack overflow detection. We now keep around the limit of the stack in the thread_struct and compare against the limit to see if we've overflowed. We can now use this on ppc64 if desired. [ paulus@samba.org: Fixed bug on 6xx where we need to reload r9 with the thread_info pointer. ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Add fast little-endian switch system callPaul Mackerras2008-04-29
| | | | | | | | | | | | | | | | | | | | | | | | | This adds a system call on 64-bit platforms for switching between little-endian and big-endian modes that is much faster than doing a prctl call. This system call is handled as a special case right at the start of the system call entry code, and because it is a special case, it uses a system call number which is out of the range of normal system calls, namely 0x1ebe. Measurements with lmbench on a 4.2GHz POWER6 showed no measurable change in the speed of normal system calls with this patch. Switching endianness with this new system call takes around 60ns on a 4.2GHz POWER6, compared with around 300ns to switch endian mode with a prctl. This can provide a significant performance advantage for emulators for little-endian architectures that want to switch between big-endian and little-endian mode frequently, e.g. because they are generating instructions sequences on the fly and they want to run those sequences in little-endian mode. The other thing about this system call is that it doesn't clobber as many registers as a normal system call. It only clobbers r12. Signed-off-by: Paul Mackerras <paulus@samba.org>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6Linus Torvalds2008-04-28
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6: (35 commits) siimage: coding style cleanup (take 2) ide-cd: clean up cdrom_analyze_sense_data() ide-cd: fix test unsigned var < 0 ide: add TSSTcorp CDDVDW SH-S202H to ivb_list[] piix: add Asus Eee 701 controller to short cable list ARM: always select HAVE_IDE remove the broken ETRAX_IDE driver ide: remove ->dma_prdtable field from ide_hwif_t ide: remove ->dma_vendor{1,3} fields from ide_hwif_t scc_pata: add ->dma_host_set and ->dma_start methods ide: skip "VLB sync" if host uses MMIO ide: add ide_pad_transfer() helper ide: remove ->INW and ->OUTW methods ide: use IDE I/O helpers directly in ide_tf_{load,read}() ns87415: add ->tf_read method scc_pata: add ->tf_{load,read} methods ide-h8300: add ->tf_{load,read} methods ide-cris: add ->tf_{load,read} methods ide: add ->tf_load and ->tf_read methods ide: move ide_tf_{load,read} to ide-iops.c ...
| * ARM: always select HAVE_IDEAdrian Bunk2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It's plain wrong for PCMCIA to select HAVE_IDE that implies e.g. the availability of an asm/ide.h It turns out this was done for ARM, and we can simply always select HAVE_IDE on ARM instead of manually tracking which platforms might possible have an IDE controller directly or indirectly. Signed-off-by: Adrian Bunk <bunk@kernel.org> Cc: Russell King <rmk+lkml@arm.linux.org.uk> Cc: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
* | x86_64 vDSO: use initdataRoland McGrath2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 64-bit vDSO image is in a special ".vdso" section for no reason I can determine. Furthermore, the location of the vdso_end symbol includes some wrongly-calculated padding space in the image, which is then (correctly) rounded to page size, resulting in an extra page of zeros in the image mapped in to user processes. This changes it to put the vdso.so image into normal initdata as we have always done for the 32-bit vDSO images. The extra padding is gone, so the user VMA is one page instead of two. The image that was already copied around at boot time is now in initdata, so we recover that wasted space after boot. Signed-off-by: Roland McGrath <roland@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | [CPUFREQ] Make acpi-cpufreq more robust against BIOS freq changes behind our ↵Venkatesh Pallipadi2008-04-28
|/ | | | | | | | | | back. We checked the hardware freq with OS cached freq value in get_cur_freqon_cpu(). Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Thomas Renninger <trenn@suse.de> Signed-off-by: Dave Jones <davej@redhat.com>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2008-04-28
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (45 commits) [MIPS] Pb1200/DBAu1200: move platform code to its proper place [MIPS] Fix handling of trap and breakpoint instructions [MIPS] Pb1200: do register SMC 91C111 [MIPS] DBAu1200: fix bad SMC 91C111 resource size [NET] Kconfig: Rename MIKROTIK_RB500 -> MIKROTIK_RB532 [MIPS] IP27: Fix build bug due to missing include [MIPS] Fix some sparse warnings on traps.c and irq-msc01.c [MIPS] cevt-gt641xx: Kill unnecessary include [MIPS] DS1287: Add clockevent driver [MIPS] add DECstation I/O ASIC clocksource [MIPS] rbtx4938: minor cleanup [MIPS] Alchemy: kill unused PCI_IRQ_TABLE_LOOKUP macro [MIPS] rbtx4938: misc cleanups [MIPS] jmr3927: use generic txx9 gpio [MIPS] rbhma4500: use generic txx9 gpio [MIPS] generic txx9 gpio support [MIPS] make fallback gpio.h gpiolib-friendly [MIPS] unexport null_perf_irq() and make it static [MIPS] unexport rtc_mips_set_time() [MIPS] unexport copy_from_user_page() ...
| * [MIPS] Pb1200/DBAu1200: move platform code to its proper placeSergei Shtylyov2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since both the IDE interface and SMC 91C111 Ethernet chip are on-board devices, not SOC devices, move the platform device registration form the common to the board specific code. While at it, remove semicolon (which didn't break compilation only by chance) from the AU1XXX_ATA_DDMA_REQ macro and do some renaming: - change 'au1200_ide0_' variable name prefix to the mere 'ide_'; - change 'smc91x_' variable name prefix to 'smc91c111_' since that's the name of the chip used on the boards; - drop 'AU1XXX_' prefix from the names of macros describing IDE and Ethernet on-board devices; - change 'SMC91111_' to 'SMC91C111_', change 'IRQ' to 'INT' in the names of the macros describing the Ethernet chip for consistency with the IDE macros; - change 'ATA_' to 'IDE_' and 'OFFSET' to 'SHIFT' (since this value is indeed a shift count) in the names of the macros describing the IDE interface. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Fix handling of trap and breakpoint instructionsRalf Baechle2008-04-28
| | | | | | | | | | | | With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Pb1200: do register SMC 91C111Sergei Shtylyov2008-04-28
| | | | | | | | | | | | | | | | Pb1200 does have SMC 91C111 Ethernet chip on board but the platform code did not register it, so one couldn't mount NFS... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] DBAu1200: fix bad SMC 91C111 resource sizeSergei Shtylyov2008-04-28
| | | | | | | | | | | | | | | | The on-board SMC 91C111 chip only decodes 16 bytes of memory (obviously, it can not decode a whole megabyte starting from address 0x19000300). Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Fix some sparse warnings on traps.c and irq-msc01.cAtsushi Nemoto2008-04-28
| | | | | | | | | | | | | | | | | | * Declare board_bind_eic_interrupt, board_watchpoint_handler in traps.h * Make msc_bind_eic_interrupt static and fix its argument types. * Make msc_levelirq_type, msc_edgeirq_type static. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] cevt-gt641xx: Kill unnecessary includeAtsushi Nemoto2008-04-28
| | | | | | | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] DS1287: Add clockevent driverYoichi Yuasa2008-04-28
| | | | | | | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] add DECstation I/O ASIC clocksourceYoichi Yuasa2008-04-28
| | | | | | | | | | | | | | Add DECstation I/O ASIC clocksource Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] rbtx4938: minor cleanupAtsushi Nemoto2008-04-28
| | | | | | | | | | | | | | Do not initialize res->parent for platform device. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] rbtx4938: misc cleanupsAtsushi Nemoto2008-04-28
| | | | | | | | | | | | | | | | | | | | * Do not use non-standard I/O accessors, such as reg_rd08, etc. * Kill unnecessary wbflush() * Kill tx4938_mips.h * Kill unnecessary includes Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] jmr3927: use generic txx9 gpioAtsushi Nemoto2008-04-28
| | | | | | | | | | | | | | Use generic txx9 gpio (and gpiolib) for JMR3927 board. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] rbhma4500: use generic txx9 gpioAtsushi Nemoto2008-04-28
| | | | | | | | | | | | | | Use generic txx9 gpio (and gpiolib) for RBHMA4500 board. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] generic txx9 gpio supportAtsushi Nemoto2008-04-28
| | | | | | | | | | | | | | This is a board-independent TXx9 gpio API implementation using gpiolib. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] unexport null_perf_irq() and make it staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | | | This patch unexports the null_perf_irq() symbol, and simultaneously makes this function static. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] unexport rtc_mips_set_time()Dmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | | | | | No users for the rtc_mips_set_time() routine exist outside of the core kernel code. Therefore, EXPORT_SYMBOL(rtc_mips_set_time) is useless, and this patch removes it. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] unexport copy_from_user_page()Dmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | | | | | No users for the copy_from_user_page() routine exist outside of the core kernel code. Therefore, EXPORT_SYMBOL(copy_from_user_page) is useless, and this patch removes it. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] unexport copy_to_user_page()Dmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | | | | | The copy_to_user_page() function is called only in the core kernel code. Therefore, there is no need to export it. This patch removes EXPORT_SYMBOL(copy_to_user_page). Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] unexport copy_user_highpage()Dmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | | | | | The copy_user_highpage() routine has no users outside of the core kernel code, so exporting this symbol is pointless. This patch removes EXPORT_SYMBOL(copy_user_highpage). Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Alchemy: move UART platform code to its proper placeSergei Shtylyov2008-04-28
| | | | | | | | | | | | | | | | | | Move the code registering the Alchemy UART platform devices from drivers/serial/ to its proper place, into the Alchemy platform code. Fix the related Kconfig entry, while at it... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Alchemy: kill useless #include's, #define's and extern'sSergei Shtylyov2008-04-28
| | | | | | | | | | | | | | | | Go thru the Alchemy code and hunt down every unneeded #include, #define, and extern (some of which refer to already long dead functions). Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] malta_int.c: make 4 variables staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following variables defined in arch/mips/mips-boards/malta/malta_int.c can become static: msc_irqmap[], msc_nr_irqs, msc_eicirqmap[], and msc_nr_eicirqs. This patch makes them static. Successfully build-tested using default configs for Malta, Atlas and SEAD boards. Runtime test successfully performed by booting the Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] make standard_io_resources[] staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The array standard_io_resources[] needs not to be exposed in the kernel global namespace. This patch makes it static. Successfully build-tested using default configs for Malta, Atlas and SEAD boards. Runtime test successfully performed by booting the Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] make plat_perf_setup() staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need for the plat_perf_setup() function to be global, so make it static. Successfully build-tested using default configs for Malta, Atlas and SEAD boards. Runtime test successfully performed by booting the Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] make mdesc and prom_getmdesc() staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Neither the mdesc[] array nor the prom_getmdesc() function need to be global. This patch makes them static. Successfully build-tested using default configs for Malta, Atlas and SEAD boards. Runtime test successfully performed by booting the Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] make mips_ejtag_setup() staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | This change makes the needlessly global function mips_ejtag_setup() static. Successfully build-tested using default configs for Malta, Atlas and SEAD boards. Runtime test successfully performed by booting the Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] make mips_nmi_setup() staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | This change makes the needlessly global function mips_nmi_setup() static. Successfully build-tested using default configs for Malta, Atlas and SEAD boards. Runtime test successfully performed by booting the Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] replace remaining __FUNCTION__ occurrencesHarvey Harrison2008-04-28
| | | | | | | | | | | | | | | | __FUNCTION__ is gcc-specific, use __func__ Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] remove redundant display of free swap space in show_mem()Johannes Weiner2008-04-28
| | | | | | | | | | | | Signed-off-by: Johannes Weiner <hannes@saeurebad.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Alchemy: kill useless time variablesSergei Shtylyov2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | Since the commit 91a2fcc88634663e9e13dcdfad0e4a860e64aeee ([MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers) removed the Alchemy specific timer handler, 'r4k_offset' and 'r4k_cur' variables became practically useless, so get rid of them at last, renaming cal_r4off() function into calc_clock() and making it return CPU frequency. Also, make 'no_au1xxx_32khz' variable static... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Alchemy: don't unmask timer IRQ earlySergei Shtylyov2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defer the unmasking of the count/compare interrupt (IRQ5) till the clockevent driver initialization: - only enable the cascaded IRQs 0 thru 4 in arch_init_irq(); kill the ALLINTS macro -- this change is blessed by AMD as I saw it in their own patch; :-) - do not force IRQ5 enabled in plat_time_init() if PM is enabled and there's no 32 KHz crystal. Update the copyrights (taking into account my prior changes), also removing Pete Popov's old email... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Move arch/mips/philips to arch/mips/nxpDaniel Laird2008-04-28
| | | | | | | | | | Signed-off-by: daniel.j.laird <daniel.j.laird@nxp.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] replace __inline with inlineHarvey Harrison2008-04-28
| | | | | | | | | | Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Add support for MIPS CMP platform.Ralf Baechle2008-04-28
| | | | | | | | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Add CoreFPGA5 support; distinguish between SOCit/ROCitChris Dearman2008-04-28
| | | | | | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Add noulri kernel argument to disable "rdhwr $29" usermode support.Chris Dearman2008-04-28
| | | | | | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Allow setting of the cache attribute at run time.Chris Dearman2008-04-28
| | | | | | | | | | | | | | | | Slightly tacky, but there is a precedent in the sparc archirecture code. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] All MIPS32 processors support64-bit physical addresses.Chris Dearman2008-04-28
| | | | | | | | | | | | | | Still, only the 4K may actually implement it. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Remove TLB sanitation codeChris Dearman2008-04-28
| | | | | | | | | | | | | | It is not being used by Malta and shouldn't be needed for MIPSsim. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Basic SPRAM supportChris Dearman2008-04-28
| | | | | | | | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Reimplement clear_page/copy_pageThiemo Seufer2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fold the SB-1 specific implementation of clear_page/copy_page in the generic version, and rewrite that one in tlbex style. The immediate benefits: - It converts the compile-time workaround for SB-1 pass 1 prefetches to a more efficient run-time check. - It allows adjustment of loop unfolling, which helps to reduce the number of redundant cdex cache ops. - It fixes some esoteric cornercases (the cache line length calculations can go wrong, and support for 64k pages without prefetch instructions will overflow the addiu immediate). - Somewhat better guesses of "good" prefetch values. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | x86: Fix 32-bit MSI-X allocation leakagePJ Waskiewicz2008-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This bug was introduced in the 2.6.24 i386/x86_64 tree merge, where MSI-X vector allocation will eventually fail. The cause is the new bit array tracking used vectors is not getting cleared properly on IRQ destruction on the 32-bit APIC code. This can be seen easily using the ixgbe 10 GbE driver on multi-core systems by simply loading and unloading the driver a few times. Depending on the number of available vectors on the host system, the MSI-X allocation will eventually fail, and the driver will only be able to use legacy interrupts. I am generating the same patch for both stable trees for 2.6.24 and 2.6.25. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | celleb_scc_pciex __iomem annotationsAl Viro2008-04-28
| | | | | | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 03:56:47 -0500