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* [POWERPC] spi: Support non-QE processorsPeter Korsgaard2007-10-08
| | | | | | | On non-QE processors (mpc831x/mpc834x) the SPI clock is the SoC clock. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 85xx: mpc85xx_mds - reset UCC ethernet properlyAnton Vorontsov2007-10-08
| | | | | | | | | | Apart from that the current code doesn't compile it's also meaningless with regard to the MPC8568E-MDS' BCSR. This patch used to reset UCCs properly. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 85xx: mpc8568mds - update dts to be able to use UCCsAnton Vorontsov2007-10-08
| | | | | | | | | | | | 1. UCC1's RX_DV pin is 16, not 15; 2. UCC1's phy is at 0x7, not 0x1. Schematics says 0x7, and recent u-boot also using 0x7. 3. Use gianfar's (eTSEC) mdio bus. This is hardware default setup. 4. tx-clock should be CLK16 (GE125, PB31); 5. phy-connection-type is RGMII-ID; Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] QE: pario - support for MPC85xx layoutAnton Vorontsov2007-10-08
| | | | | | | | 8 bytes padding required to match MPC85xx registers layout. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Reviewed-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] QEIC: Implement pluggable handlers, fix MPIC cascadingAnton Vorontsov2007-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | set_irq_chained_handler overwrites MPIC's handle_irq function (handle_fasteoi_irq) thus MPIC never gets eoi event from the cascaded IRQ. This situation hangs MPIC on MPC8568E. To solve this problem efficiently, QEIC needs pluggable handlers, specific to the underlaying interrupt controller. Patch extends qe_ic_init() function to accept low and high interrupt handlers. To avoid #ifdefs, stack of interrupt handlers specified in the header file and functions are marked 'static inline', thus handlers are compiled-in only if actually used (in the board file). Another option would be to lookup for parent controller and automatically detect handlers (will waste text size because of never used handlers, so this option abolished). qe_ic_init() also changed in regard to support multiplexed high/low lines as found in MPC8568E-MDS, plus qe_ic_cascade_muxed_mpic() handler implemented appropriately. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] mpc85xx_mds: select QUICC_ENGINEAnton Vorontsov2007-10-08
| | | | | Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 85xx/86xx: refactor RSTCR reset codeKumar Gala2007-10-08
| | | | | | | | | On the majority of 85xx & 86xx we have a register that's ability to assert HRESET_REQ to reset the board. We refactored that code so it can be shared between both platforms into fsl_soc.c and removed all the duplication in each platform directory. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Use for_each_ matching routinues for pci PHBsKumar Gala2007-10-08
| | | | | | | | | | | | On the Freescale embedded (83xx, 85xx, 86xx) and a few of the discrete bridges (mpc10x, tsi108) use the new for_each_compatible_node() or for_each_node_by_type() to provide more exact matching when looking for PHBs in the device tree. With the previous code it was possible to match on pci bridges since we were only matching on device_type. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] FSL: Access PCIe LTSSM register with correct sizeKumar Gala2007-10-08
| | | | | | | The LTSSM register is actual 32-bits wide so we should be doing a dword access. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 85xx: Failure with odd memory sizes and CONFIG_HIGHMEMDale Farnsworth2007-10-08
| | | | | | | | | | | | | | | | | | | The CONFIG_FSL_BOOKE mmu setup code fails when CONFIG_HIGHMEM=y and the 3 fixed TLB entries cannot exactly map the lowmem size. Each TLB entry can map 4MB, 16MB, 64MB or 256MB, so the failure is observed when the kernel lowmem size is not equal to the sum of up to 3 of those values. Normally, memory is sized in nice numbers, but I observed this problem while testing a crash dump kernel. The failure can also be observed by artificially reducing the kernel's main memory via the mem= kernel command line parameter. This commit fixes the problem by setting __initial_memory_limit in adjust_total_lowmem(). Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Add initial MPC8610 HPCD Platform files.Xianghua Xiao2007-10-08
| | | | | | | | | | Add basic board support for the MPC8610 HPCD. This does not include any support the SoC Display or Audio controllers. Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Jon Loelier <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Treat 8610 PCIe host bridge as transparentJason Jin2007-10-08
| | | | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Add initial MPC8610 HPCD Device Tree Source file.Xianghua Xiao2007-10-08
| | | | | | Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] spi: Use fsl_spi instead of mpc83xx_spiPeter Korsgaard2007-10-08
| | | | | | | | According to booting-without-of.txt, compatible should be "fsl_spi" and mode "cpu" or "qe" for the fsl SPI controllers. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] qe: miscellaneous code improvements and fixes to the QE libraryTimur Tabi2007-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes numerous miscellaneous code improvements to the QE library. 1. Remove struct ucc_common and merge ucc_init_guemr() into ucc_set_type() (every caller of ucc_init_guemr() also calls ucc_set_type()). Modify all callers of ucc_set_type() accordingly. 2. Remove the unused enum ucc_pram_initial_offset. 3. Refactor qe_setbrg(), also implement work-around for errata QE_General4. 4. Several printk() calls were missing the terminating \n. 5. Add __iomem where needed, and change u16 to __be16 and u32 to __be32 where appropriate. 6. In ucc_slow_init() the RBASE and TBASE registers in the PRAM were programmed with the wrong value. 7. Add the protocol type to struct us_info and updated ucc_slow_init() to use it, instead of always programming QE_CR_PROTOCOL_UNSPECIFIED. 8. Rename ucc_slow_restart_x() to ucc_slow_restart_tx() 9. Add several macros in qe.h (mostly for slow UCC support, but also to standardize some naming convention) and remove several unused macros. 10. Update ucc_geth.c to use the new macros. 11. Add ucc_slow_info.protocol to specify which QE_CR_PROTOCOL_xxx protcol to use when initializing the UCC in ucc_slow_init(). 12. Rename ucc_slow_pram.rfcr to rbmr and ucc_slow_pram.tfcr to tbmr, since these are the real names of the registers. 13. Use the setbits, clrbits, and clrsetbits where appropriate. 14. Refactor ucc_set_qe_mux_rxtx(). 15. Remove all instances of 'volatile'. 16. Simplify get_cmxucr_reg(); 17. Replace qe_mux.cmxucrX with qe_mux.cmxucr[]. 18. Updated struct ucc_geth because struct ucc_fast is not padded any more. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Update .gitignore for new vdso generated filesKumar Gala2007-10-08
| | | | | | | We now generate vdso[32,64].so.dbg as part of the build so add them to .gitignore Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Fixup MPC8568 dtsKumar Gala2007-10-08
| | | | | | | | The PCI nodes on the MPC8568 dts didn't get moved up to be sibilings of the SOC node when we did that clean up for some reason. Fix that up and some minor whitespace and adjusting the size of the soc reg property. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] mpc8568mds.dts: fix PCIe I/O address space location and sizeAnton Vorontsov2007-10-04
| | | | | | | | | | | According to u-boot/board/mpc8568mds/init.S: LAW(Local Access Window) configuration: 2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB 4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] MPC8568E-MDS: add support for ds1374 rtcAnton Vorontsov2007-10-04
| | | | | | | | | | | | MPC8568E-MDS have DS1374 chip on the I2C bus, thus let's use it. This patch also adds #address-cells and #size-cells to the I2C controllers nodes. p.s. DS1374 rtc class driver is in the -mm tree, its name is rtc-rtc-class-driver-for-the-ds1374.patch. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] fsl_soc: fix uninitialized i2c_board_info structureAnton Vorontsov2007-10-04
| | | | | | | | | i2c_board_info used semi-initialized, causing garbage in the info->flags, and that, in turn, causes various symptoms of i2c malfunctioning, like PEC mismatches. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] cpm: Describe multi-user ram in its own device node.Scott Wood2007-10-04
| | | | | | | | | | | | | | | | | | | | | The way the current CPM binding describes available multi-user (a.k.a. dual-ported) RAM doesn't work well when there are multiple free regions, and it doesn't work at all if the region doesn't begin at the start of the muram area (as the hardware needs to be programmed with offsets into this area). The latter situation can happen with SMC UARTs on CPM2, as its parameter RAM is relocatable, u-boot puts it at zero, and the kernel doesn't support moving it. It is now described with a muram node, similar to QE. The current CPM binding is sufficiently recent (i.e. never appeared in an official release) that compatibility with existing device trees is not an issue. The code supporting the new binding is shared between cpm1 and cpm2, rather than remain separated. QE should be able to use this code as well, once minor fixes are made to its device trees. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Cleaned up whitespace in head_fsl_booke.SKumar Gala2007-10-04
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] fsl_soc: rtc-ds1307 supportPeter Korsgaard2007-10-04
| | | | | | | | | Add support for the I2C devices handled by the rtc-ds1307 driver to of_register_i2c_devices. Cc: G. Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] fsl_soc: Fix trivial printk typo.Peter Korsgaard2007-10-04
| | | | | | | | Fix a trivial printk typo in fsl_soc. Cc: G. Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 8xx: Move softemu8xx.c from arch/ppcScott Wood2007-10-04
| | | | | | | | | | | | | | Previously, Soft_emulate_8xx was called with no implementation, resulting in build failures whenever building 8xx without math emulation. The implementation is copied from arch/ppc to resolve this issue. However, this sort of minimal emulation is not a very good idea other than for compatibility with existing userspaces, as it's less efficient than soft-float and can mislead users into believing they have soft-float. Thus, it is made a configurable option, off by default. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] bootwrapper: adds cuboot for MPC7448HPC2 platformRoy Zang2007-10-04
| | | | | | | | | This patch adds cuboot support for MPC7448HPC2 platform. The cuImage can be used with legacy u-boot without FDT support. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] mpc82xx: Add pq2fads board support.Scott Wood2007-10-04
| | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] mpc82xx: Update mpc8272ads, and factor out PCI and reset.Scott Wood2007-10-04
| | | | | | | | | | | | | | | | 1. PCI and reset are factored out into pq2.c. I renamed them from m82xx to pq2 because they won't work on the Integrated Host Processor line of 82xx chips (i.e. 8240, 8245, and such). 2. The PCI PIC, which is nominally board-specific, is used on multiple boards, and thus is used into pq2ads-pci-pic.c. 3. The new CPM binding is used. 4. General cleanup. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 8xx/wrapper: Embedded Planet EP88xC supportScott Wood2007-10-04
| | | | | | | | This board is also resold by Freescale under the names "QUICCStart MPC885 Evaluation System" and "CWH-PPC-885XN-VE". Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 8xx: mpc885ads cleanupScott Wood2007-10-04
| | | | | | | | It now uses the new CPM binding and the generic pin/clock functions, and has assorted fixes and cleanup. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Document local bus nodes in the device tree, and update cuboot-pq2.Scott Wood2007-10-04
| | | | | | | | | | | | | | | | | | The localbus node is used to describe devices that are connected via a chip select or similar mechanism. The advantages over placing the devices under the root node are that it can be probed without probing other random things under the root, and that the description of which chip select a given device uses can be used to set up mappings if the firmware failed to do so in a useful manner. cuboot-pq2 is updated to match the binding; previously, it called itself chipselect rather than localbus, and used phandle linkage between the actual bus node and the control node (the current agreement is to simply use the fully-qualified address of the control registers, and ignore the overlap with the IMMR node). Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] mpc8272ads: Change references from 82xx_ADS to 8272_ADS.Scott Wood2007-10-04
| | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] mpc82xx: Rename mpc82xx_ads to mpc8272_ads.Scott Wood2007-10-04
| | | | | | | | This is just a rename patch; internal references to mpc82xx_ads will be changed in the next one. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] mpc82xx: Remove a bunch of cruft that duplicates generic ↵Scott Wood2007-10-04
| | | | | | | | | | functionality. m82xx_calibrate_decr(), mpc82xx_ads_show_cpuinfo(), and mpc82xx_halt() do anything useful beyond what the generic code does. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] cpm2: Add cpm2_set_pin().Scott Wood2007-10-04
| | | | | | | | This provides a generic way for board code to set up CPM pins, rather than directly poking magic values into registers. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] cpm2: Add SCCs to cpm2_clk_setup(), and cpm2_smc_clk_setup().Scott Wood2007-10-04
| | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] cpm2: Infrastructure code cleanup.Scott Wood2007-10-04
| | | | | | | | Mostly sparse fixes (__iomem annotations, etc); also, cpm2_immr is used rather than creating many temporary mappings. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 8xx: Set initial memory limit.John Traill2007-10-03
| | | | | | | | | | | | The 8xx can only support a max of 8M during early boot (it seems a lot of 8xx boards only have 8M so the bug was never triggered), but the early allocator isn't aware of this. The following change makes it able to run with larger memory. Signed-off-by: John Traill <john.traill@freescale.com> Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 8xx: Work around CPU15 erratum.Scott Wood2007-10-03
| | | | | | | | | | | | | The CPU15 erratum on MPC8xx chips can cause incorrect code execution under certain circumstances, where there is a conditional or indirect branch in the last word of a page, with a target in the last cache line of the next page. This patch implements one of the suggested workarounds, by forcing a TLB miss whenever execution crosses a page boundary. This is done by invalidating the pages before and after the one being loaded into the TLB in the ITLB miss handler. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 8xx: Add pin and clock setting functions.Scott Wood2007-10-03
| | | | | | | | | | | These let board code set up pins and clocks without having to put magic numbers directly into the registers. The clock function is mostly duplicated from the cpm2 version; hopefully this stuff can be merged at some point. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 8xx: Infrastructure code cleanup.Scott Wood2007-10-03
| | | | | | | | | | | | | | | | | | | | | 1. Keep a global mpc8xx_immr mapping, rather than constantly creating temporary mappings. 2. Look for new fsl,cpm1 and fsl,cpm1-pic names. 3. Always reset the CPM when not using the udbg console; this is required in case the firmware initialized a device that is incompatible with one that the kernel is about to use. 4. Remove some superfluous casts and header includes. 5. Change a usage of IMAP_ADDR to get_immrbase(). 6. Use phys_addr_t, not uint, for dpram_pbase. 7. Various sparse-related fixes, such as __iomem annotations. 8. Remove mpc8xx_show_cpuinfo, which doesn't provide anything useful beyond the generic cpuinfo handler. 9. Move prototypes for 8xx support functions from board files to sysdev/commproc.h. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 8xx: Fix CONFIG_PIN_TLB.Scott Wood2007-10-03
| | | | | | | | 1. Move CONSISTENT_START on 8xx so that it doesn't overlap the IMMR mapping. 2. The wrong register was being loaded into SPRN_MD_RPN. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] bootwrapper: Use fsl_get_immr() in cuboot-pq2.c.Scott Wood2007-10-03
| | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] bootwrapper: Add fsl_get_immr() and 8xx/pq2 clock functions.Scott Wood2007-10-03
| | | | | | | | | | | | | | | | | | | | fsl_get_immr() uses /soc/ranges to determine the immr. mpc885_get_clock() transforms a crystal frequency into a system frequency according to the PLL register settings. pq2_get_clocks() does the same as the above for the PowerQUICC II, except that it produces several different clocks. The mpc8xx/pq2 set_clocks() functions modify common properties in the device tree based on the given clock data. The mpc885/pq2 fixup_clocks() functions call get_clocks(), and pass the results to set_clocks(). Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] bootwrapper: Support all-in-one PCI nodes in cuboot-pq2.Scott Wood2007-10-03
| | | | | | | | | | | | Consensus was reached to put PCI nodes at the root of the tree (and not under /soc), but the phandle to a control node was rejected in favor of simply not worrying about /pci/reg overlapping /soc/ranges. This updates cuboot-82xx to not look for the phandle. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Add early debug console for CPM serial ports.Scott Wood2007-10-03
| | | | | | | | | This code assumes that the ports have been previously set up, with buffers in DPRAM. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Introduce new CPM device bindings.Scott Wood2007-10-03
| | | | | | | | | | | | | | | | | | | | | | | | | | This introduces a new device binding for the CPM and other devices on these boards. Some of the changes include: 1. Proper namespace scoping for Freescale compatibles and properties. 2. Use compatible rather than things like device_type and model to determine which particular variant of a device is present. 3. Give the drivers the relevant CPM command word directly, rather than requiring it to have a lookup table based on device-id, SCC v. SMC, and CPM version. 4. Specify the CPCR and the usable DPRAM region in the CPM's reg property. Boards that do not require the legacy bindings should select CONFIG_PPC_CPM_NEW_BINDING to enable the of_platform CPM devices. Once all existing boards are converted and tested, the config option can become default y to prevent new boards from using the old model. Once arch/ppc is gone, the config option can be removed altogether. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] CPM: Change from fsl,brg-frequency to brg/clock-frequencyScott Wood2007-10-03
| | | | | | | | | | | | | As suggested by David Gibson, now that we have a separate node for the baud rate generators, it's better to use the standard clock-frequency property than a cpm-node-level fsl,brg-frequency property. This patch updates existing places where fsl,brg-frequency is used. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [PPC] Use cpu setup routines from cpu_setup_44x.S for ARCH=ppcPaul Mackerras2007-10-03
| | | | | | | | | | | | | | Commit 8112753bb2c0045398c89d0647792b39805f6d40 made 44x in ARCH=powerpc builds use cpu setup routines in cpu_setup_44x.S, but didn't make a similar change for ARCH=ppc, and consequently the ARCH=ppc builds fail with undefined symbols (since both use the same cputable.c). This fixes it by including cpu_setup_44x.S in the ARCH=ppc builds, and by taking out the now-redundant FPU initialization in arch/ppc/kernel/head_44x.S. Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Uartlite: Revert register io access changesGrant Likely2007-10-03
| | | | | | | | | | | | Reverts commit a15da8eff3627b8368db7f5dd260e5643213d918 This driver is used by devices other than the xilinx opb-uartlite which depend on bytewise access to the registers. The change to 32 bit access does not work on these devices. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 16:09:54 -0500