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* Merge tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreamingLinus Torvalds2015-04-16
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull arch/c6x fixes from Mark Salter. * tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming: c6x: platforms: cache: Export symbol L1P_cache_block_invalidate and L1D_cache_block_writeback c6x: kernel: setup: Export symbol memory_end c6x: kernel: setup: Add screen_info global variable c6x: include: asm: Kbuild: Add generic serial.h c6x: include: asm: dma-mapping: Add dummy dma_sync_single_range_for_device c6x: include: asm: setup: Include "linux/types.h" c6x: asm: Add default flat.h according to xtensa architecture c6x: kernel: setup: Remove 'const' for local variables in machine_init c6x: Makefile: Add -D__linux__ C6x: time: Ensure consistency in __init c6x: kernel: setup: Include "linux/console.h"
| * c6x: platforms: cache: Export symbol L1P_cache_block_invalidate and ↵Chen Gang2015-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | L1D_cache_block_writeback They are needed by other modules, the related error with allmodconfig: MODPOST 3327 modules ERROR: "L1P_cache_block_invalidate" [drivers/misc/lkdtm.ko] undefined! ERROR: "L1D_cache_block_writeback" [drivers/misc/lkdtm.ko] undefined! Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Mark Salter <msalter@redhat.com>
| * c6x: kernel: setup: Export symbol memory_endChen Gang2015-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is needed by several modules, the related error with allmodconfig: MODPOST 3327 modules ERROR: "memory_end" [net/wireless/lib80211_crypt_tkip.ko] undefined! ERROR: "memory_end" [net/sunrpc/sunrpc.ko] undefined! ERROR: "memory_end" [net/sunrpc/auth_gss/rpcsec_gss_krb5.ko] undefined! ERROR: "memory_end" [net/rxrpc/rxkad.ko] undefined! ERROR: "memory_end" [net/mac802154/mac802154.ko] undefined! ERROR: "memory_end" [net/mac80211/mac80211.ko] undefined! ERROR: "memory_end" [net/ipv6/esp6.ko] undefined! ERROR: "memory_end" [net/ipv6/ah6.ko] undefined! ERROR: "memory_end" [net/ipv4/esp4.ko] undefined! ERROR: "memory_end" [net/ipv4/ah4.ko] undefined! ERROR: "memory_end" [net/ceph/libceph.ko] undefined! ERROR: "memory_end" [net/9p/9pnet_virtio.ko] undefined! ERROR: "memory_end" [drivers/usb/wusbcore/wusbcore.ko] undefined! ERROR: "memory_end" [drivers/usb/misc/usbtest.ko] undefined! ERROR: "memory_end" [drivers/usb/core/usbcore.ko] undefined! ERROR: "memory_end" [drivers/target/target_core_file.ko] undefined! ERROR: "memory_end" [drivers/net/wireless/brcm80211/brcmfmac/brcmfmac.ko] undefined! ERROR: "memory_end" [drivers/net/wireless/ath/ath6kl/ath6kl_sdio.ko] undefined! ERROR: "memory_end" [drivers/net/virtio_net.ko] undefined! ERROR: "memory_end" [drivers/net/usb/usbnet.ko] undefined! ERROR: "memory_end" [drivers/net/ppp/ppp_mppe.ko] undefined! ERROR: "memory_end" [drivers/mtd/nand/nand.ko] undefined! ERROR: "memory_end" [drivers/mmc/card/mmc_block.ko] undefined! ERROR: "memory_end" [drivers/crypto/qce/qcrypto.ko] undefined! ERROR: "memory_end" [drivers/block/drbd/drbd.ko] undefined! ERROR: "memory_end" [drivers/block/aoe/aoe.ko] undefined! ERROR: "memory_end" [crypto/tcrypt.ko] undefined! ERROR: "memory_end" [crypto/gcm.ko] undefined! ERROR: "memory_end" [crypto/cts.ko] undefined! ERROR: "memory_end" [crypto/ccm.ko] undefined! ERROR: "memory_end" [crypto/authencesn.ko] undefined! ERROR: "memory_end" [crypto/authenc.ko] undefined! Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Mark Salter <msalter@redhat.com>
| * c6x: kernel: setup: Add screen_info global variableChen Gang2015-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Or can not pass building with allmodconfig: LD init/built-in.o drivers/built-in.o: In function `vgacon_switch': vgacon.c:(.text+0x47f8): undefined reference to `screen_info' vgacon.c:(.text+0x4810): undefined reference to `screen_info' drivers/built-in.o: In function `vgacon_resize': vgacon.c:(.text+0x4ac8): undefined reference to `screen_info' vgacon.c:(.text+0x4acc): undefined reference to `screen_info' drivers/built-in.o: In function `vgacon_save_screen': vgacon.c:(.text+0x4cc8): undefined reference to `screen_info' drivers/built-in.o:vgacon.c:(.text+0x4cd0): more undefined references to `screen_info' follow Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Mark Salter <msalter@redhat.com>
| * c6x: include: asm: Kbuild: Add generic serial.hChen Gang2015-03-26
| | | | | | | | | | | | | | | | | | | | Or it will cause building break with allmodconfig: CC [M] drivers/tty/serial/8250/8250_core.o drivers/tty/serial/8250/8250_core.c:102:24: fatal error: asm/serial.h: No such file or directory Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Mark Salter <msalter@redhat.com>
| * c6x: include: asm: dma-mapping: Add dummy dma_sync_single_range_for_deviceChen Gang2015-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | c6x does not implement get_dma_ops() for dma-mapping-common.h. And in dma-mapping-common.h, dma_sync_single_range_for_device() may be dummy. So c6x can just define a dummy function for allmodconfig building. CC [M] drivers/net/ethernet/micrel/ks8851.o drivers/net/ethernet/micrel/ks8842.c: In function 'ks8842_tx_frame_dma': drivers/net/ethernet/micrel/ks8842.c:453:2: error: implicit declaration of function 'dma_sync_single_range_for_device' [-Werror=implicit-function-declaration] dma_sync_single_range_for_device(adapter->dev, ^ Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Mark Salter <msalter@redhat.com>
| * c6x: include: asm: setup: Include "linux/types.h"Chen Gang2015-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some modules may assume "asm/setup.h" already include all headers which needed by itself. So need let "asm/setup.h" include "linux/types.h", the related error: C [M] drivers/input/joydev.o In file included from include/asm-generic/page.h:23:0, from ./arch/c6x/include/asm/page.h:9, from include/asm-generic/io.h:14, from arch/c6x/include/generated/asm/io.h:1, from drivers/input/joydev.c:15: ./arch/c6x/include/asm/setup.h:17:27: error: unknown type name 'phys_addr_t' extern int c6x_add_memory(phys_addr_t start, unsigned long size); ^ Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Mark Salter <msalter@redhat.com>
| * c6x: asm: Add default flat.h according to xtensa architectureChen Gang2015-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | For supporting uClinux flat-format executables, c6x needs to define the fewest features to support it, at present, xtensa architecture has the fewest feature for it, so just copy xtensa flat.h. The related error: CC fs/binfmt_flat.o In file included from fs/binfmt_flat.c:36:0: include/linux/flat.h:12:22: fatal error: asm/flat.h: No such file or directory Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Mark Salter <msalter@redhat.com>
| * c6x: kernel: setup: Remove 'const' for local variables in machine_initChen Gang2015-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | early_init_dt_scan() accepts "void *", the related warning: CC arch/c6x/kernel/setup.o arch/c6x/kernel/setup.c: In function 'machine_init': arch/c6x/kernel/setup.c:290:21: warning: passing argument 1 of 'early_init_dt_scan' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] early_init_dt_scan(fdt); ^ In file included from arch/c6x/kernel/setup.c:19:0: include/linux/of_fdt.h:75:13: note: expected 'void *' but argument is of type 'const void *' extern bool early_init_dt_scan(void *params); ^ Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Mark Salter <msalter@redhat.com>
| * c6x: Makefile: Add -D__linux__Chen Gang2015-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For gcc5 c6x raw compiler, at present, it may not define __linux__, so c6x kernel still needs to define __linux__ just like another archs have done. The related error: CC [M] fs/coda/psdev.o In file included from include/linux/coda.h:64:0, from fs/coda/psdev.c:45: include/uapi/linux/coda.h:221:2: error: unknown type name 'u_quad_t' u_quad_t va_size; /* file size in bytes */ ^ include/uapi/linux/coda.h:229:2: error: unknown type name 'u_quad_t' u_quad_t va_bytes; /* bytes of disk space held by file */ ^ include/uapi/linux/coda.h:230:2: error: unknown type name 'u_quad_t' u_quad_t va_filerev; /* file modification number */ ^ Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Mark Salter <msalter@redhat.com>
| * C6x: time: Ensure consistency in __initNishanth Menon2015-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | time_init invokes timer64_init (which is __init annotation) since all of these are invoked at init time, lets maintain consistency by ensuring time_init is marked appropriately as well. This fixes the following warning with CONFIG_DEBUG_SECTION_MISMATCH=y WARNING: vmlinux.o(.text+0x3bfc): Section mismatch in reference from the function time_init() to the function .init.text:timer64_init() The function time_init() references the function __init timer64_init(). This is often because time_init lacks a __init annotation or the annotation of timer64_init is wrong. Fixes: 546a39546c64 ("C6X: time management") Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com>
| * c6x: kernel: setup: Include "linux/console.h"Chen Gang2015-03-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Or c6x will cause building break for allmodconfig, the related error: CC arch/c6x/kernel/setup.o arch/c6x/kernel/setup.c: In function 'setup_arch': arch/c6x/kernel/setup.c:433:2: error: 'conswitchp' undeclared (first use in this function) conswitchp = &dummy_con; ^ arch/c6x/kernel/setup.c:433:2: note: each undeclared identifier is reported only once for each function it appears in arch/c6x/kernel/setup.c:433:16: error: 'dummy_con' undeclared (first use in this function) conswitchp = &dummy_con; ^ Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> [removed unnecessary #ifdef around include] Signed-off-by: Mark Salter <msalter@redhat.com>
* | Merge tag 'stable/for-linus-4.1-rc0-tag' of ↵Linus Torvalds2015-04-16
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip Pull xen features and fixes from David Vrabel: - use a single source list of hypercalls, generating other tables etc. at build time. - add a "Xen PV" APIC driver to support >255 VCPUs in PV guests. - significant performance improve to guest save/restore/migration. - scsiback/front save/restore support. - infrastructure for multi-page xenbus rings. - misc fixes. * tag 'stable/for-linus-4.1-rc0-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip: xen/pci: Try harder to get PXM information for Xen xenbus_client: Extend interface to support multi-page ring xen-pciback: also support disabling of bus-mastering and memory-write-invalidate xen: support suspend/resume in pvscsi frontend xen: scsiback: add LUN of restored domain xen-scsiback: define a pr_fmt macro with xen-pvscsi xen/mce: fix up xen_late_init_mcelog() error handling xen/privcmd: improve performance of MMAPBATCH_V2 xen: unify foreign GFN map/unmap for auto-xlated physmap guests x86/xen/apic: WARN with details. x86/xen: Provide a "Xen PV" APIC driver to support >255 VCPUs xen/pciback: Don't print scary messages when unsupported by hypervisor. xen: use generated hypercall symbols in arch/x86/xen/xen-head.S xen: use generated hypervisor symbols in arch/x86/xen/trace.c xen: synchronize include/xen/interface/xen.h with xen xen: build infrastructure for generating hypercall depending symbols xen: balloon: Use static attribute groups for sysfs entries xen: pcpu: Use static attribute groups for sysfs entry
| * | xen/privcmd: improve performance of MMAPBATCH_V2David Vrabel2015-03-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the IOCTL_PRIVCMD_MMAPBATCH_V2 (and older V1 version) map multiple frames at a time rather than one at a time, despite the pages being non-consecutive GFNs. xen_remap_foreign_mfn_array() is added which maps an array of GFNs (instead of a consecutive range of GFNs). Since per-frame errors are returned in an array, privcmd must set the MMAPBATCH_V1 error bits as part of the "report errors" phase, after all the frames are mapped. Migrate times are significantly improved (when using a PV toolstack domain). For example, for an idle 12 GiB PV guest: Before After real 0m38.179s 0m26.868s user 0m15.096s 0m13.652s sys 0m28.988s 0m18.732s Signed-off-by: David Vrabel <david.vrabel@citrix.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
| * | xen: unify foreign GFN map/unmap for auto-xlated physmap guestsDavid Vrabel2015-03-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Auto-translated physmap guests (arm, arm64 and x86 PVHVM/PVH) map and unmap foreign GFNs using the same method (updating the physmap). Unify the two arm and x86 implementations into one commont one. Note that on arm and arm64, the correct error code will be returned (instead of always -EFAULT) and map/unmap failure warnings are no longer printed. These changes are required if the foreign domain is paging (-ENOENT failures are expected and must be propagated up to the caller). Signed-off-by: David Vrabel <david.vrabel@citrix.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
| * | x86/xen/apic: WARN with details.Konrad Rzeszutek Wilk2015-03-16
| | | | | | | | | | | | | | | | | | | | | | | | We should not be writting to the APIC registers under Xen PV. But if we do instead of just giving an blanket warning - include some details to help troubleshoot. Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
| * | x86/xen: Provide a "Xen PV" APIC driver to support >255 VCPUsKonrad Rzeszutek Wilk2015-03-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of mangling the default APIC driver, provide a Xen PV guest specific one that explicitly provides appropriate methods. This allows use to report that all APIC IDs are valid, allowing dom0 to boot with more than 255 VCPUs. Since the probe order of APIC drivers is link dependent, we add in an late probe function to change to the Xen PV if it hadn't been done during bootup. Suggested-by: David Vrabel <david.vrabel@citrix.com> Reported-by: Cathy Avery <cathy.avery@oracle.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
| * | xen: use generated hypercall symbols in arch/x86/xen/xen-head.SJuergen Gross2015-03-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of manually list each hypercall in arch/x86/xen/xen-head.S use the auto generated symbol list. This also corrects the wrong address of xen_hypercall_mca which was located 32 bytes higher than it should. Symbol addresses have been verified to match the correct ones via objdump output. Based-on-patch-by: Jan Beulich <jbeulich@suse.com> Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: David Vrabel <david.vrabel@citrix.com> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
| * | xen: use generated hypervisor symbols in arch/x86/xen/trace.cJuergen Gross2015-03-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of manually list all hypervisor calls in arch/x86/xen/trace.c use the auto generated list. Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: David Vrabel <david.vrabel@citrix.com> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
| * | xen: synchronize include/xen/interface/xen.h with xenJuergen Gross2015-03-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | The header include/xen/interface/xen.h doesn't contain all definitions from Xen's version of that header. Update it accordingly. Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: David Vrabel <david.vrabel@citrix.com> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
| * | xen: build infrastructure for generating hypercall depending symbolsJuergen Gross2015-03-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Today there are several places in the kernel which build tables containing one entry for each possible Xen hypercall. Create an infrastructure to be able to generate these tables at build time. Based-on-patch-by: Jan Beulich <jbeulich@suse.com> Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: David Vrabel <david.vrabel@citrix.com> Acked-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
* | | Merge tag 'arm64-upstream' of ↵Linus Torvalds2015-04-16
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Will Deacon: "Here are the core arm64 updates for 4.1. Highlights include a significant rework to head.S (allowing us to boot on machines with physical memory at a really high address), an AES performance boost on Cortex-A57 and the ability to run a 32-bit userspace with 64k pages (although this requires said userspace to be built with a recent binutils). The head.S rework spilt over into KVM, so there are some changes under arch/arm/ which have been acked by Marc Zyngier (KVM co-maintainer). In particular, the linker script changes caused us some issues in -next, so there are a few merge commits where we had to apply fixes on top of a stable branch. Other changes include: - AES performance boost for Cortex-A57 - AArch32 (compat) userspace with 64k pages - Cortex-A53 erratum workaround for #845719 - defconfig updates (new platforms, PCI, ...)" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (39 commits) arm64: fix midr range for Cortex-A57 erratum 832075 arm64: errata: add workaround for cortex-a53 erratum #845719 arm64: Use bool function return values of true/false not 1/0 arm64: defconfig: updates for 4.1 arm64: Extract feature parsing code from cpu_errata.c arm64: alternative: Allow immediate branch as alternative instruction arm64: insn: Add aarch64_insn_decode_immediate ARM: kvm: round HYP section to page size instead of log2 upper bound ARM: kvm: assert on HYP section boundaries not actual code size arm64: head.S: ensure idmap_t0sz is visible arm64: pmu: add support for interrupt-affinity property dt: pmu: extend ARM PMU binding to allow for explicit interrupt affinity arm64: head.S: ensure visibility of page tables arm64: KVM: use ID map with increased VA range if required arm64: mm: increase VA range of identity map ARM: kvm: implement replacement for ld's LOG2CEIL() arm64: proc: remove unused cpu_get_pgd macro arm64: enforce x1|x2|x3 == 0 upon kernel entry as per boot protocol arm64: remove __calc_phys_offset arm64: merge __enable_mmu and __turn_mmu_on ...
| * | | arm64: fix midr range for Cortex-A57 erratum 832075Bo Yan2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Register MIDR_EL1 is masked to get variant and revision fields, then compared against midr_range_min and midr_range_max when checking whether CPU is affected by any particular erratum. However, variant and revision fields in MIDR_EL1 are separated by 16 bits, so the min and max of midr range should be constructed accordingly, otherwise the patch will not be applied when variant field is non-0. Cc: stable@vger.kernel.org # 3.19+ Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Bo Yan <byan@nvidia.com> [will: use MIDR_VARIANT_SHIFT to construct upper bound] Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: errata: add workaround for cortex-a53 erratum #845719Will Deacon2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running a compat (AArch32) userspace on Cortex-A53, a load at EL0 from a virtual address that matches the bottom 32 bits of the virtual address used by a recent load at (AArch64) EL1 might return incorrect data. This patch works around the issue by writing to the contextidr_el1 register on the exception return path when returning to a 32-bit task. This workaround is patched in at runtime based on the MIDR value of the processor. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: Use bool function return values of true/false not 1/0Joe Perches2015-03-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the normal return values for bool functions Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: defconfig: updates for 4.1Will Deacon2015-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable a few useful options in our defconfig: - New platform support (exynos7, seattle, tegra132) - SKY2 (ethernet in newer revisions of Juno) - Xgene reboot support - Virtio-pci for kvmtool and qemu - EFIVAR_FS (previously selected as a module) - NFSv4 Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: Extract feature parsing code from cpu_errata.cMarc Zyngier2015-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we detect more architectural features at runtime, it makes sense to reuse the existing framework whilst avoiding to call a feature an erratum... This patch extract the core capability parsing, moves it into a new file (cpufeature.c), and let the CPU errata detection code use it. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: alternative: Allow immediate branch as alternative instructionMarc Zyngier2015-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since all immediate branches are PC-relative on Aarch64, these instructions cannot be used as an alternative with the simplistic approach we currently have (the immediate has been computed from the .altinstr_replacement section, and end-up being completely off if we insert it directly). This patch handles the b and bl instructions in a different way, using the insn framework to recompute the immediate, and generate the right displacement. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: insn: Add aarch64_insn_decode_immediateMarc Zyngier2015-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patching an instruction sometimes requires extracting the immediate field from this instruction. To facilitate this, and avoid potential duplication of code, add aarch64_insn_decode_immediate as the reciprocal to aarch64_insn_encode_immediate. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | Merge branch 'aarch64/kvm-bounce-page' into aarch64/for-next/coreWill Deacon2015-03-27
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just as we thought we'd fixed this, another old linker reared its ugly head trying to build linux-next. Unfortunately, it's the linker binary provided on kernel.org, so give up trying to be clever and align the hyp page to 4k.
| | * | | ARM: kvm: round HYP section to page size instead of log2 upper boundArd Biesheuvel2015-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Older binutils do not support expressions involving the values of external symbols so just round up the HYP region to the page size. Tested-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> [will: when will this ever end?!] Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | | Merge branch 'aarch64/kvm-bounce-page' into aarch64/for-next/coreWill Deacon2015-03-25
| |\| | | | | | | | | | | | | | | | | | | | | | | linux-next testing found a bug with the PROVIDE keyword and older versions of binutils, so Ard has fixed that here.
| | * | | ARM: kvm: assert on HYP section boundaries not actual code sizeArd Biesheuvel2015-03-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using ASSERT() with an expression that involves a symbol that is only supplied through a PROVIDE() definition in the linker script itself is apparently not supported by some older versions of binutils. So instead, rewrite the expression so that only the section boundaries __hyp_idmap_text_start and __hyp_idmap_text_end are used. Note that this reverts the fix in 06f75a1f6200 ("ARM, arm64: kvm: get rid of the bounce page") for the ASSERT() being triggered erroneously when unrelated linker emitted veneers happen to end up in the HYP idmap region. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | | arm64: head.S: ensure idmap_t0sz is visibleMark Rutland2015-03-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We write idmap_t0sz with SCTLR_EL1.{C,M} clear, but we only have the guarnatee that the kernel Image is clean, not invalid in the caches, and therefore we might read a stale value once the MMU is enabled. This patch ensures we invalidate the corresponding cacheline after the write as we do for all other data written before we set SCTLR_EL1.{C.M}, guaranteeing that the value will be visible later. We rely on the DSBs in __create_page_tables to complete the maintenance. Signed-off-by: Mark Rutland <mark.rutland@arm.com> CC: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | | arm64: pmu: add support for interrupt-affinity propertyWill Deacon2015-03-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, the PMU devicetree bindings have expected SPIs to be listed in order of *logical* CPU number. This is problematic for bootloaders, especially when the boot CPU (logical ID 0) isn't listed first in the devicetree. This patch adds a new optional property, interrupt-affinity, to the PMU node which allows the interrupt affinity to be described using a list of phandled to CPU nodes, with each entry in the list corresponding to the SPI at the same index in the interrupts property. Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | | arm64: head.S: ensure visibility of page tablesMark Rutland2015-03-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After writing the page tables, we use __inval_cache_range to invalidate any stale cache entries. Strongly Ordered memory accesses are not ordered w.r.t. cache maintenance instructions, and hence explicit memory barriers are required to provide this ordering. However, __inval_cache_range was written to be used on Normal Cacheable memory once the MMU and caches are on, and does not have any barriers prior to the DC instructions. This patch adds a DMB between the page tables being written and the corresponding cachelines being invalidated, ensuring that the invalidation makes the new data visible to subsequent cacheable accesses. A barrier is not required before the prior invalidate as we do not access the page table memory area prior to this, and earlier barriers in preserve_boot_args and set_cpu_boot_mode_flag ensures ordering w.r.t. any stores performed prior to entering Linux. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Fixes: c218bca74eeafa2f ("arm64: Relax the kernel cache requirements for boot") Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | | arm64: KVM: use ID map with increased VA range if requiredArd Biesheuvel2015-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies the HYP init code so it can deal with system RAM residing at an offset which exceeds the reach of VA_BITS. Like for EL1, this involves configuring an additional level of translation for the ID map. However, in case of EL2, this implies that all translations use the extra level, as we cannot seamlessly switch between translation tables with different numbers of translation levels. So add an extra translation table at the root level. Since the ID map and the runtime HYP map are guaranteed not to overlap, they can share this root level, and we can essentially merge these two tables into one. Tested-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | | arm64: mm: increase VA range of identity mapArd Biesheuvel2015-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The page size and the number of translation levels, and hence the supported virtual address range, are build-time configurables on arm64 whose optimal values are use case dependent. However, in the current implementation, if the system's RAM is located at a very high offset, the virtual address range needs to reflect that merely because the identity mapping, which is only used to enable or disable the MMU, requires the extended virtual range to map the physical memory at an equal virtual offset. This patch relaxes that requirement, by increasing the number of translation levels for the identity mapping only, and only when actually needed, i.e., when system RAM's offset is found to be out of reach at runtime. Tested-by: Laura Abbott <lauraa@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | | Merge branch 'aarch64/kvm-bounce-page' into aarch64/for-next/coreWill Deacon2015-03-23
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework of the KVM HYP bounce page from Ard Biesheuvel. Subsequent arm64 idmap rework depends on this, so merge it here with Marc Zyngier's blessing (kvm-arm co-maintainer).
| | * | | ARM: kvm: implement replacement for ld's LOG2CEIL()Ard Biesheuvel2015-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 06f75a1f6200 ("ARM, arm64: kvm: get rid of the bounce page") uses ld's builtin function LOG2CEIL() to align the KVM init code to a log2 upper bound of its size. However, this function turns out to be a fairly recent addition to binutils, which breaks the build for older toolchains. So instead, implement a replacement LOG2_ROUNDUP() using the C preprocessor. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * | | ARM, arm64: kvm: get rid of the bounce pageArd Biesheuvel2015-03-19
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HYP init bounce page is a runtime construct that ensures that the HYP init code does not cross a page boundary. However, this is something we can do perfectly well at build time, by aligning the code appropriately. For arm64, we just align to 4 KB, and enforce that the code size is less than 4 KB, regardless of the chosen page size. For ARM, the whole code is less than 256 bytes, so we tweak the linker script to align at a power of 2 upper bound of the code size Note that this also fixes a benign off-by-one error in the original bounce page code, where a bounce page would be allocated unnecessarily if the code was exactly 1 page in size. On ARM, it also fixes an issue with very large kernels reported by Arnd Bergmann, where stub sections with linker emitted veneers could erroneously trigger the size/alignment ASSERT() in the linker script. Tested-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: proc: remove unused cpu_get_pgd macroWill Deacon2015-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | cpu_get_pgd isn't used anywhere and is Probably Not What You Want. Remove it before anybody decides to use it. Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: enforce x1|x2|x3 == 0 upon kernel entry as per boot protocolArd Biesheuvel2015-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the arm64 boot protocol, registers x1 to x3 should be zero upon kernel entry, and non-zero values are reserved for future use. This future use is going to be problematic if we never enforce the current rules, so start enforcing them now, by emitting a warning if non-zero values are detected. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: remove __calc_phys_offsetArd Biesheuvel2015-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This removes the function __calc_phys_offset and all open coded virtual to physical address translations using the offset kept in x28. Instead, just use absolute or PC-relative symbol references as appropriate when referring to virtual or physical addresses, respectively. Tested-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: merge __enable_mmu and __turn_mmu_onArd Biesheuvel2015-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling of the MMU is split into two functions, with an align and a branch in the middle. On arm64, the entire kernel Image is ID mapped so this is really not necessary, and we can just merge it into a single function. Also replaces an open coded adrp/add reference to __enable_mmu pair with adr_l. Tested-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: use PC-relative reference for secondary_holding_pen_releaseArd Biesheuvel2015-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the confusing virtual/physical address arithmetic with a simple PC-relative reference. Tested-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: remove __switch_data object from head.SArd Biesheuvel2015-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This removes the confusing __switch_data object from head.S, and replaces it with standard PC-relative references to the various symbols it encapsulates. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: remove processor_idArd Biesheuvel2015-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The global processor_id is assigned the MIDR_EL1 value of the boot CPU in the early init code, but is never referenced afterwards. As the relevance of the MIDR_EL1 value of the boot CPU is debatable anyway, especially under big.LITTLE, let's remove it before anyone starts using it. Tested-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: add macros for common adrp usagesArd Biesheuvel2015-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The adrp instruction is mostly used in combination with either an add, a ldr or a str instruction with the low bits of the referenced symbol in the 12-bit immediate of the followup instruction. Introduce the macros adr_l, ldr_l and str_l that encapsulate these common patterns. Tested-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | arm64: Get rid of struct cpu_tableMarc Zyngier2015-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct cpu_table is an artifact left from the (very) early days of the arm64 port, and its only real use is to allow the most beautiful "AArch64 Processor" string to be displayed at boot time. Really? Yes, really. Let's get rid of it. In order to avoid another BogoMips-gate, the aforementioned string is preserved. Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 00:32:28 -0500